TotalTest Project Status
Project File:	TotalTest.ise	Implementation State:	New
Module Name:	FPGA_ctrl	Errors:
Target Device:	xc3s50a-4vq100	Warnings:
Product Version:	ISE 11.3	Routing Results:
Design Goal:	Balanced	Timing Constraints:
Design Strategy:	Xilinx Default (unlocked)	Final Timing Score:

 

Detailed Reports						[-]
Report Name	Status	Generated	Errors	Warnings	Infos
Synthesis Report
Translation Report
Map Report
Place and Route Report
Power Report
Post-PAR Static Timing Report
Bitgen Report

 

Secondary Reports			[-]
Report Name	Status	Generated
ISIM Simulator Log	Current	Tue Oct 13 18:45:14 2009

Date Generated: 11/06/2009 - 15:49:17