UConn PAN - User contributions [en]

Mentor Connection 2009

2010-05-07T17:15:08Z

Underwood: added youtube links

[[Image:Ryan and David and Austin 7-2009.jpg|400px|right]]

* Ryan Roussel
** PowerPoint Presentation: [http://zeus.phys.uconn.edu/~jonesrt/students/MentorConnection/2009/MentorConnection-2009_3.ppt Probing the Forces Between Quarks with Photons]
** Video
*** [http://www.youtube.com/watch?v=GszT3gLXf3w Part 1]
*** [http://www.youtube.com/watch?v=05rYPKP58bc Part 2]
* Austin Antoniou
** PowerPoint Presentation: [http://zeus.phys.uconn.edu/~jonesrt/students/MentorConnection/2009/MentorConnection-2009_2.ppt Predicting Vibration Frequencies of the Diamond Wafer]
** Video
*** [http://www.youtube.com/watch?v=CsliuSZ4zb0 Part 1]
*** [http://www.youtube.com/watch?v=5irckx_5Bfg Part 2]
* David Smith
** PowerPoint Presentation: [http://zeus.phys.uconn.edu/~jonesrt/students/MentorConnection/2009/MentorConnection-2009_1.ppt Results and Comparison with Simple Effective Theory]
** Video
*** [http://www.youtube.com/watch?v=ZelvgYFcfu8 Part 1]
*** [http://www.youtube.com/watch?v=KIxbOCqmZZs Part 2]

Woody Underwood

2010-03-18T21:41:05Z

Underwood: /* Project Design Snapshot */

== About Me ==
My name is Woody Underwood. I'm a junior entering my seventh semester in the physics program at UConn. Since the summer of 2008, I've been working in the lab of Dr. Richard Jones designing electronics for the US Department of Energy's GlueX experiment. My assignment is to develop three circuit boards that work together to tag photons coming from the diamond radiator. My circuitry essentially measures (indirectly) the energy of these photons in order to determine if they are of interest to GlueX. The three boards I am designing consist of a digital board, an analog board, and a connecting backplane.

== About My Circuitry ==
Electrons leaving the diamond radiator are deflected by a magnetic field into an array of scintillating fibres, producing photons. Wave guides carry these photons to SiPMs (silicon photomultipliers) mounted on the analog circuit board. The analog board contains transimpedance amplifiers and summing circuitry to condition the signals for digitization.

The sensitivity of the SiPMs and the gain of the amplifiers on the analog board are controlled both by the power supply VCC and bias voltages supplied from the digital board. The digital board receives commands from a computer via ethernet, and uses a 32-channel DAC to output appropriate bias voltages to the SiPMs on the analog board. The digital and analog boards are connected by means of a backplane, which is also responsible for providing power and grounds to both boards.

== Summary of Fall 2008 Work ==
All circuitry design work was done using Altium Designer. The digital board was the first to be designed. The first step in designing the digital board was to review the list of key components that had already been selected by Igor and Dr. Jones. These components included such things as the Xilinx Spartan-3A FPGA, and the Analog Devices AD5535 DAC. I began by looking through datasheets for these components to find out their needs, including power and decoupling requirements. I reviewed the pinout diagrams, and then looked through Altium’s standard libraries to find components that matched (in many cases the particular component I was looking for was not in the library, but a similar footprint or schematic symbol was). For components without matching schematic symbols, I entered pinout information from the datasheets into Microsoft Excel, using a layout compatible with Altium’s Smart Grid Insert function. Then, I was able to literally copy and paste pin information from Excel into Altium to generate the schematic symbols I needed.

Once I had appropriate schematic symbols available for all parts, I began making appropriate connections in the schematic view in Altium. Though tedious, this task was not exceedingly difficult. I finished the schematics in several days, and then moved on to PCB design. I switched into Altium's PCB view. The footprints corresponding to the components I used in the schematics were automatically inserted by Altium. My job was then to position these components in logical places on the board and make all of the connections corresponding to the nets defined in the schematics.

Due to the large number of components being placed in the limited space available on the digital board, Altium's auto-router proved completely useless. Therefore, I routed the board manually. Despite Altium's revolutionary convergence of schematic and PCB design into a single program, this was no easy task. During the routing process, I had to take into account not only the connections that had to be made, but also things such as avoiding crosstalk and minimizing trace length for sensitive components. I was able to complete routing after several weeks of work. The digital board design has since been completed and the board has been printed. It is currently awaiting assembly.

The analog board provided a host of new challenges. The basic schematic for the transimpedance amplifier on the analog board was completed by Igor and Dr. Jones before the semester. Inputting the schematic into Altium was not very difficult. However, one problem I encountered was that the analog board contains 32 copies of this amplifier circuitry. After failing to find any way to insert multiple copies of both the schematic and its corresponding PCB layout, I decided to insert only single copies of each schematic page, and copy and paste the PCB layout to produce 32 copies of the amplifier circuitry. At first this seemed like a quick and easy way to get all of the necessary circuitry onto the PCB. However, I eventually discovered that this procedure would lead to major problems with the board assembly process (due to duplicate component designators, and for other reasons). Fortunately, this revelation came around the same time that Igor and Dr. Jones found a problem with the performance of the amplifier circuit. Making any changes to the amplifier circuit at this point will require a major reroute of all the traces on the analog board. Since the board needs to be completely redesigned anyway, this will give me another chance to find a way to match schematics with all 32 copies of the amplifier circuitry.

The backplane design is currently in progress. It should be relatively easy to complete. All that remains to be done is to add the LEMO connectors and power inputs. The board is simple enough that it can be routed completely by the auto-router, though a quick hand routing will probably be superior. I anticipate that I can complete the backplane with a few days of concentrated work over break.

Included below are links to the files I have been working on. Included in the files for each board is a "SmartPDF," viewable in Adobe Reader. For those without Altium Designer, these may be the best files to look at. They include complete schematics and PCB layout, and are also indexed by component.

Any questions about the tagger circuitry can be directed to me at [mailto:mitchell.underwood@uconn.edu mitchell.underwood@uconn.edu]

=== Related Files ===
* [http://zeus.phys.uconn.edu/halld/tagger/electronics/design-12-2008/DigitalBoard.zip DigitalBoard.zip]:
**Altium Project File (SiPM Control Board.PrjPcb)
**Altium PCB Layout File (Prototype1.PcbDoc)
**Altium Schematic Files (*.SchDoc)
**Altium Annotation Document (SiPM Control Board.Annotation)
***Not used, but generated by Altium when opening the project
**Altium PRJPCBSTRUCTURE File (SiPM Control Board.PRJPCBSTRUCTURE)
***Not used, but generated by Altium when opening the project)
**“SmartPDF” of the board and schematics (SiPM Control Board.pdf)
***Can be used to explore the PCB layout and schematics without needing Altium
**Pick and Place File for board population (Pick Place for Prototype1.txt)
***Used by board assembler
**NC Drill Files (Prototype1.txt, Prototype1.DRR, Prototype1.DRL)
***Used by board printer
**Gerber Files for all layers (in folder Gerbers)
***Used by board printer
**Altium CAMtastic file (CAMtastic4 FINAL.Cam)
***Basically a composite of all the Gerbers
**Photos and 3D rendering of populated board
***In folder “Photos”
**EMF Files showing different layers
***In folder “EMF Renderings”
**AutoCad File of PCB (Prototype1 Autocad.DWG)
**Altium Library of Custom Footprints for Digital Board (GlueX IC Library.SchLib)
***Current as of completion of digital board
***This library has since been updated for the backplane

*[http://zeus.phys.uconn.edu/halld/tagger/electronics/design-12-2008/Analog%20Board%2020081211.zip Analog Board 20081211.zip]:
**Altium Project File (AnalogBoard.PrjPcb)
**Altium PCB Layout File (AnalogBoardPCB.PcbDoc)
**Altium Schematic Files (Amplifer1.SchDoc, Summer.SchDoc)
**“SmartPDF” of the board and schematics (AnalogBoard.pdf)
**Altium Component Definition for SiPM (SiPM Library.PcbLib)
***Contains part footprint and pin information for the SiPM component

*[http://zeus.phys.uconn.edu/halld/tagger/electronics/design-12-2008/Backplane%2020081211.zip Backplane 20081211.zip]
**Altium Project File (Backplane.PrjPcb)
**Alitum PCB Layout File (Backplane.PcbDoc)
**Altium Schematic Files (Analog Connector.SchDoc, Digital Connector.SchDoc)
***Analog Connector = Eurocard to analog board
***Digital Connector = Eurocard to digital board, +3.3V voltage regulator, and location identifier jumper
***LEMO connections not yet included in these schematics
**“SmartPDF” of the board and schematics (Backplane.pdf)
**Pin layout files used to define pinouts for custom components (Pin Layout, 96 pin connector.xlsx, Pinouts.xlsx)
***Pin Layout, 96 pin connector = pinout definition for 96 pin Eurocard connector
***Pinouts.xlsx = pinout definitions for digital board, which were reused for the 48 pin digital Eurocard receptacle on backplane
**Altium Library of Custom Components (GlueX IC Library.SchLib)
***UPDATED to include new backplane components
***An older version of this library was used for the digital board

==Summary of Spring 2009 Work==

At the end of the fall semester, Dr. Jones, Igor, and I determined that the amplifier/summing circuit we had designed simply didn’t have sufficient performance characteristics to be useful for GlueX. During the beginning of the spring semester, Igor came up with a new design, utilizing more transistors, to provide the high gain, fast response, picosecond resolution amplifier that we needed. The design performed flawlessly both in MatLab simulations and in a handmade single channel prototype. The first of my goals for the spring 2009 semester was to capture the schematic for this new amplifier into Altium designer, and layout a new amplifier board. The second of my goals, of course, was to complete production of the digital control board prototypes.

[[Image:Digital Board, Populated.JPG|thumb|The populated digital board, with a tube of Chap-BlockTM for size comparison.]] Since the fall semester left us with three unpopulated digital control board PCBs, getting those PCBs assembled with their components was the first priority. I began the semester by tracking down all of the components we needed (some of which were selected at the end of the fall semester), and making appropriate substitutions for components whose availability had changed since the fall. In the process of selecting these components, I noticed several places where it seemed like power consumption on the board may be somewhat high. To fix this, I developed a spreadsheet in Microsoft Excel that calculates optimal resistor values to use for to obtain a specified voltage divider stiffness. With this tool, I was able to optimize power consumption across the board, and select appropriate components. Once all components had been selected, ordered, and received, we sent the order out to Screamin’ Circuits for assembly. The boards came back several weeks later, and are currently awaiting testing by some undergraduates who will be in the lab this summer.

While Igor was finalizing his amplifier/summing circuit, I worked briefly on design of the backplane. A number of details regarding trace impedance and board dimensions were ironed out. Nonetheless, many problems still remain which I will need to tackle over the summer. The first of these problems is that we have yet to find an appropriate low cost coaxial connector to route signals off the backplane. In addition, screws with which to mount the backplane to the tagger must be selected so that appropriate holes can be created for them on the PCB.

Once we were satisfied that the amplifier/summing circuit performed as required, I shifted work from the backplane to the amplifier board. Around the same time, I began working on a poster to present my work at the Frontiers in Undergraduate Research Exhibition held during Open House Weekend here at UConn. If you’re interested in my poster, check it out here.

[[Image:Amplifier-Summer-Laid-out.gif|thumb|A prototype layout of 5 amplifier channels and a summing circuit. Actual size is ~1.6" tall. Areas in green represent problems to be resolved over summer 2009. A prototype amplifier with no green spots has been designed and will be replicated to this design soon.]] To start the amplifier/summing circuit project, I searched high and low for information about how to handle multi-channel designs in Altium. Not surprisingly, the first Google result on the query “multichannel design Altium” had everything I was missing during the fall when I was trying to lay out the original amplifier circuit. Using my new knowledge of Altium’s multichannel capabilities, I captured Igor’s new design into the schematics editor of Altium Designer. With proper nested schematic sheets, the entire 30 channel amplifier/6 channel summer design was compressed into just 4 schematic sheets, vs. the ~40 or so that would have been required had I laid out the complete schematics of the old design.

I spent about a week and a half trying to figure out how to handle nesting independent nets from a repeated subsheet into another repeated subsheet which also produces independent nets from the nets of the first sheet. This sounds somewhat complicated, and I suppose perhaps it is a somewhat unique situation, since none of the ~5 sample multichannel projects included with Altium had such a construction in them. Basically, each summing circuit has five amplifier subcircuits, each of which puts out its own signal independent of the other four. From the perspective of the entire board, there are 6 summers, each of which has five independent signals coming from the amplifiers, and one summed signal. Determining how to get Altium to realize the proper connections from each individual amplifier, through that amplifier’s summer, to the main schematic was a complicated mess of naming conventions, but eventually I was able to make Altium reflect all of the appropriate connections in the PCB view. Though there are a few net naming issues still to be resolved, this problem has mostly been ironed out.

The final few weeks of the semester were spent laying out amplifier components in the PCB view of Altium. As of right now, a compact design for an amplifier measuring 0.183”x~1.3” has been completed. Making use of 0201 size components, this amplifier is approximately .2” shorter than the old design, despite incorporating an extra transistor. The amplifier design features an isolating ground trace running the length of the amplifier to prevent crosstalk between channels. A prototype layout of the summing circuit has also been completed, though some layout issues there remain to be resolved over the summer.

===Related Files===
*[http://zeus.phys.uconn.edu/halld/tagger/electronics/design-6-2009/Progress20090505.zip Design Snapshot 5/5/2009]
**Backplane
***Backplane.PrjPcb (Altium Project File)
***Backplane.PcbDoc (Altium PCB File)
***Analog Connector.SchDoc, Digital Connector.SchDoc, LEMO.SchDoc (Altium Schematics)
***Backplane.pdf (SmartPDF File of the schematics and PCB layout)
**Amplifier Board
***Analog Board.PrjPcb (Altium Project File)
***Amplifier Board.PcbDoc (Altium PCB File)
***Main.SchDoc, Amplifier.SchDoc, Summer.SchDoc, Voltage References.SchDoc (Altium Schematics)
***Analog Board.pdf (SmartPDF File of the schematics and PCB layout
****The SmartPDF shows the entire PCB workspace, including components that have not yet been placed on the physical PCB.
****The bottom left corner of the PCB view shows a proof-of-concept 5 amplifiers/1 summer layout.
****Finding AMP6 using the PDF bookmarks shows the prototype amplifier layout that resolves mismatched footprint issues (indicated in green in the image farther up on this page).

== Summary of Fall 2009 Work ==

=== Mid-Semester Update, 11/12/2009 ===
We now have one fully working prototype of the SiPM Digital Control Board, and the SiPM Amplifier Board is currently being manufactured and assembled by Sierra Circuits, Inc. The backplane design is nearly complete and will be going out for quoting within a week.

Here is a zip file containing the most recent versions of the tagger files: [http://zeus.phys.uconn.edu/halld/tagger/electronics/design-11-2009/TaggerMicroscopeProgress20091112.zip Design Snapshot 11/12/2009]

A few notes about these files:
*There are four subfolders in the zip file. The folders for the three PCBs are clearly labelled. Each PCB folder has one project file (.PrjPcb) which can be opened in Altium Designer. Each project file refers to only one PcbDoc file, making it easy to figure out what you should look at to see the board.
*The SiPM digital control board project has 4 shelved polygons which should be restored (Tools->Polygon Pours->Restore 4 shelved polyons) to see the state of the board as it was last manufactured. Revisions from the testing process have not yet been entered into Altium but can be reviewed on this wiki: [[Digital control board debugging notes]]
*The SiPM amplifier (analog) board project will give an error message that it was unable to find "Test PCB.PcbDoc". Please ignore this. The file was intentionally omitted to prevent confusion, and is not related to the actual design.
*The backplane project will give an error message that it was unable to find "Backplane_New.PcbDoc". Please ignore this. The file was intentionally omitted to prevent confusion, and is not related to the actual design.

=== End of Semester Update ===
This semester, a lot of progress has been made on the tagger electronics. The digital control board is now onto revision 2.0, the amplifier board is in production, and the backplane is awaiting completion of the purchase order for production to begin. It is exciting to say that the bulk of the work is now finally complete. Remaining for the spring are the tasks of testing the amplifier board, and seeing that everything fits into the backplane. Here are some details about what I accomplished this semester, as well as links to the most recent project files.

==== Digital Control Board ====
The semester began with the digital control board prototypes sitting on lab bench waiting to be tested. My job was primarily to design the boards, not to debug them, though I still played an integral part in the testing process. We were all relieved that none of the boards appeared to smoke immediately when we first applied power, though there were a few confusing problems that had to be sorted out. Most of these problems are described in detail on the [[Digital control board debugging notes]] page. More or less, we had to solder a pin that wasn't connected, replace the crystal oscillator with a CMOS oscillator, and rewire few traces that were accidentally connected to pins intended for other signals. I won't repeat all of the changes we made here since it would be redundant to the page that already discusses it, but the important part is that we have one board that is fully operational, and the version 2.0 schematics/layout reflecting all these changes are complete. I anticipate that production of the version 2.0 boards will occur at the beginning of the spring 2010 semester.

There is still one lingering problem with the digital board design that has not yet been resolved, however. Even after all of the version 2.0 changes were implemented on the version 1.0 boards, only one of the three boards produced actually functioned properly. For a reason unknown to us, two of the boards ended up with their digital to analog converters burning up and smoking. We thoroughly reviewed the schematics and the layout, and found nothing miswired. Furthermore, we analyzed the placement of the ball grid array DAC to the best of our ability, and determined that a misalignment of balls is not the cause of the failure. All of our power supplies are stable, properly decoupled, and grounded as called for by DAC's manufacturer. Currently, the best hypothesis for the failure of 2 of the 3 DACs is that one or more of the absolute maximum ratings must have been exceeded at some point during the assembly process. Analog Devices lists fairly specific specs with small tolerances relating to maximum temperature and the length of time which the DAC may spend inside a reflow oven. We are currently working with the assembly company to attempt to determine exactly what caused the failure. They plan to reexamine the DAC BGAs on heir x-ray machine, and also perform other testing to determine if the assembly process caused the failure.

==== Amplifier Board ====
Throughout the summer and the beginning of the fall semester, I completed the design for the SiPM Amplifier Board, version 1.0. All 30 channels have been implemented along with their summing circuits. As I mentioned in the mid semester update above, this board is being manufactured and assembled by Sierra Circuits, Inc. Some unexpected setbacks occurred in the assembly process that delayed the boards somewhat, but I believe everything is now on track for delivery of the finished product before the start of the spring semester. A number of problems relating to minimum quantities of parts, as well as part naming conventions have now been resolved, and the assembly process should be complete in several weeks.

==== Backplane ====
The backplane design, version 1.0, has also been completed. Sierra Circuits will be manufacturing the backplane, which we will assemble ourselves. The backplane is a particularly interesting PCB from a manufacturing standpoint, because it is designed to be completely light proof. Since the backplane is the only material standing between the whole of Hall D and the inside of the tagger microscope dark box, opacity of the board is particularly important.

Most PCBs with internal copper layers are already fairly opaque, because the copper blocks light from transmitting through the FR-4 and prepreg. Through hole components do not particulary compromise board opacity, because the holes are plugged with component pins and solder. What does have a greater affect on the opaqueness of a board, however, is the thermal reliefs by which through hole pins and vias connect to internal plane layers. These reliefs are designed to aid in the soldering process by minimizing the amount of copper that is directly connected to the plating in the hole. A typical relief consists of four 7-10 mil traces connecting the hole's plating to the internal plane. The plane itself remains about 20 mil away from the hole, to prevent conduction of heat during the soldering process. Unfortunately, this means that there is a small gap in which there is only FR-4 to stop light from passing through the board. Since FR-4 is transparent, this poses a problem for our design. We were able work with Sierra Circuits to come up with a board design that includes an internal layer of special black FR-4 to prevent light leakage through the heat reliefs. While this is certainly not a standard feature, Sierra was confident that they could implement it for us, and we look forward to testing the boards' opacity in the spring.

==== Project Design Snapshot ====
Here is a link to the most recent project files: [http://zeus.phys.uconn.edu/halld/tagger/electronics/design-12-2009/Tagger%20Microscope%20Progress%2020091217.zip Tagger Progress, December 17, 2009]

A few notes about these files:
*There are four subfolders in the zip file. The folders for the three PCBs are clearly labelled. Each PCB folder has one project file (.PrjPcb) which can be opened in Altium Designer. Each project file refers to only one PcbDoc file, making it easy to figure out what you should look at to see the board.
*The SiPM amplifier (analog) board project will give an error message that it was unable to find "Test PCB.PcbDoc". Please ignore this. The file was intentionally omitted to prevent confusion, and is not related to the actual design.
*The backplane project will give an error message that it was unable to find "Backplane_New.PcbDoc". Please ignore this. The file was intentionally omitted to prevent confusion, and is not related to the actual design.
*The most recent bill of materials, which resolves all of the naming convention issues brought up by Sierra is labelled with the date 20091212 in the Amplifier Board folder.

Woody Underwood

2010-03-18T21:39:43Z

Underwood: /* Project Design Snapshot */

== About Me ==
My name is Woody Underwood. I'm a junior entering my seventh semester in the physics program at UConn. Since the summer of 2008, I've been working in the lab of Dr. Richard Jones designing electronics for the US Department of Energy's GlueX experiment. My assignment is to develop three circuit boards that work together to tag photons coming from the diamond radiator. My circuitry essentially measures (indirectly) the energy of these photons in order to determine if they are of interest to GlueX. The three boards I am designing consist of a digital board, an analog board, and a connecting backplane.

== About My Circuitry ==
Electrons leaving the diamond radiator are deflected by a magnetic field into an array of scintillating fibres, producing photons. Wave guides carry these photons to SiPMs (silicon photomultipliers) mounted on the analog circuit board. The analog board contains transimpedance amplifiers and summing circuitry to condition the signals for digitization.

The sensitivity of the SiPMs and the gain of the amplifiers on the analog board are controlled both by the power supply VCC and bias voltages supplied from the digital board. The digital board receives commands from a computer via ethernet, and uses a 32-channel DAC to output appropriate bias voltages to the SiPMs on the analog board. The digital and analog boards are connected by means of a backplane, which is also responsible for providing power and grounds to both boards.

== Summary of Fall 2008 Work ==
All circuitry design work was done using Altium Designer. The digital board was the first to be designed. The first step in designing the digital board was to review the list of key components that had already been selected by Igor and Dr. Jones. These components included such things as the Xilinx Spartan-3A FPGA, and the Analog Devices AD5535 DAC. I began by looking through datasheets for these components to find out their needs, including power and decoupling requirements. I reviewed the pinout diagrams, and then looked through Altium’s standard libraries to find components that matched (in many cases the particular component I was looking for was not in the library, but a similar footprint or schematic symbol was). For components without matching schematic symbols, I entered pinout information from the datasheets into Microsoft Excel, using a layout compatible with Altium’s Smart Grid Insert function. Then, I was able to literally copy and paste pin information from Excel into Altium to generate the schematic symbols I needed.

Once I had appropriate schematic symbols available for all parts, I began making appropriate connections in the schematic view in Altium. Though tedious, this task was not exceedingly difficult. I finished the schematics in several days, and then moved on to PCB design. I switched into Altium's PCB view. The footprints corresponding to the components I used in the schematics were automatically inserted by Altium. My job was then to position these components in logical places on the board and make all of the connections corresponding to the nets defined in the schematics.

Due to the large number of components being placed in the limited space available on the digital board, Altium's auto-router proved completely useless. Therefore, I routed the board manually. Despite Altium's revolutionary convergence of schematic and PCB design into a single program, this was no easy task. During the routing process, I had to take into account not only the connections that had to be made, but also things such as avoiding crosstalk and minimizing trace length for sensitive components. I was able to complete routing after several weeks of work. The digital board design has since been completed and the board has been printed. It is currently awaiting assembly.

The analog board provided a host of new challenges. The basic schematic for the transimpedance amplifier on the analog board was completed by Igor and Dr. Jones before the semester. Inputting the schematic into Altium was not very difficult. However, one problem I encountered was that the analog board contains 32 copies of this amplifier circuitry. After failing to find any way to insert multiple copies of both the schematic and its corresponding PCB layout, I decided to insert only single copies of each schematic page, and copy and paste the PCB layout to produce 32 copies of the amplifier circuitry. At first this seemed like a quick and easy way to get all of the necessary circuitry onto the PCB. However, I eventually discovered that this procedure would lead to major problems with the board assembly process (due to duplicate component designators, and for other reasons). Fortunately, this revelation came around the same time that Igor and Dr. Jones found a problem with the performance of the amplifier circuit. Making any changes to the amplifier circuit at this point will require a major reroute of all the traces on the analog board. Since the board needs to be completely redesigned anyway, this will give me another chance to find a way to match schematics with all 32 copies of the amplifier circuitry.

The backplane design is currently in progress. It should be relatively easy to complete. All that remains to be done is to add the LEMO connectors and power inputs. The board is simple enough that it can be routed completely by the auto-router, though a quick hand routing will probably be superior. I anticipate that I can complete the backplane with a few days of concentrated work over break.

Included below are links to the files I have been working on. Included in the files for each board is a "SmartPDF," viewable in Adobe Reader. For those without Altium Designer, these may be the best files to look at. They include complete schematics and PCB layout, and are also indexed by component.

Any questions about the tagger circuitry can be directed to me at [mailto:mitchell.underwood@uconn.edu mitchell.underwood@uconn.edu]

=== Related Files ===
* [http://zeus.phys.uconn.edu/halld/tagger/electronics/design-12-2008/DigitalBoard.zip DigitalBoard.zip]:
**Altium Project File (SiPM Control Board.PrjPcb)
**Altium PCB Layout File (Prototype1.PcbDoc)
**Altium Schematic Files (*.SchDoc)
**Altium Annotation Document (SiPM Control Board.Annotation)
***Not used, but generated by Altium when opening the project
**Altium PRJPCBSTRUCTURE File (SiPM Control Board.PRJPCBSTRUCTURE)
***Not used, but generated by Altium when opening the project)
**“SmartPDF” of the board and schematics (SiPM Control Board.pdf)
***Can be used to explore the PCB layout and schematics without needing Altium
**Pick and Place File for board population (Pick Place for Prototype1.txt)
***Used by board assembler
**NC Drill Files (Prototype1.txt, Prototype1.DRR, Prototype1.DRL)
***Used by board printer
**Gerber Files for all layers (in folder Gerbers)
***Used by board printer
**Altium CAMtastic file (CAMtastic4 FINAL.Cam)
***Basically a composite of all the Gerbers
**Photos and 3D rendering of populated board
***In folder “Photos”
**EMF Files showing different layers
***In folder “EMF Renderings”
**AutoCad File of PCB (Prototype1 Autocad.DWG)
**Altium Library of Custom Footprints for Digital Board (GlueX IC Library.SchLib)
***Current as of completion of digital board
***This library has since been updated for the backplane

*[http://zeus.phys.uconn.edu/halld/tagger/electronics/design-12-2008/Analog%20Board%2020081211.zip Analog Board 20081211.zip]:
**Altium Project File (AnalogBoard.PrjPcb)
**Altium PCB Layout File (AnalogBoardPCB.PcbDoc)
**Altium Schematic Files (Amplifer1.SchDoc, Summer.SchDoc)
**“SmartPDF” of the board and schematics (AnalogBoard.pdf)
**Altium Component Definition for SiPM (SiPM Library.PcbLib)
***Contains part footprint and pin information for the SiPM component

*[http://zeus.phys.uconn.edu/halld/tagger/electronics/design-12-2008/Backplane%2020081211.zip Backplane 20081211.zip]
**Altium Project File (Backplane.PrjPcb)
**Alitum PCB Layout File (Backplane.PcbDoc)
**Altium Schematic Files (Analog Connector.SchDoc, Digital Connector.SchDoc)
***Analog Connector = Eurocard to analog board
***Digital Connector = Eurocard to digital board, +3.3V voltage regulator, and location identifier jumper
***LEMO connections not yet included in these schematics
**“SmartPDF” of the board and schematics (Backplane.pdf)
**Pin layout files used to define pinouts for custom components (Pin Layout, 96 pin connector.xlsx, Pinouts.xlsx)
***Pin Layout, 96 pin connector = pinout definition for 96 pin Eurocard connector
***Pinouts.xlsx = pinout definitions for digital board, which were reused for the 48 pin digital Eurocard receptacle on backplane
**Altium Library of Custom Components (GlueX IC Library.SchLib)
***UPDATED to include new backplane components
***An older version of this library was used for the digital board

==Summary of Spring 2009 Work==

At the end of the fall semester, Dr. Jones, Igor, and I determined that the amplifier/summing circuit we had designed simply didn’t have sufficient performance characteristics to be useful for GlueX. During the beginning of the spring semester, Igor came up with a new design, utilizing more transistors, to provide the high gain, fast response, picosecond resolution amplifier that we needed. The design performed flawlessly both in MatLab simulations and in a handmade single channel prototype. The first of my goals for the spring 2009 semester was to capture the schematic for this new amplifier into Altium designer, and layout a new amplifier board. The second of my goals, of course, was to complete production of the digital control board prototypes.

[[Image:Digital Board, Populated.JPG|thumb|The populated digital board, with a tube of Chap-BlockTM for size comparison.]] Since the fall semester left us with three unpopulated digital control board PCBs, getting those PCBs assembled with their components was the first priority. I began the semester by tracking down all of the components we needed (some of which were selected at the end of the fall semester), and making appropriate substitutions for components whose availability had changed since the fall. In the process of selecting these components, I noticed several places where it seemed like power consumption on the board may be somewhat high. To fix this, I developed a spreadsheet in Microsoft Excel that calculates optimal resistor values to use for to obtain a specified voltage divider stiffness. With this tool, I was able to optimize power consumption across the board, and select appropriate components. Once all components had been selected, ordered, and received, we sent the order out to Screamin’ Circuits for assembly. The boards came back several weeks later, and are currently awaiting testing by some undergraduates who will be in the lab this summer.

While Igor was finalizing his amplifier/summing circuit, I worked briefly on design of the backplane. A number of details regarding trace impedance and board dimensions were ironed out. Nonetheless, many problems still remain which I will need to tackle over the summer. The first of these problems is that we have yet to find an appropriate low cost coaxial connector to route signals off the backplane. In addition, screws with which to mount the backplane to the tagger must be selected so that appropriate holes can be created for them on the PCB.

Once we were satisfied that the amplifier/summing circuit performed as required, I shifted work from the backplane to the amplifier board. Around the same time, I began working on a poster to present my work at the Frontiers in Undergraduate Research Exhibition held during Open House Weekend here at UConn. If you’re interested in my poster, check it out here.

[[Image:Amplifier-Summer-Laid-out.gif|thumb|A prototype layout of 5 amplifier channels and a summing circuit. Actual size is ~1.6" tall. Areas in green represent problems to be resolved over summer 2009. A prototype amplifier with no green spots has been designed and will be replicated to this design soon.]] To start the amplifier/summing circuit project, I searched high and low for information about how to handle multi-channel designs in Altium. Not surprisingly, the first Google result on the query “multichannel design Altium” had everything I was missing during the fall when I was trying to lay out the original amplifier circuit. Using my new knowledge of Altium’s multichannel capabilities, I captured Igor’s new design into the schematics editor of Altium Designer. With proper nested schematic sheets, the entire 30 channel amplifier/6 channel summer design was compressed into just 4 schematic sheets, vs. the ~40 or so that would have been required had I laid out the complete schematics of the old design.

I spent about a week and a half trying to figure out how to handle nesting independent nets from a repeated subsheet into another repeated subsheet which also produces independent nets from the nets of the first sheet. This sounds somewhat complicated, and I suppose perhaps it is a somewhat unique situation, since none of the ~5 sample multichannel projects included with Altium had such a construction in them. Basically, each summing circuit has five amplifier subcircuits, each of which puts out its own signal independent of the other four. From the perspective of the entire board, there are 6 summers, each of which has five independent signals coming from the amplifiers, and one summed signal. Determining how to get Altium to realize the proper connections from each individual amplifier, through that amplifier’s summer, to the main schematic was a complicated mess of naming conventions, but eventually I was able to make Altium reflect all of the appropriate connections in the PCB view. Though there are a few net naming issues still to be resolved, this problem has mostly been ironed out.

The final few weeks of the semester were spent laying out amplifier components in the PCB view of Altium. As of right now, a compact design for an amplifier measuring 0.183”x~1.3” has been completed. Making use of 0201 size components, this amplifier is approximately .2” shorter than the old design, despite incorporating an extra transistor. The amplifier design features an isolating ground trace running the length of the amplifier to prevent crosstalk between channels. A prototype layout of the summing circuit has also been completed, though some layout issues there remain to be resolved over the summer.

===Related Files===
*[http://zeus.phys.uconn.edu/halld/tagger/electronics/design-6-2009/Progress20090505.zip Design Snapshot 5/5/2009]
**Backplane
***Backplane.PrjPcb (Altium Project File)
***Backplane.PcbDoc (Altium PCB File)
***Analog Connector.SchDoc, Digital Connector.SchDoc, LEMO.SchDoc (Altium Schematics)
***Backplane.pdf (SmartPDF File of the schematics and PCB layout)
**Amplifier Board
***Analog Board.PrjPcb (Altium Project File)
***Amplifier Board.PcbDoc (Altium PCB File)
***Main.SchDoc, Amplifier.SchDoc, Summer.SchDoc, Voltage References.SchDoc (Altium Schematics)
***Analog Board.pdf (SmartPDF File of the schematics and PCB layout
****The SmartPDF shows the entire PCB workspace, including components that have not yet been placed on the physical PCB.
****The bottom left corner of the PCB view shows a proof-of-concept 5 amplifiers/1 summer layout.
****Finding AMP6 using the PDF bookmarks shows the prototype amplifier layout that resolves mismatched footprint issues (indicated in green in the image farther up on this page).

== Summary of Fall 2009 Work ==

=== Mid-Semester Update, 11/12/2009 ===
We now have one fully working prototype of the SiPM Digital Control Board, and the SiPM Amplifier Board is currently being manufactured and assembled by Sierra Circuits, Inc. The backplane design is nearly complete and will be going out for quoting within a week.

Here is a zip file containing the most recent versions of the tagger files: [http://zeus.phys.uconn.edu/halld/tagger/electronics/design-11-2009/TaggerMicroscopeProgress20091112.zip Design Snapshot 11/12/2009]

A few notes about these files:
*There are four subfolders in the zip file. The folders for the three PCBs are clearly labelled. Each PCB folder has one project file (.PrjPcb) which can be opened in Altium Designer. Each project file refers to only one PcbDoc file, making it easy to figure out what you should look at to see the board.
*The SiPM digital control board project has 4 shelved polygons which should be restored (Tools->Polygon Pours->Restore 4 shelved polyons) to see the state of the board as it was last manufactured. Revisions from the testing process have not yet been entered into Altium but can be reviewed on this wiki: [[Digital control board debugging notes]]
*The SiPM amplifier (analog) board project will give an error message that it was unable to find "Test PCB.PcbDoc". Please ignore this. The file was intentionally omitted to prevent confusion, and is not related to the actual design.
*The backplane project will give an error message that it was unable to find "Backplane_New.PcbDoc". Please ignore this. The file was intentionally omitted to prevent confusion, and is not related to the actual design.

=== End of Semester Update ===
This semester, a lot of progress has been made on the tagger electronics. The digital control board is now onto revision 2.0, the amplifier board is in production, and the backplane is awaiting completion of the purchase order for production to begin. It is exciting to say that the bulk of the work is now finally complete. Remaining for the spring are the tasks of testing the amplifier board, and seeing that everything fits into the backplane. Here are some details about what I accomplished this semester, as well as links to the most recent project files.

==== Digital Control Board ====
The semester began with the digital control board prototypes sitting on lab bench waiting to be tested. My job was primarily to design the boards, not to debug them, though I still played an integral part in the testing process. We were all relieved that none of the boards appeared to smoke immediately when we first applied power, though there were a few confusing problems that had to be sorted out. Most of these problems are described in detail on the [[Digital control board debugging notes]] page. More or less, we had to solder a pin that wasn't connected, replace the crystal oscillator with a CMOS oscillator, and rewire few traces that were accidentally connected to pins intended for other signals. I won't repeat all of the changes we made here since it would be redundant to the page that already discusses it, but the important part is that we have one board that is fully operational, and the version 2.0 schematics/layout reflecting all these changes are complete. I anticipate that production of the version 2.0 boards will occur at the beginning of the spring 2010 semester.

There is still one lingering problem with the digital board design that has not yet been resolved, however. Even after all of the version 2.0 changes were implemented on the version 1.0 boards, only one of the three boards produced actually functioned properly. For a reason unknown to us, two of the boards ended up with their digital to analog converters burning up and smoking. We thoroughly reviewed the schematics and the layout, and found nothing miswired. Furthermore, we analyzed the placement of the ball grid array DAC to the best of our ability, and determined that a misalignment of balls is not the cause of the failure. All of our power supplies are stable, properly decoupled, and grounded as called for by DAC's manufacturer. Currently, the best hypothesis for the failure of 2 of the 3 DACs is that one or more of the absolute maximum ratings must have been exceeded at some point during the assembly process. Analog Devices lists fairly specific specs with small tolerances relating to maximum temperature and the length of time which the DAC may spend inside a reflow oven. We are currently working with the assembly company to attempt to determine exactly what caused the failure. They plan to reexamine the DAC BGAs on heir x-ray machine, and also perform other testing to determine if the assembly process caused the failure.

==== Amplifier Board ====
Throughout the summer and the beginning of the fall semester, I completed the design for the SiPM Amplifier Board, version 1.0. All 30 channels have been implemented along with their summing circuits. As I mentioned in the mid semester update above, this board is being manufactured and assembled by Sierra Circuits, Inc. Some unexpected setbacks occurred in the assembly process that delayed the boards somewhat, but I believe everything is now on track for delivery of the finished product before the start of the spring semester. A number of problems relating to minimum quantities of parts, as well as part naming conventions have now been resolved, and the assembly process should be complete in several weeks.

==== Backplane ====
The backplane design, version 1.0, has also been completed. Sierra Circuits will be manufacturing the backplane, which we will assemble ourselves. The backplane is a particularly interesting PCB from a manufacturing standpoint, because it is designed to be completely light proof. Since the backplane is the only material standing between the whole of Hall D and the inside of the tagger microscope dark box, opacity of the board is particularly important.

Most PCBs with internal copper layers are already fairly opaque, because the copper blocks light from transmitting through the FR-4 and prepreg. Through hole components do not particulary compromise board opacity, because the holes are plugged with component pins and solder. What does have a greater affect on the opaqueness of a board, however, is the thermal reliefs by which through hole pins and vias connect to internal plane layers. These reliefs are designed to aid in the soldering process by minimizing the amount of copper that is directly connected to the plating in the hole. A typical relief consists of four 7-10 mil traces connecting the hole's plating to the internal plane. The plane itself remains about 20 mil away from the hole, to prevent conduction of heat during the soldering process. Unfortunately, this means that there is a small gap in which there is only FR-4 to stop light from passing through the board. Since FR-4 is transparent, this poses a problem for our design. We were able work with Sierra Circuits to come up with a board design that includes an internal layer of special black FR-4 to prevent light leakage through the heat reliefs. While this is certainly not a standard feature, Sierra was confident that they could implement it for us, and we look forward to testing the boards' opacity in the spring.

==== Project Design Snapshot ====
Here is a link to the most project files: [http://zeus.phys.uconn.edu/halld/tagger/electronics/design-12-2009/Tagger%20Microscope%20Progress%2020091217.zip Tagger Progress, December 17, 2009]

A few notes about these files:
*There are four subfolders in the zip file. The folders for the three PCBs are clearly labelled. Each PCB folder has one project file (.PrjPcb) which can be opened in Altium Designer. Each project file refers to only one PcbDoc file, making it easy to figure out what you should look at to see the board.
*The SiPM amplifier (analog) board project will give an error message that it was unable to find "Test PCB.PcbDoc". Please ignore this. The file was intentionally omitted to prevent confusion, and is not related to the actual design.
*The backplane project will give an error message that it was unable to find "Backplane_New.PcbDoc". Please ignore this. The file was intentionally omitted to prevent confusion, and is not related to the actual design.
*The most recent bill of materials, which resolves all of the naming convention issues brought up by Sierra is labelled with the date 20091212 in the Amplifier Board folder.

Woody Underwood

2009-12-21T03:52:21Z

Underwood: /* Digital Control Board */ added that we are working with screaming circuits

== About Me ==
My name is Woody Underwood. I'm a junior entering my seventh semester in the physics program at UConn. Since the summer of 2008, I've been working in the lab of Dr. Richard Jones designing electronics for the US Department of Energy's GlueX experiment. My assignment is to develop three circuit boards that work together to tag photons coming from the diamond radiator. My circuitry essentially measures (indirectly) the energy of these photons in order to determine if they are of interest to GlueX. The three boards I am designing consist of a digital board, an analog board, and a connecting backplane.

== About My Circuitry ==
Electrons leaving the diamond radiator are deflected by a magnetic field into an array of scintillating fibres, producing photons. Wave guides carry these photons to SiPMs (silicon photomultipliers) mounted on the analog circuit board. The analog board contains transimpedance amplifiers and summing circuitry to condition the signals for digitization.

The sensitivity of the SiPMs and the gain of the amplifiers on the analog board are controlled both by the power supply VCC and bias voltages supplied from the digital board. The digital board receives commands from a computer via ethernet, and uses a 32-channel DAC to output appropriate bias voltages to the SiPMs on the analog board. The digital and analog boards are connected by means of a backplane, which is also responsible for providing power and grounds to both boards.

== Summary of Fall 2008 Work ==
All circuitry design work was done using Altium Designer. The digital board was the first to be designed. The first step in designing the digital board was to review the list of key components that had already been selected by Igor and Dr. Jones. These components included such things as the Xilinx Spartan-3A FPGA, and the Analog Devices AD5535 DAC. I began by looking through datasheets for these components to find out their needs, including power and decoupling requirements. I reviewed the pinout diagrams, and then looked through Altium’s standard libraries to find components that matched (in many cases the particular component I was looking for was not in the library, but a similar footprint or schematic symbol was). For components without matching schematic symbols, I entered pinout information from the datasheets into Microsoft Excel, using a layout compatible with Altium’s Smart Grid Insert function. Then, I was able to literally copy and paste pin information from Excel into Altium to generate the schematic symbols I needed.

Once I had appropriate schematic symbols available for all parts, I began making appropriate connections in the schematic view in Altium. Though tedious, this task was not exceedingly difficult. I finished the schematics in several days, and then moved on to PCB design. I switched into Altium's PCB view. The footprints corresponding to the components I used in the schematics were automatically inserted by Altium. My job was then to position these components in logical places on the board and make all of the connections corresponding to the nets defined in the schematics.

Due to the large number of components being placed in the limited space available on the digital board, Altium's auto-router proved completely useless. Therefore, I routed the board manually. Despite Altium's revolutionary convergence of schematic and PCB design into a single program, this was no easy task. During the routing process, I had to take into account not only the connections that had to be made, but also things such as avoiding crosstalk and minimizing trace length for sensitive components. I was able to complete routing after several weeks of work. The digital board design has since been completed and the board has been printed. It is currently awaiting assembly.

The analog board provided a host of new challenges. The basic schematic for the transimpedance amplifier on the analog board was completed by Igor and Dr. Jones before the semester. Inputting the schematic into Altium was not very difficult. However, one problem I encountered was that the analog board contains 32 copies of this amplifier circuitry. After failing to find any way to insert multiple copies of both the schematic and its corresponding PCB layout, I decided to insert only single copies of each schematic page, and copy and paste the PCB layout to produce 32 copies of the amplifier circuitry. At first this seemed like a quick and easy way to get all of the necessary circuitry onto the PCB. However, I eventually discovered that this procedure would lead to major problems with the board assembly process (due to duplicate component designators, and for other reasons). Fortunately, this revelation came around the same time that Igor and Dr. Jones found a problem with the performance of the amplifier circuit. Making any changes to the amplifier circuit at this point will require a major reroute of all the traces on the analog board. Since the board needs to be completely redesigned anyway, this will give me another chance to find a way to match schematics with all 32 copies of the amplifier circuitry.

The backplane design is currently in progress. It should be relatively easy to complete. All that remains to be done is to add the LEMO connectors and power inputs. The board is simple enough that it can be routed completely by the auto-router, though a quick hand routing will probably be superior. I anticipate that I can complete the backplane with a few days of concentrated work over break.

Included below are links to the files I have been working on. Included in the files for each board is a "SmartPDF," viewable in Adobe Reader. For those without Altium Designer, these may be the best files to look at. They include complete schematics and PCB layout, and are also indexed by component.

Any questions about the tagger circuitry can be directed to me at [mailto:mitchell.underwood@uconn.edu mitchell.underwood@uconn.edu]

=== Related Files ===
* [http://zeus.phys.uconn.edu/halld/tagger/electronics/design-12-2008/DigitalBoard.zip DigitalBoard.zip]:
**Altium Project File (SiPM Control Board.PrjPcb)
**Altium PCB Layout File (Prototype1.PcbDoc)
**Altium Schematic Files (*.SchDoc)
**Altium Annotation Document (SiPM Control Board.Annotation)
***Not used, but generated by Altium when opening the project
**Altium PRJPCBSTRUCTURE File (SiPM Control Board.PRJPCBSTRUCTURE)
***Not used, but generated by Altium when opening the project)
**“SmartPDF” of the board and schematics (SiPM Control Board.pdf)
***Can be used to explore the PCB layout and schematics without needing Altium
**Pick and Place File for board population (Pick Place for Prototype1.txt)
***Used by board assembler
**NC Drill Files (Prototype1.txt, Prototype1.DRR, Prototype1.DRL)
***Used by board printer
**Gerber Files for all layers (in folder Gerbers)
***Used by board printer
**Altium CAMtastic file (CAMtastic4 FINAL.Cam)
***Basically a composite of all the Gerbers
**Photos and 3D rendering of populated board
***In folder “Photos”
**EMF Files showing different layers
***In folder “EMF Renderings”
**AutoCad File of PCB (Prototype1 Autocad.DWG)
**Altium Library of Custom Footprints for Digital Board (GlueX IC Library.SchLib)
***Current as of completion of digital board
***This library has since been updated for the backplane

*[http://zeus.phys.uconn.edu/halld/tagger/electronics/design-12-2008/Analog%20Board%2020081211.zip Analog Board 20081211.zip]:
**Altium Project File (AnalogBoard.PrjPcb)
**Altium PCB Layout File (AnalogBoardPCB.PcbDoc)
**Altium Schematic Files (Amplifer1.SchDoc, Summer.SchDoc)
**“SmartPDF” of the board and schematics (AnalogBoard.pdf)
**Altium Component Definition for SiPM (SiPM Library.PcbLib)
***Contains part footprint and pin information for the SiPM component

*[http://zeus.phys.uconn.edu/halld/tagger/electronics/design-12-2008/Backplane%2020081211.zip Backplane 20081211.zip]
**Altium Project File (Backplane.PrjPcb)
**Alitum PCB Layout File (Backplane.PcbDoc)
**Altium Schematic Files (Analog Connector.SchDoc, Digital Connector.SchDoc)
***Analog Connector = Eurocard to analog board
***Digital Connector = Eurocard to digital board, +3.3V voltage regulator, and location identifier jumper
***LEMO connections not yet included in these schematics
**“SmartPDF” of the board and schematics (Backplane.pdf)
**Pin layout files used to define pinouts for custom components (Pin Layout, 96 pin connector.xlsx, Pinouts.xlsx)
***Pin Layout, 96 pin connector = pinout definition for 96 pin Eurocard connector
***Pinouts.xlsx = pinout definitions for digital board, which were reused for the 48 pin digital Eurocard receptacle on backplane
**Altium Library of Custom Components (GlueX IC Library.SchLib)
***UPDATED to include new backplane components
***An older version of this library was used for the digital board

==Summary of Spring 2009 Work==

At the end of the fall semester, Dr. Jones, Igor, and I determined that the amplifier/summing circuit we had designed simply didn’t have sufficient performance characteristics to be useful for GlueX. During the beginning of the spring semester, Igor came up with a new design, utilizing more transistors, to provide the high gain, fast response, picosecond resolution amplifier that we needed. The design performed flawlessly both in MatLab simulations and in a handmade single channel prototype. The first of my goals for the spring 2009 semester was to capture the schematic for this new amplifier into Altium designer, and layout a new amplifier board. The second of my goals, of course, was to complete production of the digital control board prototypes.

[[Image:Digital Board, Populated.JPG|thumb|The populated digital board, with a tube of Chap-BlockTM for size comparison.]] Since the fall semester left us with three unpopulated digital control board PCBs, getting those PCBs assembled with their components was the first priority. I began the semester by tracking down all of the components we needed (some of which were selected at the end of the fall semester), and making appropriate substitutions for components whose availability had changed since the fall. In the process of selecting these components, I noticed several places where it seemed like power consumption on the board may be somewhat high. To fix this, I developed a spreadsheet in Microsoft Excel that calculates optimal resistor values to use for to obtain a specified voltage divider stiffness. With this tool, I was able to optimize power consumption across the board, and select appropriate components. Once all components had been selected, ordered, and received, we sent the order out to Screamin’ Circuits for assembly. The boards came back several weeks later, and are currently awaiting testing by some undergraduates who will be in the lab this summer.

While Igor was finalizing his amplifier/summing circuit, I worked briefly on design of the backplane. A number of details regarding trace impedance and board dimensions were ironed out. Nonetheless, many problems still remain which I will need to tackle over the summer. The first of these problems is that we have yet to find an appropriate low cost coaxial connector to route signals off the backplane. In addition, screws with which to mount the backplane to the tagger must be selected so that appropriate holes can be created for them on the PCB.

Once we were satisfied that the amplifier/summing circuit performed as required, I shifted work from the backplane to the amplifier board. Around the same time, I began working on a poster to present my work at the Frontiers in Undergraduate Research Exhibition held during Open House Weekend here at UConn. If you’re interested in my poster, check it out here.

[[Image:Amplifier-Summer-Laid-out.gif|thumb|A prototype layout of 5 amplifier channels and a summing circuit. Actual size is ~1.6" tall. Areas in green represent problems to be resolved over summer 2009. A prototype amplifier with no green spots has been designed and will be replicated to this design soon.]] To start the amplifier/summing circuit project, I searched high and low for information about how to handle multi-channel designs in Altium. Not surprisingly, the first Google result on the query “multichannel design Altium” had everything I was missing during the fall when I was trying to lay out the original amplifier circuit. Using my new knowledge of Altium’s multichannel capabilities, I captured Igor’s new design into the schematics editor of Altium Designer. With proper nested schematic sheets, the entire 30 channel amplifier/6 channel summer design was compressed into just 4 schematic sheets, vs. the ~40 or so that would have been required had I laid out the complete schematics of the old design.

I spent about a week and a half trying to figure out how to handle nesting independent nets from a repeated subsheet into another repeated subsheet which also produces independent nets from the nets of the first sheet. This sounds somewhat complicated, and I suppose perhaps it is a somewhat unique situation, since none of the ~5 sample multichannel projects included with Altium had such a construction in them. Basically, each summing circuit has five amplifier subcircuits, each of which puts out its own signal independent of the other four. From the perspective of the entire board, there are 6 summers, each of which has five independent signals coming from the amplifiers, and one summed signal. Determining how to get Altium to realize the proper connections from each individual amplifier, through that amplifier’s summer, to the main schematic was a complicated mess of naming conventions, but eventually I was able to make Altium reflect all of the appropriate connections in the PCB view. Though there are a few net naming issues still to be resolved, this problem has mostly been ironed out.

The final few weeks of the semester were spent laying out amplifier components in the PCB view of Altium. As of right now, a compact design for an amplifier measuring 0.183”x~1.3” has been completed. Making use of 0201 size components, this amplifier is approximately .2” shorter than the old design, despite incorporating an extra transistor. The amplifier design features an isolating ground trace running the length of the amplifier to prevent crosstalk between channels. A prototype layout of the summing circuit has also been completed, though some layout issues there remain to be resolved over the summer.

===Related Files===
*[http://zeus.phys.uconn.edu/halld/tagger/electronics/design-6-2009/Progress20090505.zip Design Snapshot 5/5/2009]
**Backplane
***Backplane.PrjPcb (Altium Project File)
***Backplane.PcbDoc (Altium PCB File)
***Analog Connector.SchDoc, Digital Connector.SchDoc, LEMO.SchDoc (Altium Schematics)
***Backplane.pdf (SmartPDF File of the schematics and PCB layout)
**Amplifier Board
***Analog Board.PrjPcb (Altium Project File)
***Amplifier Board.PcbDoc (Altium PCB File)
***Main.SchDoc, Amplifier.SchDoc, Summer.SchDoc, Voltage References.SchDoc (Altium Schematics)
***Analog Board.pdf (SmartPDF File of the schematics and PCB layout
****The SmartPDF shows the entire PCB workspace, including components that have not yet been placed on the physical PCB.
****The bottom left corner of the PCB view shows a proof-of-concept 5 amplifiers/1 summer layout.
****Finding AMP6 using the PDF bookmarks shows the prototype amplifier layout that resolves mismatched footprint issues (indicated in green in the image farther up on this page).

== Summary of Fall 2009 Work ==

=== Mid-Semester Update, 11/12/2009 ===
We now have one fully working prototype of the SiPM Digital Control Board, and the SiPM Amplifier Board is currently being manufactured and assembled by Sierra Circuits, Inc. The backplane design is nearly complete and will be going out for quoting within a week.

Here is a zip file containing the most recent versions of the tagger files: [http://zeus.phys.uconn.edu/halld/tagger/electronics/design-11-2009/TaggerMicroscopeProgress20091112.zip Design Snapshot 11/12/2009]

A few notes about these files:
*There are four subfolders in the zip file. The folders for the three PCBs are clearly labelled. Each PCB folder has one project file (.PrjPcb) which can be opened in Altium Designer. Each project file refers to only one PcbDoc file, making it easy to figure out what you should look at to see the board.
*The SiPM digital control board project has 4 shelved polygons which should be restored (Tools->Polygon Pours->Restore 4 shelved polyons) to see the state of the board as it was last manufactured. Revisions from the testing process have not yet been entered into Altium but can be reviewed on this wiki: [[Digital control board debugging notes]]
*The SiPM amplifier (analog) board project will give an error message that it was unable to find "Test PCB.PcbDoc". Please ignore this. The file was intentionally omitted to prevent confusion, and is not related to the actual design.
*The backplane project will give an error message that it was unable to find "Backplane_New.PcbDoc". Please ignore this. The file was intentionally omitted to prevent confusion, and is not related to the actual design.

=== End of Semester Update ===
This semester, a lot of progress has been made on the tagger electronics. The digital control board is now onto revision 2.0, the amplifier board is in production, and the backplane is awaiting completion of the purchase order for production to begin. It is exciting to say that the bulk of the work is now finally complete. Remaining for the spring are the tasks of testing the amplifier board, and seeing that everything fits into the backplane. Here are some details about what I accomplished this semester, as well as links to the most recent project files.

==== Digital Control Board ====
The semester began with the digital control board prototypes sitting on lab bench waiting to be tested. My job was primarily to design the boards, not to debug them, though I still played an integral part in the testing process. We were all relieved that none of the boards appeared to smoke immediately when we first applied power, though there were a few confusing problems that had to be sorted out. Most of these problems are described in detail on the [[Digital control board debugging notes]] page. More or less, we had to solder a pin that wasn't connected, replace the crystal oscillator with a CMOS oscillator, and rewire few traces that were accidentally connected to pins intended for other signals. I won't repeat all of the changes we made here since it would be redundant to the page that already discusses it, but the important part is that we have one board that is fully operational, and the version 2.0 schematics/layout reflecting all these changes are complete. I anticipate that production of the version 2.0 boards will occur at the beginning of the spring 2010 semester.

There is still one lingering problem with the digital board design that has not yet been resolved, however. Even after all of the version 2.0 changes were implemented on the version 1.0 boards, only one of the three boards produced actually functioned properly. For a reason unknown to us, two of the boards ended up with their digital to analog converters burning up and smoking. We thoroughly reviewed the schematics and the layout, and found nothing miswired. Furthermore, we analyzed the placement of the ball grid array DAC to the best of our ability, and determined that a misalignment of balls is not the cause of the failure. All of our power supplies are stable, properly decoupled, and grounded as called for by DAC's manufacturer. Currently, the best hypothesis for the failure of 2 of the 3 DACs is that one or more of the absolute maximum ratings must have been exceeded at some point during the assembly process. Analog Devices lists fairly specific specs with small tolerances relating to maximum temperature and the length of time which the DAC may spend inside a reflow oven. We are currently working with the assembly company to attempt to determine exactly what caused the failure. They plan to reexamine the DAC BGAs on heir x-ray machine, and also perform other testing to determine if the assembly process caused the failure.

==== Amplifier Board ====
Throughout the summer and the beginning of the fall semester, I completed the design for the SiPM Amplifier Board, version 1.0. All 30 channels have been implemented along with their summing circuits. As I mentioned in the mid semester update above, this board is being manufactured and assembled by Sierra Circuits, Inc. Some unexpected setbacks occurred in the assembly process that delayed the boards somewhat, but I believe everything is now on track for delivery of the finished product before the start of the spring semester. A number of problems relating to minimum quantities of parts, as well as part naming conventions have now been resolved, and the assembly process should be complete in several weeks.

==== Backplane ====
The backplane design, version 1.0, has also been completed. Sierra Circuits will be manufacturing the backplane, which we will assemble ourselves. The backplane is a particularly interesting PCB from a manufacturing standpoint, because it is designed to be completely light proof. Since the backplane is the only material standing between the whole of Hall D and the inside of the tagger microscope dark box, opacity of the board is particularly important.

Most PCBs with internal copper layers are already fairly opaque, because the copper blocks light from transmitting through the FR-4 and prepreg. Through hole components do not particulary compromise board opacity, because the holes are plugged with component pins and solder. What does have a greater affect on the opaqueness of a board, however, is the thermal reliefs by which through hole pins and vias connect to internal plane layers. These reliefs are designed to aid in the soldering process by minimizing the amount of copper that is directly connected to the plating in the hole. A typical relief consists of four 7-10 mil traces connecting the hole's plating to the internal plane. The plane itself remains about 20 mil away from the hole, to prevent conduction of heat during the soldering process. Unfortunately, this means that there is a small gap in which there is only FR-4 to stop light from passing through the board. Since FR-4 is transparent, this poses a problem for our design. We were able work with Sierra Circuits to come up with a board design that includes an internal layer of special black FR-4 to prevent light leakage through the heat reliefs. While this is certainly not a standard feature, Sierra was confident that they could implement it for us, and we look forward to testing the boards' opacity in the spring.

==== Project Design Snapshot ====
Here is a link to the most project files: INSERT LINK TO DESIGN SNAPSHOT 12/17/2009 HERE

A few notes about these files:
*There are four subfolders in the zip file. The folders for the three PCBs are clearly labelled. Each PCB folder has one project file (.PrjPcb) which can be opened in Altium Designer. Each project file refers to only one PcbDoc file, making it easy to figure out what you should look at to see the board.
*The SiPM amplifier (analog) board project will give an error message that it was unable to find "Test PCB.PcbDoc". Please ignore this. The file was intentionally omitted to prevent confusion, and is not related to the actual design.
*The backplane project will give an error message that it was unable to find "Backplane_New.PcbDoc". Please ignore this. The file was intentionally omitted to prevent confusion, and is not related to the actual design.
*The most recent bill of materials, which resolves all of the naming convention issues brought up by Sierra is labelled with the date 20091212 in the Amplifier Board folder.

Woody Underwood

2009-12-17T22:22:20Z

Underwood: /* Project Design Snapshot */ typo

== About Me ==
My name is Woody Underwood. I'm a junior entering my seventh semester in the physics program at UConn. Since the summer of 2008, I've been working in the lab of Dr. Richard Jones designing electronics for the US Department of Energy's GlueX experiment. My assignment is to develop three circuit boards that work together to tag photons coming from the diamond radiator. My circuitry essentially measures (indirectly) the energy of these photons in order to determine if they are of interest to GlueX. The three boards I am designing consist of a digital board, an analog board, and a connecting backplane.

== About My Circuitry ==
Electrons leaving the diamond radiator are deflected by a magnetic field into an array of scintillating fibres, producing photons. Wave guides carry these photons to SiPMs (silicon photomultipliers) mounted on the analog circuit board. The analog board contains transimpedance amplifiers and summing circuitry to condition the signals for digitization.

The sensitivity of the SiPMs and the gain of the amplifiers on the analog board are controlled both by the power supply VCC and bias voltages supplied from the digital board. The digital board receives commands from a computer via ethernet, and uses a 32-channel DAC to output appropriate bias voltages to the SiPMs on the analog board. The digital and analog boards are connected by means of a backplane, which is also responsible for providing power and grounds to both boards.

== Summary of Fall 2008 Work ==
All circuitry design work was done using Altium Designer. The digital board was the first to be designed. The first step in designing the digital board was to review the list of key components that had already been selected by Igor and Dr. Jones. These components included such things as the Xilinx Spartan-3A FPGA, and the Analog Devices AD5535 DAC. I began by looking through datasheets for these components to find out their needs, including power and decoupling requirements. I reviewed the pinout diagrams, and then looked through Altium’s standard libraries to find components that matched (in many cases the particular component I was looking for was not in the library, but a similar footprint or schematic symbol was). For components without matching schematic symbols, I entered pinout information from the datasheets into Microsoft Excel, using a layout compatible with Altium’s Smart Grid Insert function. Then, I was able to literally copy and paste pin information from Excel into Altium to generate the schematic symbols I needed.

Once I had appropriate schematic symbols available for all parts, I began making appropriate connections in the schematic view in Altium. Though tedious, this task was not exceedingly difficult. I finished the schematics in several days, and then moved on to PCB design. I switched into Altium's PCB view. The footprints corresponding to the components I used in the schematics were automatically inserted by Altium. My job was then to position these components in logical places on the board and make all of the connections corresponding to the nets defined in the schematics.

Due to the large number of components being placed in the limited space available on the digital board, Altium's auto-router proved completely useless. Therefore, I routed the board manually. Despite Altium's revolutionary convergence of schematic and PCB design into a single program, this was no easy task. During the routing process, I had to take into account not only the connections that had to be made, but also things such as avoiding crosstalk and minimizing trace length for sensitive components. I was able to complete routing after several weeks of work. The digital board design has since been completed and the board has been printed. It is currently awaiting assembly.

The analog board provided a host of new challenges. The basic schematic for the transimpedance amplifier on the analog board was completed by Igor and Dr. Jones before the semester. Inputting the schematic into Altium was not very difficult. However, one problem I encountered was that the analog board contains 32 copies of this amplifier circuitry. After failing to find any way to insert multiple copies of both the schematic and its corresponding PCB layout, I decided to insert only single copies of each schematic page, and copy and paste the PCB layout to produce 32 copies of the amplifier circuitry. At first this seemed like a quick and easy way to get all of the necessary circuitry onto the PCB. However, I eventually discovered that this procedure would lead to major problems with the board assembly process (due to duplicate component designators, and for other reasons). Fortunately, this revelation came around the same time that Igor and Dr. Jones found a problem with the performance of the amplifier circuit. Making any changes to the amplifier circuit at this point will require a major reroute of all the traces on the analog board. Since the board needs to be completely redesigned anyway, this will give me another chance to find a way to match schematics with all 32 copies of the amplifier circuitry.

The backplane design is currently in progress. It should be relatively easy to complete. All that remains to be done is to add the LEMO connectors and power inputs. The board is simple enough that it can be routed completely by the auto-router, though a quick hand routing will probably be superior. I anticipate that I can complete the backplane with a few days of concentrated work over break.

Included below are links to the files I have been working on. Included in the files for each board is a "SmartPDF," viewable in Adobe Reader. For those without Altium Designer, these may be the best files to look at. They include complete schematics and PCB layout, and are also indexed by component.

Any questions about the tagger circuitry can be directed to me at [mailto:mitchell.underwood@uconn.edu mitchell.underwood@uconn.edu]

=== Related Files ===
* [http://zeus.phys.uconn.edu/halld/tagger/electronics/design-12-2008/DigitalBoard.zip DigitalBoard.zip]:
**Altium Project File (SiPM Control Board.PrjPcb)
**Altium PCB Layout File (Prototype1.PcbDoc)
**Altium Schematic Files (*.SchDoc)
**Altium Annotation Document (SiPM Control Board.Annotation)
***Not used, but generated by Altium when opening the project
**Altium PRJPCBSTRUCTURE File (SiPM Control Board.PRJPCBSTRUCTURE)
***Not used, but generated by Altium when opening the project)
**“SmartPDF” of the board and schematics (SiPM Control Board.pdf)
***Can be used to explore the PCB layout and schematics without needing Altium
**Pick and Place File for board population (Pick Place for Prototype1.txt)
***Used by board assembler
**NC Drill Files (Prototype1.txt, Prototype1.DRR, Prototype1.DRL)
***Used by board printer
**Gerber Files for all layers (in folder Gerbers)
***Used by board printer
**Altium CAMtastic file (CAMtastic4 FINAL.Cam)
***Basically a composite of all the Gerbers
**Photos and 3D rendering of populated board
***In folder “Photos”
**EMF Files showing different layers
***In folder “EMF Renderings”
**AutoCad File of PCB (Prototype1 Autocad.DWG)
**Altium Library of Custom Footprints for Digital Board (GlueX IC Library.SchLib)
***Current as of completion of digital board
***This library has since been updated for the backplane

*[http://zeus.phys.uconn.edu/halld/tagger/electronics/design-12-2008/Analog%20Board%2020081211.zip Analog Board 20081211.zip]:
**Altium Project File (AnalogBoard.PrjPcb)
**Altium PCB Layout File (AnalogBoardPCB.PcbDoc)
**Altium Schematic Files (Amplifer1.SchDoc, Summer.SchDoc)
**“SmartPDF” of the board and schematics (AnalogBoard.pdf)
**Altium Component Definition for SiPM (SiPM Library.PcbLib)
***Contains part footprint and pin information for the SiPM component

*[http://zeus.phys.uconn.edu/halld/tagger/electronics/design-12-2008/Backplane%2020081211.zip Backplane 20081211.zip]
**Altium Project File (Backplane.PrjPcb)
**Alitum PCB Layout File (Backplane.PcbDoc)
**Altium Schematic Files (Analog Connector.SchDoc, Digital Connector.SchDoc)
***Analog Connector = Eurocard to analog board
***Digital Connector = Eurocard to digital board, +3.3V voltage regulator, and location identifier jumper
***LEMO connections not yet included in these schematics
**“SmartPDF” of the board and schematics (Backplane.pdf)
**Pin layout files used to define pinouts for custom components (Pin Layout, 96 pin connector.xlsx, Pinouts.xlsx)
***Pin Layout, 96 pin connector = pinout definition for 96 pin Eurocard connector
***Pinouts.xlsx = pinout definitions for digital board, which were reused for the 48 pin digital Eurocard receptacle on backplane
**Altium Library of Custom Components (GlueX IC Library.SchLib)
***UPDATED to include new backplane components
***An older version of this library was used for the digital board

==Summary of Spring 2009 Work==

At the end of the fall semester, Dr. Jones, Igor, and I determined that the amplifier/summing circuit we had designed simply didn’t have sufficient performance characteristics to be useful for GlueX. During the beginning of the spring semester, Igor came up with a new design, utilizing more transistors, to provide the high gain, fast response, picosecond resolution amplifier that we needed. The design performed flawlessly both in MatLab simulations and in a handmade single channel prototype. The first of my goals for the spring 2009 semester was to capture the schematic for this new amplifier into Altium designer, and layout a new amplifier board. The second of my goals, of course, was to complete production of the digital control board prototypes.

[[Image:Digital Board, Populated.JPG|thumb|The populated digital board, with a tube of Chap-BlockTM for size comparison.]] Since the fall semester left us with three unpopulated digital control board PCBs, getting those PCBs assembled with their components was the first priority. I began the semester by tracking down all of the components we needed (some of which were selected at the end of the fall semester), and making appropriate substitutions for components whose availability had changed since the fall. In the process of selecting these components, I noticed several places where it seemed like power consumption on the board may be somewhat high. To fix this, I developed a spreadsheet in Microsoft Excel that calculates optimal resistor values to use for to obtain a specified voltage divider stiffness. With this tool, I was able to optimize power consumption across the board, and select appropriate components. Once all components had been selected, ordered, and received, we sent the order out to Screamin’ Circuits for assembly. The boards came back several weeks later, and are currently awaiting testing by some undergraduates who will be in the lab this summer.

While Igor was finalizing his amplifier/summing circuit, I worked briefly on design of the backplane. A number of details regarding trace impedance and board dimensions were ironed out. Nonetheless, many problems still remain which I will need to tackle over the summer. The first of these problems is that we have yet to find an appropriate low cost coaxial connector to route signals off the backplane. In addition, screws with which to mount the backplane to the tagger must be selected so that appropriate holes can be created for them on the PCB.

Once we were satisfied that the amplifier/summing circuit performed as required, I shifted work from the backplane to the amplifier board. Around the same time, I began working on a poster to present my work at the Frontiers in Undergraduate Research Exhibition held during Open House Weekend here at UConn. If you’re interested in my poster, check it out here.

[[Image:Amplifier-Summer-Laid-out.gif|thumb|A prototype layout of 5 amplifier channels and a summing circuit. Actual size is ~1.6" tall. Areas in green represent problems to be resolved over summer 2009. A prototype amplifier with no green spots has been designed and will be replicated to this design soon.]] To start the amplifier/summing circuit project, I searched high and low for information about how to handle multi-channel designs in Altium. Not surprisingly, the first Google result on the query “multichannel design Altium” had everything I was missing during the fall when I was trying to lay out the original amplifier circuit. Using my new knowledge of Altium’s multichannel capabilities, I captured Igor’s new design into the schematics editor of Altium Designer. With proper nested schematic sheets, the entire 30 channel amplifier/6 channel summer design was compressed into just 4 schematic sheets, vs. the ~40 or so that would have been required had I laid out the complete schematics of the old design.

I spent about a week and a half trying to figure out how to handle nesting independent nets from a repeated subsheet into another repeated subsheet which also produces independent nets from the nets of the first sheet. This sounds somewhat complicated, and I suppose perhaps it is a somewhat unique situation, since none of the ~5 sample multichannel projects included with Altium had such a construction in them. Basically, each summing circuit has five amplifier subcircuits, each of which puts out its own signal independent of the other four. From the perspective of the entire board, there are 6 summers, each of which has five independent signals coming from the amplifiers, and one summed signal. Determining how to get Altium to realize the proper connections from each individual amplifier, through that amplifier’s summer, to the main schematic was a complicated mess of naming conventions, but eventually I was able to make Altium reflect all of the appropriate connections in the PCB view. Though there are a few net naming issues still to be resolved, this problem has mostly been ironed out.

The final few weeks of the semester were spent laying out amplifier components in the PCB view of Altium. As of right now, a compact design for an amplifier measuring 0.183”x~1.3” has been completed. Making use of 0201 size components, this amplifier is approximately .2” shorter than the old design, despite incorporating an extra transistor. The amplifier design features an isolating ground trace running the length of the amplifier to prevent crosstalk between channels. A prototype layout of the summing circuit has also been completed, though some layout issues there remain to be resolved over the summer.

===Related Files===
*[http://zeus.phys.uconn.edu/halld/tagger/electronics/design-6-2009/Progress20090505.zip Design Snapshot 5/5/2009]
**Backplane
***Backplane.PrjPcb (Altium Project File)
***Backplane.PcbDoc (Altium PCB File)
***Analog Connector.SchDoc, Digital Connector.SchDoc, LEMO.SchDoc (Altium Schematics)
***Backplane.pdf (SmartPDF File of the schematics and PCB layout)
**Amplifier Board
***Analog Board.PrjPcb (Altium Project File)
***Amplifier Board.PcbDoc (Altium PCB File)
***Main.SchDoc, Amplifier.SchDoc, Summer.SchDoc, Voltage References.SchDoc (Altium Schematics)
***Analog Board.pdf (SmartPDF File of the schematics and PCB layout
****The SmartPDF shows the entire PCB workspace, including components that have not yet been placed on the physical PCB.
****The bottom left corner of the PCB view shows a proof-of-concept 5 amplifiers/1 summer layout.
****Finding AMP6 using the PDF bookmarks shows the prototype amplifier layout that resolves mismatched footprint issues (indicated in green in the image farther up on this page).

== Summary of Fall 2009 Work ==

=== Mid-Semester Update, 11/12/2009 ===
We now have one fully working prototype of the SiPM Digital Control Board, and the SiPM Amplifier Board is currently being manufactured and assembled by Sierra Circuits, Inc. The backplane design is nearly complete and will be going out for quoting within a week.

Here is a zip file containing the most recent versions of the tagger files: [http://zeus.phys.uconn.edu/halld/tagger/electronics/design-11-2009/TaggerMicroscopeProgress20091112.zip Design Snapshot 11/12/2009]

A few notes about these files:
*There are four subfolders in the zip file. The folders for the three PCBs are clearly labelled. Each PCB folder has one project file (.PrjPcb) which can be opened in Altium Designer. Each project file refers to only one PcbDoc file, making it easy to figure out what you should look at to see the board.
*The SiPM digital control board project has 4 shelved polygons which should be restored (Tools->Polygon Pours->Restore 4 shelved polyons) to see the state of the board as it was last manufactured. Revisions from the testing process have not yet been entered into Altium but can be reviewed on this wiki: [[Digital control board debugging notes]]
*The SiPM amplifier (analog) board project will give an error message that it was unable to find "Test PCB.PcbDoc". Please ignore this. The file was intentionally omitted to prevent confusion, and is not related to the actual design.
*The backplane project will give an error message that it was unable to find "Backplane_New.PcbDoc". Please ignore this. The file was intentionally omitted to prevent confusion, and is not related to the actual design.

=== End of Semester Update ===
This semester, a lot of progress has been made on the tagger electronics. The digital control board is now onto revision 2.0, the amplifier board is in production, and the backplane is awaiting completion of the purchase order for production to begin. It is exciting to say that the bulk of the work is now finally complete. Remaining for the spring are the tasks of testing the amplifier board, and seeing that everything fits into the backplane. Here are some details about what I accomplished this semester, as well as links to the most recent project files.

==== Digital Control Board ====
The semester began with the digital control board prototypes sitting on lab bench waiting to be tested. My job was primarily to design the boards, not to debug them, though I still played an integral part in the testing process. We were all relieved that none of the boards appeared to smoke immediately when we first applied power, though there were a few confusing problems that had to be sorted out. Most of these problems are described in detail on the [[Digital control board debugging notes]] page. More or less, we had to solder a pin that wasn't connected, replace the crystal oscillator with a CMOS oscillator, and rewire few traces that were accidentally connected to pins intended for other signals. I won't repeat all of the changes we made here since it would be redundant to the page that already discusses it, but the important part is that we have one board that is fully operational, and the version 2.0 schematics/layout reflecting all these changes are complete. I anticipate that production of the version 2.0 boards will occur at the beginning of the spring 2010 semester.

There is still one lingering problem with the digital board design that has not yet been resolved, however. Even after all of the version 2.0 changes were implemented on the version 1.0 boards, only one of the three boards produced actually functioned properly. For a reason unknown to us, two of the boards ended up with their digital to analog converters burning up and smoking. We thoroughly reviewed the schematics and the layout, and found nothing miswired. Furthermore, we analyzed the placement of the ball grid array DAC to the best of our ability, and determined that a misalignment of balls is not the cause of the failure. All of our power supplies are stable, properly decoupled, and grounded as called for by DAC's manufacturer. Currently, the best hypothesis for the failure of 2 of the 3 DACs is that one or more of the absolute maximum ratings must have been exceeded at some point during the assembly process. Analog Devices lists fairly specific specs with small tolerances relating to maximum temperature and the length of time which the DAC may spend inside a reflow oven. We have run into some difficultly trying to find out from the boards' assembler whether they followed the published specs for the assembly process, but we intend to keep trying until the cause of the DAC failure has been resolved.

==== Amplifier Board ====
Throughout the summer and the beginning of the fall semester, I completed the design for the SiPM Amplifier Board, version 1.0. All 30 channels have been implemented along with their summing circuits. As I mentioned in the mid semester update above, this board is being manufactured and assembled by Sierra Circuits, Inc. Some unexpected setbacks occurred in the assembly process that delayed the boards somewhat, but I believe everything is now on track for delivery of the finished product before the start of the spring semester. A number of problems relating to minimum quantities of parts, as well as part naming conventions have now been resolved, and the assembly process should be complete in several weeks.

==== Backplane ====
The backplane design, version 1.0, has also been completed. Sierra Circuits will be manufacturing the backplane, which we will assemble ourselves. The backplane is a particularly interesting PCB from a manufacturing standpoint, because it is designed to be completely light proof. Since the backplane is the only material standing between the whole of Hall D and the inside of the tagger microscope dark box, opacity of the board is particularly important.

Most PCBs with internal copper layers are already fairly opaque, because the copper blocks light from transmitting through the FR-4 and prepreg. Through hole components do not particulary compromise board opacity, because the holes are plugged with component pins and solder. What does have a greater affect on the opaqueness of a board, however, is the thermal reliefs by which through hole pins and vias connect to internal plane layers. These reliefs are designed to aid in the soldering process by minimizing the amount of copper that is directly connected to the plating in the hole. A typical relief consists of four 7-10 mil traces connecting the hole's plating to the internal plane. The plane itself remains about 20 mil away from the hole, to prevent conduction of heat during the soldering process. Unfortunately, this means that there is a small gap in which there is only FR-4 to stop light from passing through the board. Since FR-4 is transparent, this poses a problem for our design. We were able work with Sierra Circuits to come up with a board design that includes an internal layer of special black FR-4 to prevent light leakage through the heat reliefs. While this is certainly not a standard feature, Sierra was confident that they could implement it for us, and we look forward to testing the boards' opacity in the spring.

==== Project Design Snapshot ====
Here is a link to the most project files: INSERT LINK TO DESIGN SNAPSHOT 12/17/2009 HERE

A few notes about these files:
*There are four subfolders in the zip file. The folders for the three PCBs are clearly labelled. Each PCB folder has one project file (.PrjPcb) which can be opened in Altium Designer. Each project file refers to only one PcbDoc file, making it easy to figure out what you should look at to see the board.
*The SiPM amplifier (analog) board project will give an error message that it was unable to find "Test PCB.PcbDoc". Please ignore this. The file was intentionally omitted to prevent confusion, and is not related to the actual design.
*The backplane project will give an error message that it was unable to find "Backplane_New.PcbDoc". Please ignore this. The file was intentionally omitted to prevent confusion, and is not related to the actual design.
*The most recent bill of materials, which resolves all of the naming convention issues brought up by Sierra is labelled with the date 20091212 in the Amplifier Board folder.

Woody Underwood

2009-12-17T22:22:02Z

Underwood: /* Project Design Snapshot */

== About Me ==
My name is Woody Underwood. I'm a junior entering my seventh semester in the physics program at UConn. Since the summer of 2008, I've been working in the lab of Dr. Richard Jones designing electronics for the US Department of Energy's GlueX experiment. My assignment is to develop three circuit boards that work together to tag photons coming from the diamond radiator. My circuitry essentially measures (indirectly) the energy of these photons in order to determine if they are of interest to GlueX. The three boards I am designing consist of a digital board, an analog board, and a connecting backplane.

== About My Circuitry ==
Electrons leaving the diamond radiator are deflected by a magnetic field into an array of scintillating fibres, producing photons. Wave guides carry these photons to SiPMs (silicon photomultipliers) mounted on the analog circuit board. The analog board contains transimpedance amplifiers and summing circuitry to condition the signals for digitization.

The sensitivity of the SiPMs and the gain of the amplifiers on the analog board are controlled both by the power supply VCC and bias voltages supplied from the digital board. The digital board receives commands from a computer via ethernet, and uses a 32-channel DAC to output appropriate bias voltages to the SiPMs on the analog board. The digital and analog boards are connected by means of a backplane, which is also responsible for providing power and grounds to both boards.

== Summary of Fall 2008 Work ==
All circuitry design work was done using Altium Designer. The digital board was the first to be designed. The first step in designing the digital board was to review the list of key components that had already been selected by Igor and Dr. Jones. These components included such things as the Xilinx Spartan-3A FPGA, and the Analog Devices AD5535 DAC. I began by looking through datasheets for these components to find out their needs, including power and decoupling requirements. I reviewed the pinout diagrams, and then looked through Altium’s standard libraries to find components that matched (in many cases the particular component I was looking for was not in the library, but a similar footprint or schematic symbol was). For components without matching schematic symbols, I entered pinout information from the datasheets into Microsoft Excel, using a layout compatible with Altium’s Smart Grid Insert function. Then, I was able to literally copy and paste pin information from Excel into Altium to generate the schematic symbols I needed.

Once I had appropriate schematic symbols available for all parts, I began making appropriate connections in the schematic view in Altium. Though tedious, this task was not exceedingly difficult. I finished the schematics in several days, and then moved on to PCB design. I switched into Altium's PCB view. The footprints corresponding to the components I used in the schematics were automatically inserted by Altium. My job was then to position these components in logical places on the board and make all of the connections corresponding to the nets defined in the schematics.

Due to the large number of components being placed in the limited space available on the digital board, Altium's auto-router proved completely useless. Therefore, I routed the board manually. Despite Altium's revolutionary convergence of schematic and PCB design into a single program, this was no easy task. During the routing process, I had to take into account not only the connections that had to be made, but also things such as avoiding crosstalk and minimizing trace length for sensitive components. I was able to complete routing after several weeks of work. The digital board design has since been completed and the board has been printed. It is currently awaiting assembly.

The analog board provided a host of new challenges. The basic schematic for the transimpedance amplifier on the analog board was completed by Igor and Dr. Jones before the semester. Inputting the schematic into Altium was not very difficult. However, one problem I encountered was that the analog board contains 32 copies of this amplifier circuitry. After failing to find any way to insert multiple copies of both the schematic and its corresponding PCB layout, I decided to insert only single copies of each schematic page, and copy and paste the PCB layout to produce 32 copies of the amplifier circuitry. At first this seemed like a quick and easy way to get all of the necessary circuitry onto the PCB. However, I eventually discovered that this procedure would lead to major problems with the board assembly process (due to duplicate component designators, and for other reasons). Fortunately, this revelation came around the same time that Igor and Dr. Jones found a problem with the performance of the amplifier circuit. Making any changes to the amplifier circuit at this point will require a major reroute of all the traces on the analog board. Since the board needs to be completely redesigned anyway, this will give me another chance to find a way to match schematics with all 32 copies of the amplifier circuitry.

The backplane design is currently in progress. It should be relatively easy to complete. All that remains to be done is to add the LEMO connectors and power inputs. The board is simple enough that it can be routed completely by the auto-router, though a quick hand routing will probably be superior. I anticipate that I can complete the backplane with a few days of concentrated work over break.

Included below are links to the files I have been working on. Included in the files for each board is a "SmartPDF," viewable in Adobe Reader. For those without Altium Designer, these may be the best files to look at. They include complete schematics and PCB layout, and are also indexed by component.

Any questions about the tagger circuitry can be directed to me at [mailto:mitchell.underwood@uconn.edu mitchell.underwood@uconn.edu]

=== Related Files ===
* [http://zeus.phys.uconn.edu/halld/tagger/electronics/design-12-2008/DigitalBoard.zip DigitalBoard.zip]:
**Altium Project File (SiPM Control Board.PrjPcb)
**Altium PCB Layout File (Prototype1.PcbDoc)
**Altium Schematic Files (*.SchDoc)
**Altium Annotation Document (SiPM Control Board.Annotation)
***Not used, but generated by Altium when opening the project
**Altium PRJPCBSTRUCTURE File (SiPM Control Board.PRJPCBSTRUCTURE)
***Not used, but generated by Altium when opening the project)
**“SmartPDF” of the board and schematics (SiPM Control Board.pdf)
***Can be used to explore the PCB layout and schematics without needing Altium
**Pick and Place File for board population (Pick Place for Prototype1.txt)
***Used by board assembler
**NC Drill Files (Prototype1.txt, Prototype1.DRR, Prototype1.DRL)
***Used by board printer
**Gerber Files for all layers (in folder Gerbers)
***Used by board printer
**Altium CAMtastic file (CAMtastic4 FINAL.Cam)
***Basically a composite of all the Gerbers
**Photos and 3D rendering of populated board
***In folder “Photos”
**EMF Files showing different layers
***In folder “EMF Renderings”
**AutoCad File of PCB (Prototype1 Autocad.DWG)
**Altium Library of Custom Footprints for Digital Board (GlueX IC Library.SchLib)
***Current as of completion of digital board
***This library has since been updated for the backplane

*[http://zeus.phys.uconn.edu/halld/tagger/electronics/design-12-2008/Analog%20Board%2020081211.zip Analog Board 20081211.zip]:
**Altium Project File (AnalogBoard.PrjPcb)
**Altium PCB Layout File (AnalogBoardPCB.PcbDoc)
**Altium Schematic Files (Amplifer1.SchDoc, Summer.SchDoc)
**“SmartPDF” of the board and schematics (AnalogBoard.pdf)
**Altium Component Definition for SiPM (SiPM Library.PcbLib)
***Contains part footprint and pin information for the SiPM component

*[http://zeus.phys.uconn.edu/halld/tagger/electronics/design-12-2008/Backplane%2020081211.zip Backplane 20081211.zip]
**Altium Project File (Backplane.PrjPcb)
**Alitum PCB Layout File (Backplane.PcbDoc)
**Altium Schematic Files (Analog Connector.SchDoc, Digital Connector.SchDoc)
***Analog Connector = Eurocard to analog board
***Digital Connector = Eurocard to digital board, +3.3V voltage regulator, and location identifier jumper
***LEMO connections not yet included in these schematics
**“SmartPDF” of the board and schematics (Backplane.pdf)
**Pin layout files used to define pinouts for custom components (Pin Layout, 96 pin connector.xlsx, Pinouts.xlsx)
***Pin Layout, 96 pin connector = pinout definition for 96 pin Eurocard connector
***Pinouts.xlsx = pinout definitions for digital board, which were reused for the 48 pin digital Eurocard receptacle on backplane
**Altium Library of Custom Components (GlueX IC Library.SchLib)
***UPDATED to include new backplane components
***An older version of this library was used for the digital board

==Summary of Spring 2009 Work==

At the end of the fall semester, Dr. Jones, Igor, and I determined that the amplifier/summing circuit we had designed simply didn’t have sufficient performance characteristics to be useful for GlueX. During the beginning of the spring semester, Igor came up with a new design, utilizing more transistors, to provide the high gain, fast response, picosecond resolution amplifier that we needed. The design performed flawlessly both in MatLab simulations and in a handmade single channel prototype. The first of my goals for the spring 2009 semester was to capture the schematic for this new amplifier into Altium designer, and layout a new amplifier board. The second of my goals, of course, was to complete production of the digital control board prototypes.

[[Image:Digital Board, Populated.JPG|thumb|The populated digital board, with a tube of Chap-BlockTM for size comparison.]] Since the fall semester left us with three unpopulated digital control board PCBs, getting those PCBs assembled with their components was the first priority. I began the semester by tracking down all of the components we needed (some of which were selected at the end of the fall semester), and making appropriate substitutions for components whose availability had changed since the fall. In the process of selecting these components, I noticed several places where it seemed like power consumption on the board may be somewhat high. To fix this, I developed a spreadsheet in Microsoft Excel that calculates optimal resistor values to use for to obtain a specified voltage divider stiffness. With this tool, I was able to optimize power consumption across the board, and select appropriate components. Once all components had been selected, ordered, and received, we sent the order out to Screamin’ Circuits for assembly. The boards came back several weeks later, and are currently awaiting testing by some undergraduates who will be in the lab this summer.

While Igor was finalizing his amplifier/summing circuit, I worked briefly on design of the backplane. A number of details regarding trace impedance and board dimensions were ironed out. Nonetheless, many problems still remain which I will need to tackle over the summer. The first of these problems is that we have yet to find an appropriate low cost coaxial connector to route signals off the backplane. In addition, screws with which to mount the backplane to the tagger must be selected so that appropriate holes can be created for them on the PCB.

Once we were satisfied that the amplifier/summing circuit performed as required, I shifted work from the backplane to the amplifier board. Around the same time, I began working on a poster to present my work at the Frontiers in Undergraduate Research Exhibition held during Open House Weekend here at UConn. If you’re interested in my poster, check it out here.

[[Image:Amplifier-Summer-Laid-out.gif|thumb|A prototype layout of 5 amplifier channels and a summing circuit. Actual size is ~1.6" tall. Areas in green represent problems to be resolved over summer 2009. A prototype amplifier with no green spots has been designed and will be replicated to this design soon.]] To start the amplifier/summing circuit project, I searched high and low for information about how to handle multi-channel designs in Altium. Not surprisingly, the first Google result on the query “multichannel design Altium” had everything I was missing during the fall when I was trying to lay out the original amplifier circuit. Using my new knowledge of Altium’s multichannel capabilities, I captured Igor’s new design into the schematics editor of Altium Designer. With proper nested schematic sheets, the entire 30 channel amplifier/6 channel summer design was compressed into just 4 schematic sheets, vs. the ~40 or so that would have been required had I laid out the complete schematics of the old design.

I spent about a week and a half trying to figure out how to handle nesting independent nets from a repeated subsheet into another repeated subsheet which also produces independent nets from the nets of the first sheet. This sounds somewhat complicated, and I suppose perhaps it is a somewhat unique situation, since none of the ~5 sample multichannel projects included with Altium had such a construction in them. Basically, each summing circuit has five amplifier subcircuits, each of which puts out its own signal independent of the other four. From the perspective of the entire board, there are 6 summers, each of which has five independent signals coming from the amplifiers, and one summed signal. Determining how to get Altium to realize the proper connections from each individual amplifier, through that amplifier’s summer, to the main schematic was a complicated mess of naming conventions, but eventually I was able to make Altium reflect all of the appropriate connections in the PCB view. Though there are a few net naming issues still to be resolved, this problem has mostly been ironed out.

The final few weeks of the semester were spent laying out amplifier components in the PCB view of Altium. As of right now, a compact design for an amplifier measuring 0.183”x~1.3” has been completed. Making use of 0201 size components, this amplifier is approximately .2” shorter than the old design, despite incorporating an extra transistor. The amplifier design features an isolating ground trace running the length of the amplifier to prevent crosstalk between channels. A prototype layout of the summing circuit has also been completed, though some layout issues there remain to be resolved over the summer.

===Related Files===
*[http://zeus.phys.uconn.edu/halld/tagger/electronics/design-6-2009/Progress20090505.zip Design Snapshot 5/5/2009]
**Backplane
***Backplane.PrjPcb (Altium Project File)
***Backplane.PcbDoc (Altium PCB File)
***Analog Connector.SchDoc, Digital Connector.SchDoc, LEMO.SchDoc (Altium Schematics)
***Backplane.pdf (SmartPDF File of the schematics and PCB layout)
**Amplifier Board
***Analog Board.PrjPcb (Altium Project File)
***Amplifier Board.PcbDoc (Altium PCB File)
***Main.SchDoc, Amplifier.SchDoc, Summer.SchDoc, Voltage References.SchDoc (Altium Schematics)
***Analog Board.pdf (SmartPDF File of the schematics and PCB layout
****The SmartPDF shows the entire PCB workspace, including components that have not yet been placed on the physical PCB.
****The bottom left corner of the PCB view shows a proof-of-concept 5 amplifiers/1 summer layout.
****Finding AMP6 using the PDF bookmarks shows the prototype amplifier layout that resolves mismatched footprint issues (indicated in green in the image farther up on this page).

== Summary of Fall 2009 Work ==

=== Mid-Semester Update, 11/12/2009 ===
We now have one fully working prototype of the SiPM Digital Control Board, and the SiPM Amplifier Board is currently being manufactured and assembled by Sierra Circuits, Inc. The backplane design is nearly complete and will be going out for quoting within a week.

Here is a zip file containing the most recent versions of the tagger files: [http://zeus.phys.uconn.edu/halld/tagger/electronics/design-11-2009/TaggerMicroscopeProgress20091112.zip Design Snapshot 11/12/2009]

A few notes about these files:
*There are four subfolders in the zip file. The folders for the three PCBs are clearly labelled. Each PCB folder has one project file (.PrjPcb) which can be opened in Altium Designer. Each project file refers to only one PcbDoc file, making it easy to figure out what you should look at to see the board.
*The SiPM digital control board project has 4 shelved polygons which should be restored (Tools->Polygon Pours->Restore 4 shelved polyons) to see the state of the board as it was last manufactured. Revisions from the testing process have not yet been entered into Altium but can be reviewed on this wiki: [[Digital control board debugging notes]]
*The SiPM amplifier (analog) board project will give an error message that it was unable to find "Test PCB.PcbDoc". Please ignore this. The file was intentionally omitted to prevent confusion, and is not related to the actual design.
*The backplane project will give an error message that it was unable to find "Backplane_New.PcbDoc". Please ignore this. The file was intentionally omitted to prevent confusion, and is not related to the actual design.

=== End of Semester Update ===
This semester, a lot of progress has been made on the tagger electronics. The digital control board is now onto revision 2.0, the amplifier board is in production, and the backplane is awaiting completion of the purchase order for production to begin. It is exciting to say that the bulk of the work is now finally complete. Remaining for the spring are the tasks of testing the amplifier board, and seeing that everything fits into the backplane. Here are some details about what I accomplished this semester, as well as links to the most recent project files.

==== Digital Control Board ====
The semester began with the digital control board prototypes sitting on lab bench waiting to be tested. My job was primarily to design the boards, not to debug them, though I still played an integral part in the testing process. We were all relieved that none of the boards appeared to smoke immediately when we first applied power, though there were a few confusing problems that had to be sorted out. Most of these problems are described in detail on the [[Digital control board debugging notes]] page. More or less, we had to solder a pin that wasn't connected, replace the crystal oscillator with a CMOS oscillator, and rewire few traces that were accidentally connected to pins intended for other signals. I won't repeat all of the changes we made here since it would be redundant to the page that already discusses it, but the important part is that we have one board that is fully operational, and the version 2.0 schematics/layout reflecting all these changes are complete. I anticipate that production of the version 2.0 boards will occur at the beginning of the spring 2010 semester.

There is still one lingering problem with the digital board design that has not yet been resolved, however. Even after all of the version 2.0 changes were implemented on the version 1.0 boards, only one of the three boards produced actually functioned properly. For a reason unknown to us, two of the boards ended up with their digital to analog converters burning up and smoking. We thoroughly reviewed the schematics and the layout, and found nothing miswired. Furthermore, we analyzed the placement of the ball grid array DAC to the best of our ability, and determined that a misalignment of balls is not the cause of the failure. All of our power supplies are stable, properly decoupled, and grounded as called for by DAC's manufacturer. Currently, the best hypothesis for the failure of 2 of the 3 DACs is that one or more of the absolute maximum ratings must have been exceeded at some point during the assembly process. Analog Devices lists fairly specific specs with small tolerances relating to maximum temperature and the length of time which the DAC may spend inside a reflow oven. We have run into some difficultly trying to find out from the boards' assembler whether they followed the published specs for the assembly process, but we intend to keep trying until the cause of the DAC failure has been resolved.

==== Amplifier Board ====
Throughout the summer and the beginning of the fall semester, I completed the design for the SiPM Amplifier Board, version 1.0. All 30 channels have been implemented along with their summing circuits. As I mentioned in the mid semester update above, this board is being manufactured and assembled by Sierra Circuits, Inc. Some unexpected setbacks occurred in the assembly process that delayed the boards somewhat, but I believe everything is now on track for delivery of the finished product before the start of the spring semester. A number of problems relating to minimum quantities of parts, as well as part naming conventions have now been resolved, and the assembly process should be complete in several weeks.

==== Backplane ====
The backplane design, version 1.0, has also been completed. Sierra Circuits will be manufacturing the backplane, which we will assemble ourselves. The backplane is a particularly interesting PCB from a manufacturing standpoint, because it is designed to be completely light proof. Since the backplane is the only material standing between the whole of Hall D and the inside of the tagger microscope dark box, opacity of the board is particularly important.

Most PCBs with internal copper layers are already fairly opaque, because the copper blocks light from transmitting through the FR-4 and prepreg. Through hole components do not particulary compromise board opacity, because the holes are plugged with component pins and solder. What does have a greater affect on the opaqueness of a board, however, is the thermal reliefs by which through hole pins and vias connect to internal plane layers. These reliefs are designed to aid in the soldering process by minimizing the amount of copper that is directly connected to the plating in the hole. A typical relief consists of four 7-10 mil traces connecting the hole's plating to the internal plane. The plane itself remains about 20 mil away from the hole, to prevent conduction of heat during the soldering process. Unfortunately, this means that there is a small gap in which there is only FR-4 to stop light from passing through the board. Since FR-4 is transparent, this poses a problem for our design. We were able work with Sierra Circuits to come up with a board design that includes an internal layer of special black FR-4 to prevent light leakage through the heat reliefs. While this is certainly not a standard feature, Sierra was confident that they could implement it for us, and we look forward to testing the boards' opacity in the spring.

==== Project Design Snapshot ====
Here is a link to the most project files: INSERT LINK TO DESIGN SNAPSHOT 12/17/2009 HERE

A few notes about these files:
*There are four subfolders in the zip file. The folders for the three PCBs are clearly labelled. Each PCB folder has one project file (.PrjPcb) which can be opened in Altium Designer. Each project file refers to only one PcbDoc file, making it easy to figure out what you should look at to see the board.
*The SiPM amplifier (analog) board project will give an error message that it was unable to find "Test PCB.PcbDoc". Please ignore this. The file was intentionally omitted to prevent confusion, and is not related to the actual design.
*The backplane project will give an error message that it was unable to find "Backplane_New.PcbDoc". Please ignore this. The file was intentionally omitted to prevent confusion, and is not related to the actual design.
*The most recent bill of materials, which resolves all of the naming convention issues brought up by Sierra is labelle with the date 20091212 in the Amplifier Board folder.

Woody Underwood

2009-12-17T22:19:13Z

Underwood: /* Summary of Fall 2009 Work */

== About Me ==
My name is Woody Underwood. I'm a junior entering my seventh semester in the physics program at UConn. Since the summer of 2008, I've been working in the lab of Dr. Richard Jones designing electronics for the US Department of Energy's GlueX experiment. My assignment is to develop three circuit boards that work together to tag photons coming from the diamond radiator. My circuitry essentially measures (indirectly) the energy of these photons in order to determine if they are of interest to GlueX. The three boards I am designing consist of a digital board, an analog board, and a connecting backplane.

== About My Circuitry ==
Electrons leaving the diamond radiator are deflected by a magnetic field into an array of scintillating fibres, producing photons. Wave guides carry these photons to SiPMs (silicon photomultipliers) mounted on the analog circuit board. The analog board contains transimpedance amplifiers and summing circuitry to condition the signals for digitization.

The sensitivity of the SiPMs and the gain of the amplifiers on the analog board are controlled both by the power supply VCC and bias voltages supplied from the digital board. The digital board receives commands from a computer via ethernet, and uses a 32-channel DAC to output appropriate bias voltages to the SiPMs on the analog board. The digital and analog boards are connected by means of a backplane, which is also responsible for providing power and grounds to both boards.

== Summary of Fall 2008 Work ==
All circuitry design work was done using Altium Designer. The digital board was the first to be designed. The first step in designing the digital board was to review the list of key components that had already been selected by Igor and Dr. Jones. These components included such things as the Xilinx Spartan-3A FPGA, and the Analog Devices AD5535 DAC. I began by looking through datasheets for these components to find out their needs, including power and decoupling requirements. I reviewed the pinout diagrams, and then looked through Altium’s standard libraries to find components that matched (in many cases the particular component I was looking for was not in the library, but a similar footprint or schematic symbol was). For components without matching schematic symbols, I entered pinout information from the datasheets into Microsoft Excel, using a layout compatible with Altium’s Smart Grid Insert function. Then, I was able to literally copy and paste pin information from Excel into Altium to generate the schematic symbols I needed.

Once I had appropriate schematic symbols available for all parts, I began making appropriate connections in the schematic view in Altium. Though tedious, this task was not exceedingly difficult. I finished the schematics in several days, and then moved on to PCB design. I switched into Altium's PCB view. The footprints corresponding to the components I used in the schematics were automatically inserted by Altium. My job was then to position these components in logical places on the board and make all of the connections corresponding to the nets defined in the schematics.

Due to the large number of components being placed in the limited space available on the digital board, Altium's auto-router proved completely useless. Therefore, I routed the board manually. Despite Altium's revolutionary convergence of schematic and PCB design into a single program, this was no easy task. During the routing process, I had to take into account not only the connections that had to be made, but also things such as avoiding crosstalk and minimizing trace length for sensitive components. I was able to complete routing after several weeks of work. The digital board design has since been completed and the board has been printed. It is currently awaiting assembly.

The analog board provided a host of new challenges. The basic schematic for the transimpedance amplifier on the analog board was completed by Igor and Dr. Jones before the semester. Inputting the schematic into Altium was not very difficult. However, one problem I encountered was that the analog board contains 32 copies of this amplifier circuitry. After failing to find any way to insert multiple copies of both the schematic and its corresponding PCB layout, I decided to insert only single copies of each schematic page, and copy and paste the PCB layout to produce 32 copies of the amplifier circuitry. At first this seemed like a quick and easy way to get all of the necessary circuitry onto the PCB. However, I eventually discovered that this procedure would lead to major problems with the board assembly process (due to duplicate component designators, and for other reasons). Fortunately, this revelation came around the same time that Igor and Dr. Jones found a problem with the performance of the amplifier circuit. Making any changes to the amplifier circuit at this point will require a major reroute of all the traces on the analog board. Since the board needs to be completely redesigned anyway, this will give me another chance to find a way to match schematics with all 32 copies of the amplifier circuitry.

The backplane design is currently in progress. It should be relatively easy to complete. All that remains to be done is to add the LEMO connectors and power inputs. The board is simple enough that it can be routed completely by the auto-router, though a quick hand routing will probably be superior. I anticipate that I can complete the backplane with a few days of concentrated work over break.

Included below are links to the files I have been working on. Included in the files for each board is a "SmartPDF," viewable in Adobe Reader. For those without Altium Designer, these may be the best files to look at. They include complete schematics and PCB layout, and are also indexed by component.

Any questions about the tagger circuitry can be directed to me at [mailto:mitchell.underwood@uconn.edu mitchell.underwood@uconn.edu]

=== Related Files ===
* [http://zeus.phys.uconn.edu/halld/tagger/electronics/design-12-2008/DigitalBoard.zip DigitalBoard.zip]:
**Altium Project File (SiPM Control Board.PrjPcb)
**Altium PCB Layout File (Prototype1.PcbDoc)
**Altium Schematic Files (*.SchDoc)
**Altium Annotation Document (SiPM Control Board.Annotation)
***Not used, but generated by Altium when opening the project
**Altium PRJPCBSTRUCTURE File (SiPM Control Board.PRJPCBSTRUCTURE)
***Not used, but generated by Altium when opening the project)
**“SmartPDF” of the board and schematics (SiPM Control Board.pdf)
***Can be used to explore the PCB layout and schematics without needing Altium
**Pick and Place File for board population (Pick Place for Prototype1.txt)
***Used by board assembler
**NC Drill Files (Prototype1.txt, Prototype1.DRR, Prototype1.DRL)
***Used by board printer
**Gerber Files for all layers (in folder Gerbers)
***Used by board printer
**Altium CAMtastic file (CAMtastic4 FINAL.Cam)
***Basically a composite of all the Gerbers
**Photos and 3D rendering of populated board
***In folder “Photos”
**EMF Files showing different layers
***In folder “EMF Renderings”
**AutoCad File of PCB (Prototype1 Autocad.DWG)
**Altium Library of Custom Footprints for Digital Board (GlueX IC Library.SchLib)
***Current as of completion of digital board
***This library has since been updated for the backplane

*[http://zeus.phys.uconn.edu/halld/tagger/electronics/design-12-2008/Analog%20Board%2020081211.zip Analog Board 20081211.zip]:
**Altium Project File (AnalogBoard.PrjPcb)
**Altium PCB Layout File (AnalogBoardPCB.PcbDoc)
**Altium Schematic Files (Amplifer1.SchDoc, Summer.SchDoc)
**“SmartPDF” of the board and schematics (AnalogBoard.pdf)
**Altium Component Definition for SiPM (SiPM Library.PcbLib)
***Contains part footprint and pin information for the SiPM component

*[http://zeus.phys.uconn.edu/halld/tagger/electronics/design-12-2008/Backplane%2020081211.zip Backplane 20081211.zip]
**Altium Project File (Backplane.PrjPcb)
**Alitum PCB Layout File (Backplane.PcbDoc)
**Altium Schematic Files (Analog Connector.SchDoc, Digital Connector.SchDoc)
***Analog Connector = Eurocard to analog board
***Digital Connector = Eurocard to digital board, +3.3V voltage regulator, and location identifier jumper
***LEMO connections not yet included in these schematics
**“SmartPDF” of the board and schematics (Backplane.pdf)
**Pin layout files used to define pinouts for custom components (Pin Layout, 96 pin connector.xlsx, Pinouts.xlsx)
***Pin Layout, 96 pin connector = pinout definition for 96 pin Eurocard connector
***Pinouts.xlsx = pinout definitions for digital board, which were reused for the 48 pin digital Eurocard receptacle on backplane
**Altium Library of Custom Components (GlueX IC Library.SchLib)
***UPDATED to include new backplane components
***An older version of this library was used for the digital board

==Summary of Spring 2009 Work==

At the end of the fall semester, Dr. Jones, Igor, and I determined that the amplifier/summing circuit we had designed simply didn’t have sufficient performance characteristics to be useful for GlueX. During the beginning of the spring semester, Igor came up with a new design, utilizing more transistors, to provide the high gain, fast response, picosecond resolution amplifier that we needed. The design performed flawlessly both in MatLab simulations and in a handmade single channel prototype. The first of my goals for the spring 2009 semester was to capture the schematic for this new amplifier into Altium designer, and layout a new amplifier board. The second of my goals, of course, was to complete production of the digital control board prototypes.

[[Image:Digital Board, Populated.JPG|thumb|The populated digital board, with a tube of Chap-BlockTM for size comparison.]] Since the fall semester left us with three unpopulated digital control board PCBs, getting those PCBs assembled with their components was the first priority. I began the semester by tracking down all of the components we needed (some of which were selected at the end of the fall semester), and making appropriate substitutions for components whose availability had changed since the fall. In the process of selecting these components, I noticed several places where it seemed like power consumption on the board may be somewhat high. To fix this, I developed a spreadsheet in Microsoft Excel that calculates optimal resistor values to use for to obtain a specified voltage divider stiffness. With this tool, I was able to optimize power consumption across the board, and select appropriate components. Once all components had been selected, ordered, and received, we sent the order out to Screamin’ Circuits for assembly. The boards came back several weeks later, and are currently awaiting testing by some undergraduates who will be in the lab this summer.

While Igor was finalizing his amplifier/summing circuit, I worked briefly on design of the backplane. A number of details regarding trace impedance and board dimensions were ironed out. Nonetheless, many problems still remain which I will need to tackle over the summer. The first of these problems is that we have yet to find an appropriate low cost coaxial connector to route signals off the backplane. In addition, screws with which to mount the backplane to the tagger must be selected so that appropriate holes can be created for them on the PCB.

Once we were satisfied that the amplifier/summing circuit performed as required, I shifted work from the backplane to the amplifier board. Around the same time, I began working on a poster to present my work at the Frontiers in Undergraduate Research Exhibition held during Open House Weekend here at UConn. If you’re interested in my poster, check it out here.

[[Image:Amplifier-Summer-Laid-out.gif|thumb|A prototype layout of 5 amplifier channels and a summing circuit. Actual size is ~1.6" tall. Areas in green represent problems to be resolved over summer 2009. A prototype amplifier with no green spots has been designed and will be replicated to this design soon.]] To start the amplifier/summing circuit project, I searched high and low for information about how to handle multi-channel designs in Altium. Not surprisingly, the first Google result on the query “multichannel design Altium” had everything I was missing during the fall when I was trying to lay out the original amplifier circuit. Using my new knowledge of Altium’s multichannel capabilities, I captured Igor’s new design into the schematics editor of Altium Designer. With proper nested schematic sheets, the entire 30 channel amplifier/6 channel summer design was compressed into just 4 schematic sheets, vs. the ~40 or so that would have been required had I laid out the complete schematics of the old design.

I spent about a week and a half trying to figure out how to handle nesting independent nets from a repeated subsheet into another repeated subsheet which also produces independent nets from the nets of the first sheet. This sounds somewhat complicated, and I suppose perhaps it is a somewhat unique situation, since none of the ~5 sample multichannel projects included with Altium had such a construction in them. Basically, each summing circuit has five amplifier subcircuits, each of which puts out its own signal independent of the other four. From the perspective of the entire board, there are 6 summers, each of which has five independent signals coming from the amplifiers, and one summed signal. Determining how to get Altium to realize the proper connections from each individual amplifier, through that amplifier’s summer, to the main schematic was a complicated mess of naming conventions, but eventually I was able to make Altium reflect all of the appropriate connections in the PCB view. Though there are a few net naming issues still to be resolved, this problem has mostly been ironed out.

The final few weeks of the semester were spent laying out amplifier components in the PCB view of Altium. As of right now, a compact design for an amplifier measuring 0.183”x~1.3” has been completed. Making use of 0201 size components, this amplifier is approximately .2” shorter than the old design, despite incorporating an extra transistor. The amplifier design features an isolating ground trace running the length of the amplifier to prevent crosstalk between channels. A prototype layout of the summing circuit has also been completed, though some layout issues there remain to be resolved over the summer.

===Related Files===
*[http://zeus.phys.uconn.edu/halld/tagger/electronics/design-6-2009/Progress20090505.zip Design Snapshot 5/5/2009]
**Backplane
***Backplane.PrjPcb (Altium Project File)
***Backplane.PcbDoc (Altium PCB File)
***Analog Connector.SchDoc, Digital Connector.SchDoc, LEMO.SchDoc (Altium Schematics)
***Backplane.pdf (SmartPDF File of the schematics and PCB layout)
**Amplifier Board
***Analog Board.PrjPcb (Altium Project File)
***Amplifier Board.PcbDoc (Altium PCB File)
***Main.SchDoc, Amplifier.SchDoc, Summer.SchDoc, Voltage References.SchDoc (Altium Schematics)
***Analog Board.pdf (SmartPDF File of the schematics and PCB layout
****The SmartPDF shows the entire PCB workspace, including components that have not yet been placed on the physical PCB.
****The bottom left corner of the PCB view shows a proof-of-concept 5 amplifiers/1 summer layout.
****Finding AMP6 using the PDF bookmarks shows the prototype amplifier layout that resolves mismatched footprint issues (indicated in green in the image farther up on this page).

== Summary of Fall 2009 Work ==

=== Mid-Semester Update, 11/12/2009 ===
We now have one fully working prototype of the SiPM Digital Control Board, and the SiPM Amplifier Board is currently being manufactured and assembled by Sierra Circuits, Inc. The backplane design is nearly complete and will be going out for quoting within a week.

Here is a zip file containing the most recent versions of the tagger files: [http://zeus.phys.uconn.edu/halld/tagger/electronics/design-11-2009/TaggerMicroscopeProgress20091112.zip Design Snapshot 11/12/2009]

A few notes about these files:
*There are four subfolders in the zip file. The folders for the three PCBs are clearly labelled. Each PCB folder has one project file (.PrjPcb) which can be opened in Altium Designer. Each project file refers to only one PcbDoc file, making it easy to figure out what you should look at to see the board.
*The SiPM digital control board project has 4 shelved polygons which should be restored (Tools->Polygon Pours->Restore 4 shelved polyons) to see the state of the board as it was last manufactured. Revisions from the testing process have not yet been entered into Altium but can be reviewed on this wiki: [[Digital control board debugging notes]]
*The SiPM amplifier (analog) board project will give an error message that it was unable to find "Test PCB.PcbDoc". Please ignore this. The file was intentionally omitted to prevent confusion, and is not related to the actual design.
*The backplane project will give an error message that it was unable to find "Backplane_New.PcbDoc". Please ignore this. The file was intentionally omitted to prevent confusion, and is not related to the actual design.

=== End of Semester Update ===
This semester, a lot of progress has been made on the tagger electronics. The digital control board is now onto revision 2.0, the amplifier board is in production, and the backplane is awaiting completion of the purchase order for production to begin. It is exciting to say that the bulk of the work is now finally complete. Remaining for the spring are the tasks of testing the amplifier board, and seeing that everything fits into the backplane. Here are some details about what I accomplished this semester, as well as links to the most recent project files.

==== Digital Control Board ====
The semester began with the digital control board prototypes sitting on lab bench waiting to be tested. My job was primarily to design the boards, not to debug them, though I still played an integral part in the testing process. We were all relieved that none of the boards appeared to smoke immediately when we first applied power, though there were a few confusing problems that had to be sorted out. Most of these problems are described in detail on the [[Digital control board debugging notes]] page. More or less, we had to solder a pin that wasn't connected, replace the crystal oscillator with a CMOS oscillator, and rewire few traces that were accidentally connected to pins intended for other signals. I won't repeat all of the changes we made here since it would be redundant to the page that already discusses it, but the important part is that we have one board that is fully operational, and the version 2.0 schematics/layout reflecting all these changes are complete. I anticipate that production of the version 2.0 boards will occur at the beginning of the spring 2010 semester.

There is still one lingering problem with the digital board design that has not yet been resolved, however. Even after all of the version 2.0 changes were implemented on the version 1.0 boards, only one of the three boards produced actually functioned properly. For a reason unknown to us, two of the boards ended up with their digital to analog converters burning up and smoking. We thoroughly reviewed the schematics and the layout, and found nothing miswired. Furthermore, we analyzed the placement of the ball grid array DAC to the best of our ability, and determined that a misalignment of balls is not the cause of the failure. All of our power supplies are stable, properly decoupled, and grounded as called for by DAC's manufacturer. Currently, the best hypothesis for the failure of 2 of the 3 DACs is that one or more of the absolute maximum ratings must have been exceeded at some point during the assembly process. Analog Devices lists fairly specific specs with small tolerances relating to maximum temperature and the length of time which the DAC may spend inside a reflow oven. We have run into some difficultly trying to find out from the boards' assembler whether they followed the published specs for the assembly process, but we intend to keep trying until the cause of the DAC failure has been resolved.

==== Amplifier Board ====
Throughout the summer and the beginning of the fall semester, I completed the design for the SiPM Amplifier Board, version 1.0. All 30 channels have been implemented along with their summing circuits. As I mentioned in the mid semester update above, this board is being manufactured and assembled by Sierra Circuits, Inc. Some unexpected setbacks occurred in the assembly process that delayed the boards somewhat, but I believe everything is now on track for delivery of the finished product before the start of the spring semester. A number of problems relating to minimum quantities of parts, as well as part naming conventions have now been resolved, and the assembly process should be complete in several weeks.

==== Backplane ====
The backplane design, version 1.0, has also been completed. Sierra Circuits will be manufacturing the backplane, which we will assemble ourselves. The backplane is a particularly interesting PCB from a manufacturing standpoint, because it is designed to be completely light proof. Since the backplane is the only material standing between the whole of Hall D and the inside of the tagger microscope dark box, opacity of the board is particularly important.

Most PCBs with internal copper layers are already fairly opaque, because the copper blocks light from transmitting through the FR-4 and prepreg. Through hole components do not particulary compromise board opacity, because the holes are plugged with component pins and solder. What does have a greater affect on the opaqueness of a board, however, is the thermal reliefs by which through hole pins and vias connect to internal plane layers. These reliefs are designed to aid in the soldering process by minimizing the amount of copper that is directly connected to the plating in the hole. A typical relief consists of four 7-10 mil traces connecting the hole's plating to the internal plane. The plane itself remains about 20 mil away from the hole, to prevent conduction of heat during the soldering process. Unfortunately, this means that there is a small gap in which there is only FR-4 to stop light from passing through the board. Since FR-4 is transparent, this poses a problem for our design. We were able work with Sierra Circuits to come up with a board design that includes an internal layer of special black FR-4 to prevent light leakage through the heat reliefs. While this is certainly not a standard feature, Sierra was confident that they could implement it for us, and we look forward to testing the boards' opacity in the spring.

==== Project Design Snapshot ====
Here is a link to the most project files: INSERT LINK TO DESIGN SNAPSHOT 12/17/2009 HERE

A few notes about these files:
*There are four subfolders in the zip file. The folders for the three PCBs are clearly labelled. Each PCB folder has one project file (.PrjPcb) which can be opened in Altium Designer. Each project file refers to only one PcbDoc file, making it easy to figure out what you should look at to see the board.
*The SiPM amplifier (analog) board project will give an error message that it was unable to find "Test PCB.PcbDoc". Please ignore this. The file was intentionally omitted to prevent confusion, and is not related to the actual design.
*The backplane project will give an error message that it was unable to find "Backplane_New.PcbDoc". Please ignore this. The file was intentionally omitted to prevent confusion, and is not related to the actual design.

Woody Underwood

2009-12-17T22:15:57Z

Underwood: /* Backplane */

== About Me ==
My name is Woody Underwood. I'm a junior entering my seventh semester in the physics program at UConn. Since the summer of 2008, I've been working in the lab of Dr. Richard Jones designing electronics for the US Department of Energy's GlueX experiment. My assignment is to develop three circuit boards that work together to tag photons coming from the diamond radiator. My circuitry essentially measures (indirectly) the energy of these photons in order to determine if they are of interest to GlueX. The three boards I am designing consist of a digital board, an analog board, and a connecting backplane.

== About My Circuitry ==
Electrons leaving the diamond radiator are deflected by a magnetic field into an array of scintillating fibres, producing photons. Wave guides carry these photons to SiPMs (silicon photomultipliers) mounted on the analog circuit board. The analog board contains transimpedance amplifiers and summing circuitry to condition the signals for digitization.

The sensitivity of the SiPMs and the gain of the amplifiers on the analog board are controlled both by the power supply VCC and bias voltages supplied from the digital board. The digital board receives commands from a computer via ethernet, and uses a 32-channel DAC to output appropriate bias voltages to the SiPMs on the analog board. The digital and analog boards are connected by means of a backplane, which is also responsible for providing power and grounds to both boards.

== Summary of Fall 2008 Work ==
All circuitry design work was done using Altium Designer. The digital board was the first to be designed. The first step in designing the digital board was to review the list of key components that had already been selected by Igor and Dr. Jones. These components included such things as the Xilinx Spartan-3A FPGA, and the Analog Devices AD5535 DAC. I began by looking through datasheets for these components to find out their needs, including power and decoupling requirements. I reviewed the pinout diagrams, and then looked through Altium’s standard libraries to find components that matched (in many cases the particular component I was looking for was not in the library, but a similar footprint or schematic symbol was). For components without matching schematic symbols, I entered pinout information from the datasheets into Microsoft Excel, using a layout compatible with Altium’s Smart Grid Insert function. Then, I was able to literally copy and paste pin information from Excel into Altium to generate the schematic symbols I needed.

Once I had appropriate schematic symbols available for all parts, I began making appropriate connections in the schematic view in Altium. Though tedious, this task was not exceedingly difficult. I finished the schematics in several days, and then moved on to PCB design. I switched into Altium's PCB view. The footprints corresponding to the components I used in the schematics were automatically inserted by Altium. My job was then to position these components in logical places on the board and make all of the connections corresponding to the nets defined in the schematics.

Due to the large number of components being placed in the limited space available on the digital board, Altium's auto-router proved completely useless. Therefore, I routed the board manually. Despite Altium's revolutionary convergence of schematic and PCB design into a single program, this was no easy task. During the routing process, I had to take into account not only the connections that had to be made, but also things such as avoiding crosstalk and minimizing trace length for sensitive components. I was able to complete routing after several weeks of work. The digital board design has since been completed and the board has been printed. It is currently awaiting assembly.

The analog board provided a host of new challenges. The basic schematic for the transimpedance amplifier on the analog board was completed by Igor and Dr. Jones before the semester. Inputting the schematic into Altium was not very difficult. However, one problem I encountered was that the analog board contains 32 copies of this amplifier circuitry. After failing to find any way to insert multiple copies of both the schematic and its corresponding PCB layout, I decided to insert only single copies of each schematic page, and copy and paste the PCB layout to produce 32 copies of the amplifier circuitry. At first this seemed like a quick and easy way to get all of the necessary circuitry onto the PCB. However, I eventually discovered that this procedure would lead to major problems with the board assembly process (due to duplicate component designators, and for other reasons). Fortunately, this revelation came around the same time that Igor and Dr. Jones found a problem with the performance of the amplifier circuit. Making any changes to the amplifier circuit at this point will require a major reroute of all the traces on the analog board. Since the board needs to be completely redesigned anyway, this will give me another chance to find a way to match schematics with all 32 copies of the amplifier circuitry.

The backplane design is currently in progress. It should be relatively easy to complete. All that remains to be done is to add the LEMO connectors and power inputs. The board is simple enough that it can be routed completely by the auto-router, though a quick hand routing will probably be superior. I anticipate that I can complete the backplane with a few days of concentrated work over break.

Included below are links to the files I have been working on. Included in the files for each board is a "SmartPDF," viewable in Adobe Reader. For those without Altium Designer, these may be the best files to look at. They include complete schematics and PCB layout, and are also indexed by component.

Any questions about the tagger circuitry can be directed to me at [mailto:mitchell.underwood@uconn.edu mitchell.underwood@uconn.edu]

=== Related Files ===
* [http://zeus.phys.uconn.edu/halld/tagger/electronics/design-12-2008/DigitalBoard.zip DigitalBoard.zip]:
**Altium Project File (SiPM Control Board.PrjPcb)
**Altium PCB Layout File (Prototype1.PcbDoc)
**Altium Schematic Files (*.SchDoc)
**Altium Annotation Document (SiPM Control Board.Annotation)
***Not used, but generated by Altium when opening the project
**Altium PRJPCBSTRUCTURE File (SiPM Control Board.PRJPCBSTRUCTURE)
***Not used, but generated by Altium when opening the project)
**“SmartPDF” of the board and schematics (SiPM Control Board.pdf)
***Can be used to explore the PCB layout and schematics without needing Altium
**Pick and Place File for board population (Pick Place for Prototype1.txt)
***Used by board assembler
**NC Drill Files (Prototype1.txt, Prototype1.DRR, Prototype1.DRL)
***Used by board printer
**Gerber Files for all layers (in folder Gerbers)
***Used by board printer
**Altium CAMtastic file (CAMtastic4 FINAL.Cam)
***Basically a composite of all the Gerbers
**Photos and 3D rendering of populated board
***In folder “Photos”
**EMF Files showing different layers
***In folder “EMF Renderings”
**AutoCad File of PCB (Prototype1 Autocad.DWG)
**Altium Library of Custom Footprints for Digital Board (GlueX IC Library.SchLib)
***Current as of completion of digital board
***This library has since been updated for the backplane

*[http://zeus.phys.uconn.edu/halld/tagger/electronics/design-12-2008/Analog%20Board%2020081211.zip Analog Board 20081211.zip]:
**Altium Project File (AnalogBoard.PrjPcb)
**Altium PCB Layout File (AnalogBoardPCB.PcbDoc)
**Altium Schematic Files (Amplifer1.SchDoc, Summer.SchDoc)
**“SmartPDF” of the board and schematics (AnalogBoard.pdf)
**Altium Component Definition for SiPM (SiPM Library.PcbLib)
***Contains part footprint and pin information for the SiPM component

*[http://zeus.phys.uconn.edu/halld/tagger/electronics/design-12-2008/Backplane%2020081211.zip Backplane 20081211.zip]
**Altium Project File (Backplane.PrjPcb)
**Alitum PCB Layout File (Backplane.PcbDoc)
**Altium Schematic Files (Analog Connector.SchDoc, Digital Connector.SchDoc)
***Analog Connector = Eurocard to analog board
***Digital Connector = Eurocard to digital board, +3.3V voltage regulator, and location identifier jumper
***LEMO connections not yet included in these schematics
**“SmartPDF” of the board and schematics (Backplane.pdf)
**Pin layout files used to define pinouts for custom components (Pin Layout, 96 pin connector.xlsx, Pinouts.xlsx)
***Pin Layout, 96 pin connector = pinout definition for 96 pin Eurocard connector
***Pinouts.xlsx = pinout definitions for digital board, which were reused for the 48 pin digital Eurocard receptacle on backplane
**Altium Library of Custom Components (GlueX IC Library.SchLib)
***UPDATED to include new backplane components
***An older version of this library was used for the digital board

==Summary of Spring 2009 Work==

At the end of the fall semester, Dr. Jones, Igor, and I determined that the amplifier/summing circuit we had designed simply didn’t have sufficient performance characteristics to be useful for GlueX. During the beginning of the spring semester, Igor came up with a new design, utilizing more transistors, to provide the high gain, fast response, picosecond resolution amplifier that we needed. The design performed flawlessly both in MatLab simulations and in a handmade single channel prototype. The first of my goals for the spring 2009 semester was to capture the schematic for this new amplifier into Altium designer, and layout a new amplifier board. The second of my goals, of course, was to complete production of the digital control board prototypes.

[[Image:Digital Board, Populated.JPG|thumb|The populated digital board, with a tube of Chap-BlockTM for size comparison.]] Since the fall semester left us with three unpopulated digital control board PCBs, getting those PCBs assembled with their components was the first priority. I began the semester by tracking down all of the components we needed (some of which were selected at the end of the fall semester), and making appropriate substitutions for components whose availability had changed since the fall. In the process of selecting these components, I noticed several places where it seemed like power consumption on the board may be somewhat high. To fix this, I developed a spreadsheet in Microsoft Excel that calculates optimal resistor values to use for to obtain a specified voltage divider stiffness. With this tool, I was able to optimize power consumption across the board, and select appropriate components. Once all components had been selected, ordered, and received, we sent the order out to Screamin’ Circuits for assembly. The boards came back several weeks later, and are currently awaiting testing by some undergraduates who will be in the lab this summer.

While Igor was finalizing his amplifier/summing circuit, I worked briefly on design of the backplane. A number of details regarding trace impedance and board dimensions were ironed out. Nonetheless, many problems still remain which I will need to tackle over the summer. The first of these problems is that we have yet to find an appropriate low cost coaxial connector to route signals off the backplane. In addition, screws with which to mount the backplane to the tagger must be selected so that appropriate holes can be created for them on the PCB.

Once we were satisfied that the amplifier/summing circuit performed as required, I shifted work from the backplane to the amplifier board. Around the same time, I began working on a poster to present my work at the Frontiers in Undergraduate Research Exhibition held during Open House Weekend here at UConn. If you’re interested in my poster, check it out here.

[[Image:Amplifier-Summer-Laid-out.gif|thumb|A prototype layout of 5 amplifier channels and a summing circuit. Actual size is ~1.6" tall. Areas in green represent problems to be resolved over summer 2009. A prototype amplifier with no green spots has been designed and will be replicated to this design soon.]] To start the amplifier/summing circuit project, I searched high and low for information about how to handle multi-channel designs in Altium. Not surprisingly, the first Google result on the query “multichannel design Altium” had everything I was missing during the fall when I was trying to lay out the original amplifier circuit. Using my new knowledge of Altium’s multichannel capabilities, I captured Igor’s new design into the schematics editor of Altium Designer. With proper nested schematic sheets, the entire 30 channel amplifier/6 channel summer design was compressed into just 4 schematic sheets, vs. the ~40 or so that would have been required had I laid out the complete schematics of the old design.

I spent about a week and a half trying to figure out how to handle nesting independent nets from a repeated subsheet into another repeated subsheet which also produces independent nets from the nets of the first sheet. This sounds somewhat complicated, and I suppose perhaps it is a somewhat unique situation, since none of the ~5 sample multichannel projects included with Altium had such a construction in them. Basically, each summing circuit has five amplifier subcircuits, each of which puts out its own signal independent of the other four. From the perspective of the entire board, there are 6 summers, each of which has five independent signals coming from the amplifiers, and one summed signal. Determining how to get Altium to realize the proper connections from each individual amplifier, through that amplifier’s summer, to the main schematic was a complicated mess of naming conventions, but eventually I was able to make Altium reflect all of the appropriate connections in the PCB view. Though there are a few net naming issues still to be resolved, this problem has mostly been ironed out.

The final few weeks of the semester were spent laying out amplifier components in the PCB view of Altium. As of right now, a compact design for an amplifier measuring 0.183”x~1.3” has been completed. Making use of 0201 size components, this amplifier is approximately .2” shorter than the old design, despite incorporating an extra transistor. The amplifier design features an isolating ground trace running the length of the amplifier to prevent crosstalk between channels. A prototype layout of the summing circuit has also been completed, though some layout issues there remain to be resolved over the summer.

===Related Files===
*[http://zeus.phys.uconn.edu/halld/tagger/electronics/design-6-2009/Progress20090505.zip Design Snapshot 5/5/2009]
**Backplane
***Backplane.PrjPcb (Altium Project File)
***Backplane.PcbDoc (Altium PCB File)
***Analog Connector.SchDoc, Digital Connector.SchDoc, LEMO.SchDoc (Altium Schematics)
***Backplane.pdf (SmartPDF File of the schematics and PCB layout)
**Amplifier Board
***Analog Board.PrjPcb (Altium Project File)
***Amplifier Board.PcbDoc (Altium PCB File)
***Main.SchDoc, Amplifier.SchDoc, Summer.SchDoc, Voltage References.SchDoc (Altium Schematics)
***Analog Board.pdf (SmartPDF File of the schematics and PCB layout
****The SmartPDF shows the entire PCB workspace, including components that have not yet been placed on the physical PCB.
****The bottom left corner of the PCB view shows a proof-of-concept 5 amplifiers/1 summer layout.
****Finding AMP6 using the PDF bookmarks shows the prototype amplifier layout that resolves mismatched footprint issues (indicated in green in the image farther up on this page).

== Summary of Fall 2009 Work ==

=== Mid-Semester Update, 11/12/2009 ===
We now have one fully working prototype of the SiPM Digital Control Board, and the SiPM Amplifier Board is currently being manufactured and assembled by Sierra Circuits, Inc. The backplane design is nearly complete and will be going out for quoting within a week.

Here is a zip file containing the most recent versions of the tagger files: [http://zeus.phys.uconn.edu/halld/tagger/electronics/design-11-2009/TaggerMicroscopeProgress20091112.zip Design Snapshot 11/12/2009]

A few notes about these files:
*There are four subfolders in the zip file. The folders for the three PCBs are clearly labelled. Each PCB folder has one project file (.PrjPcb) which can be opened in Altium Designer. Each project file refers to only one PcbDoc file, making it easy to figure out what you should look at to see the board.
*The SiPM digital control board project has 4 shelved polygons which should be restored (Tools->Polygon Pours->Restore 4 shelved polyons) to see the state of the board as it was last manufactured. Revisions from the testing process have not yet been entered into Altium but can be reviewed on this wiki: [[Digital control board debugging notes]]
*The SiPM amplifier (analog) board project will give an error message that it was unable to find "Test PCB.PcbDoc". Please ignore this. The file was intentionally omitted to prevent confusion, and is not related to the actual design.
*The backplane project will give an error message that it was unable to find "Backplane_New.PcbDoc". Please ignore this. The file was intentionally omitted to prevent confusion, and is not related to the actual design.

=== End of Semester Update ===
This semester, a lot of progress has been made on the tagger electronics. The digital control board is now onto revision 2.0, the amplifier board is in production, and the backplane is awaiting completion of the purchase order for production to begin. It is exciting to say that the bulk of the work is now finally complete. Remaining for the spring are the tasks of testing the amplifier board, and seeing that everything fits into the backplane. Here are some details about what I accomplished this semester, as well as links to the most recent project files.

==== Digital Control Board ====
The semester began with the digital control board prototypes sitting on lab bench waiting to be tested. My job was primarily to design the boards, not to debug them, though I still played an integral part in the testing process. We were all relieved that none of the boards appeared to smoke immediately when we first applied power, though there were a few confusing problems that had to be sorted out. Most of these problems are described in detail on the [[Digital control board debugging notes]] page. More or less, we had to solder a pin that wasn't connected, replace the crystal oscillator with a CMOS oscillator, and rewire few traces that were accidentally connected to pins intended for other signals. I won't repeat all of the changes we made here since it would be redundant to the page that already discusses it, but the important part is that we have one board that is fully operational, and the version 2.0 schematics/layout reflecting all these changes are complete. I anticipate that production of the version 2.0 boards will occur at the beginning of the spring 2010 semester.

There is still one lingering problem with the digital board design that has not yet been resolved, however. Even after all of the version 2.0 changes were implemented on the version 1.0 boards, only one of the three boards produced actually functioned properly. For a reason unknown to us, two of the boards ended up with their digital to analog converters burning up and smoking. We thoroughly reviewed the schematics and the layout, and found nothing miswired. Furthermore, we analyzed the placement of the ball grid array DAC to the best of our ability, and determined that a misalignment of balls is not the cause of the failure. All of our power supplies are stable, properly decoupled, and grounded as called for by DAC's manufacturer. Currently, the best hypothesis for the failure of 2 of the 3 DACs is that one or more of the absolute maximum ratings must have been exceeded at some point during the assembly process. Analog Devices lists fairly specific specs with small tolerances relating to maximum temperature and the length of time which the DAC may spend inside a reflow oven. We have run into some difficultly trying to find out from the boards' assembler whether they followed the published specs for the assembly process, but we intend to keep trying until the cause of the DAC failure has been resolved.

==== Amplifier Board ====
Throughout the summer and the beginning of the fall semester, I completed the design for the SiPM Amplifier Board, version 1.0. All 30 channels have been implemented along with their summing circuits. As I mentioned in the mid semester update above, this board is being manufactured and assembled by Sierra Circuits, Inc. Some unexpected setbacks occurred in the assembly process that delayed the boards somewhat, but I believe everything is now on track for delivery of the finished product before the start of the spring semester. A number of problems relating to minimum quantities of parts, as well as part naming conventions have now been resolved, and the assembly process should be complete in several weeks.

==== Backplane ====
The backplane design, version 1.0, has also been completed. Sierra Circuits will be manufacturing the backplane, which we will assemble ourselves. The backplane is a particularly interesting PCB from a manufacturing standpoint, because it is designed to be completely light proof. Since the backplane is the only material standing between the whole of Hall D and the inside of the tagger microscope dark box, opacity of the board is particularly important.

Most PCBs with internal copper layers are already fairly opaque, because the copper blocks light from transmitting through the FR-4 and prepreg. Through hole components do not particulary compromise board opacity, because the holes are plugged with component pins and solder. What does have a greater affect on the opaqueness of a board, however, is the thermal reliefs by which through hole pins and vias connect to internal plane layers. These reliefs are designed to aid in the soldering process by minimizing the amount of copper that is directly connected to the plating in the hole. A typical relief consists of four 7-10 mil traces connecting the hole's plating to the internal plane. The plane itself remains about 20 mil away from the hole, to prevent conduction of heat during the soldering process. Unfortunately, this means that there is a small gap in which there is only FR-4 to stop light from passing through the board. Since FR-4 is transparent, this poses a problem for our design. We were able work with Sierra Circuits to come up with a board design that includes an internal layer of special black FR-4 to prevent light leakage through the heat reliefs. While this is certainly not a standard feature, Sierra was confident that they could implement it for us, and we look forward to testing the boards' opacity in the spring.

==== Project Design Snapshot ====
Here is a link to the most project files: INSERT LINK TO DESIGN SNAPSHOT 12/17/2009 HERE

The files are all clearly labelled.

Woody Underwood

2009-12-17T22:01:20Z

Underwood: /* Fall 2009 Work */

== About Me ==
My name is Woody Underwood. I'm a junior entering my seventh semester in the physics program at UConn. Since the summer of 2008, I've been working in the lab of Dr. Richard Jones designing electronics for the US Department of Energy's GlueX experiment. My assignment is to develop three circuit boards that work together to tag photons coming from the diamond radiator. My circuitry essentially measures (indirectly) the energy of these photons in order to determine if they are of interest to GlueX. The three boards I am designing consist of a digital board, an analog board, and a connecting backplane.

== About My Circuitry ==
Electrons leaving the diamond radiator are deflected by a magnetic field into an array of scintillating fibres, producing photons. Wave guides carry these photons to SiPMs (silicon photomultipliers) mounted on the analog circuit board. The analog board contains transimpedance amplifiers and summing circuitry to condition the signals for digitization.

The sensitivity of the SiPMs and the gain of the amplifiers on the analog board are controlled both by the power supply VCC and bias voltages supplied from the digital board. The digital board receives commands from a computer via ethernet, and uses a 32-channel DAC to output appropriate bias voltages to the SiPMs on the analog board. The digital and analog boards are connected by means of a backplane, which is also responsible for providing power and grounds to both boards.

== Summary of Fall 2008 Work ==
All circuitry design work was done using Altium Designer. The digital board was the first to be designed. The first step in designing the digital board was to review the list of key components that had already been selected by Igor and Dr. Jones. These components included such things as the Xilinx Spartan-3A FPGA, and the Analog Devices AD5535 DAC. I began by looking through datasheets for these components to find out their needs, including power and decoupling requirements. I reviewed the pinout diagrams, and then looked through Altium’s standard libraries to find components that matched (in many cases the particular component I was looking for was not in the library, but a similar footprint or schematic symbol was). For components without matching schematic symbols, I entered pinout information from the datasheets into Microsoft Excel, using a layout compatible with Altium’s Smart Grid Insert function. Then, I was able to literally copy and paste pin information from Excel into Altium to generate the schematic symbols I needed.

Once I had appropriate schematic symbols available for all parts, I began making appropriate connections in the schematic view in Altium. Though tedious, this task was not exceedingly difficult. I finished the schematics in several days, and then moved on to PCB design. I switched into Altium's PCB view. The footprints corresponding to the components I used in the schematics were automatically inserted by Altium. My job was then to position these components in logical places on the board and make all of the connections corresponding to the nets defined in the schematics.

Due to the large number of components being placed in the limited space available on the digital board, Altium's auto-router proved completely useless. Therefore, I routed the board manually. Despite Altium's revolutionary convergence of schematic and PCB design into a single program, this was no easy task. During the routing process, I had to take into account not only the connections that had to be made, but also things such as avoiding crosstalk and minimizing trace length for sensitive components. I was able to complete routing after several weeks of work. The digital board design has since been completed and the board has been printed. It is currently awaiting assembly.

The analog board provided a host of new challenges. The basic schematic for the transimpedance amplifier on the analog board was completed by Igor and Dr. Jones before the semester. Inputting the schematic into Altium was not very difficult. However, one problem I encountered was that the analog board contains 32 copies of this amplifier circuitry. After failing to find any way to insert multiple copies of both the schematic and its corresponding PCB layout, I decided to insert only single copies of each schematic page, and copy and paste the PCB layout to produce 32 copies of the amplifier circuitry. At first this seemed like a quick and easy way to get all of the necessary circuitry onto the PCB. However, I eventually discovered that this procedure would lead to major problems with the board assembly process (due to duplicate component designators, and for other reasons). Fortunately, this revelation came around the same time that Igor and Dr. Jones found a problem with the performance of the amplifier circuit. Making any changes to the amplifier circuit at this point will require a major reroute of all the traces on the analog board. Since the board needs to be completely redesigned anyway, this will give me another chance to find a way to match schematics with all 32 copies of the amplifier circuitry.

The backplane design is currently in progress. It should be relatively easy to complete. All that remains to be done is to add the LEMO connectors and power inputs. The board is simple enough that it can be routed completely by the auto-router, though a quick hand routing will probably be superior. I anticipate that I can complete the backplane with a few days of concentrated work over break.

Included below are links to the files I have been working on. Included in the files for each board is a "SmartPDF," viewable in Adobe Reader. For those without Altium Designer, these may be the best files to look at. They include complete schematics and PCB layout, and are also indexed by component.

Any questions about the tagger circuitry can be directed to me at [mailto:mitchell.underwood@uconn.edu mitchell.underwood@uconn.edu]

=== Related Files ===
* [http://zeus.phys.uconn.edu/halld/tagger/electronics/design-12-2008/DigitalBoard.zip DigitalBoard.zip]:
**Altium Project File (SiPM Control Board.PrjPcb)
**Altium PCB Layout File (Prototype1.PcbDoc)
**Altium Schematic Files (*.SchDoc)
**Altium Annotation Document (SiPM Control Board.Annotation)
***Not used, but generated by Altium when opening the project
**Altium PRJPCBSTRUCTURE File (SiPM Control Board.PRJPCBSTRUCTURE)
***Not used, but generated by Altium when opening the project)
**“SmartPDF” of the board and schematics (SiPM Control Board.pdf)
***Can be used to explore the PCB layout and schematics without needing Altium
**Pick and Place File for board population (Pick Place for Prototype1.txt)
***Used by board assembler
**NC Drill Files (Prototype1.txt, Prototype1.DRR, Prototype1.DRL)
***Used by board printer
**Gerber Files for all layers (in folder Gerbers)
***Used by board printer
**Altium CAMtastic file (CAMtastic4 FINAL.Cam)
***Basically a composite of all the Gerbers
**Photos and 3D rendering of populated board
***In folder “Photos”
**EMF Files showing different layers
***In folder “EMF Renderings”
**AutoCad File of PCB (Prototype1 Autocad.DWG)
**Altium Library of Custom Footprints for Digital Board (GlueX IC Library.SchLib)
***Current as of completion of digital board
***This library has since been updated for the backplane

*[http://zeus.phys.uconn.edu/halld/tagger/electronics/design-12-2008/Analog%20Board%2020081211.zip Analog Board 20081211.zip]:
**Altium Project File (AnalogBoard.PrjPcb)
**Altium PCB Layout File (AnalogBoardPCB.PcbDoc)
**Altium Schematic Files (Amplifer1.SchDoc, Summer.SchDoc)
**“SmartPDF” of the board and schematics (AnalogBoard.pdf)
**Altium Component Definition for SiPM (SiPM Library.PcbLib)
***Contains part footprint and pin information for the SiPM component

*[http://zeus.phys.uconn.edu/halld/tagger/electronics/design-12-2008/Backplane%2020081211.zip Backplane 20081211.zip]
**Altium Project File (Backplane.PrjPcb)
**Alitum PCB Layout File (Backplane.PcbDoc)
**Altium Schematic Files (Analog Connector.SchDoc, Digital Connector.SchDoc)
***Analog Connector = Eurocard to analog board
***Digital Connector = Eurocard to digital board, +3.3V voltage regulator, and location identifier jumper
***LEMO connections not yet included in these schematics
**“SmartPDF” of the board and schematics (Backplane.pdf)
**Pin layout files used to define pinouts for custom components (Pin Layout, 96 pin connector.xlsx, Pinouts.xlsx)
***Pin Layout, 96 pin connector = pinout definition for 96 pin Eurocard connector
***Pinouts.xlsx = pinout definitions for digital board, which were reused for the 48 pin digital Eurocard receptacle on backplane
**Altium Library of Custom Components (GlueX IC Library.SchLib)
***UPDATED to include new backplane components
***An older version of this library was used for the digital board

==Summary of Spring 2009 Work==

At the end of the fall semester, Dr. Jones, Igor, and I determined that the amplifier/summing circuit we had designed simply didn’t have sufficient performance characteristics to be useful for GlueX. During the beginning of the spring semester, Igor came up with a new design, utilizing more transistors, to provide the high gain, fast response, picosecond resolution amplifier that we needed. The design performed flawlessly both in MatLab simulations and in a handmade single channel prototype. The first of my goals for the spring 2009 semester was to capture the schematic for this new amplifier into Altium designer, and layout a new amplifier board. The second of my goals, of course, was to complete production of the digital control board prototypes.

[[Image:Digital Board, Populated.JPG|thumb|The populated digital board, with a tube of Chap-BlockTM for size comparison.]] Since the fall semester left us with three unpopulated digital control board PCBs, getting those PCBs assembled with their components was the first priority. I began the semester by tracking down all of the components we needed (some of which were selected at the end of the fall semester), and making appropriate substitutions for components whose availability had changed since the fall. In the process of selecting these components, I noticed several places where it seemed like power consumption on the board may be somewhat high. To fix this, I developed a spreadsheet in Microsoft Excel that calculates optimal resistor values to use for to obtain a specified voltage divider stiffness. With this tool, I was able to optimize power consumption across the board, and select appropriate components. Once all components had been selected, ordered, and received, we sent the order out to Screamin’ Circuits for assembly. The boards came back several weeks later, and are currently awaiting testing by some undergraduates who will be in the lab this summer.

While Igor was finalizing his amplifier/summing circuit, I worked briefly on design of the backplane. A number of details regarding trace impedance and board dimensions were ironed out. Nonetheless, many problems still remain which I will need to tackle over the summer. The first of these problems is that we have yet to find an appropriate low cost coaxial connector to route signals off the backplane. In addition, screws with which to mount the backplane to the tagger must be selected so that appropriate holes can be created for them on the PCB.

Once we were satisfied that the amplifier/summing circuit performed as required, I shifted work from the backplane to the amplifier board. Around the same time, I began working on a poster to present my work at the Frontiers in Undergraduate Research Exhibition held during Open House Weekend here at UConn. If you’re interested in my poster, check it out here.

[[Image:Amplifier-Summer-Laid-out.gif|thumb|A prototype layout of 5 amplifier channels and a summing circuit. Actual size is ~1.6" tall. Areas in green represent problems to be resolved over summer 2009. A prototype amplifier with no green spots has been designed and will be replicated to this design soon.]] To start the amplifier/summing circuit project, I searched high and low for information about how to handle multi-channel designs in Altium. Not surprisingly, the first Google result on the query “multichannel design Altium” had everything I was missing during the fall when I was trying to lay out the original amplifier circuit. Using my new knowledge of Altium’s multichannel capabilities, I captured Igor’s new design into the schematics editor of Altium Designer. With proper nested schematic sheets, the entire 30 channel amplifier/6 channel summer design was compressed into just 4 schematic sheets, vs. the ~40 or so that would have been required had I laid out the complete schematics of the old design.

I spent about a week and a half trying to figure out how to handle nesting independent nets from a repeated subsheet into another repeated subsheet which also produces independent nets from the nets of the first sheet. This sounds somewhat complicated, and I suppose perhaps it is a somewhat unique situation, since none of the ~5 sample multichannel projects included with Altium had such a construction in them. Basically, each summing circuit has five amplifier subcircuits, each of which puts out its own signal independent of the other four. From the perspective of the entire board, there are 6 summers, each of which has five independent signals coming from the amplifiers, and one summed signal. Determining how to get Altium to realize the proper connections from each individual amplifier, through that amplifier’s summer, to the main schematic was a complicated mess of naming conventions, but eventually I was able to make Altium reflect all of the appropriate connections in the PCB view. Though there are a few net naming issues still to be resolved, this problem has mostly been ironed out.

The final few weeks of the semester were spent laying out amplifier components in the PCB view of Altium. As of right now, a compact design for an amplifier measuring 0.183”x~1.3” has been completed. Making use of 0201 size components, this amplifier is approximately .2” shorter than the old design, despite incorporating an extra transistor. The amplifier design features an isolating ground trace running the length of the amplifier to prevent crosstalk between channels. A prototype layout of the summing circuit has also been completed, though some layout issues there remain to be resolved over the summer.

===Related Files===
*[http://zeus.phys.uconn.edu/halld/tagger/electronics/design-6-2009/Progress20090505.zip Design Snapshot 5/5/2009]
**Backplane
***Backplane.PrjPcb (Altium Project File)
***Backplane.PcbDoc (Altium PCB File)
***Analog Connector.SchDoc, Digital Connector.SchDoc, LEMO.SchDoc (Altium Schematics)
***Backplane.pdf (SmartPDF File of the schematics and PCB layout)
**Amplifier Board
***Analog Board.PrjPcb (Altium Project File)
***Amplifier Board.PcbDoc (Altium PCB File)
***Main.SchDoc, Amplifier.SchDoc, Summer.SchDoc, Voltage References.SchDoc (Altium Schematics)
***Analog Board.pdf (SmartPDF File of the schematics and PCB layout
****The SmartPDF shows the entire PCB workspace, including components that have not yet been placed on the physical PCB.
****The bottom left corner of the PCB view shows a proof-of-concept 5 amplifiers/1 summer layout.
****Finding AMP6 using the PDF bookmarks shows the prototype amplifier layout that resolves mismatched footprint issues (indicated in green in the image farther up on this page).

== Summary of Fall 2009 Work ==

=== Mid-Semester Update, 11/12/2009 ===
We now have one fully working prototype of the SiPM Digital Control Board, and the SiPM Amplifier Board is currently being manufactured and assembled by Sierra Circuits, Inc. The backplane design is nearly complete and will be going out for quoting within a week.

Here is a zip file containing the most recent versions of the tagger files: [http://zeus.phys.uconn.edu/halld/tagger/electronics/design-11-2009/TaggerMicroscopeProgress20091112.zip Design Snapshot 11/12/2009]

A few notes about these files:
*There are four subfolders in the zip file. The folders for the three PCBs are clearly labelled. Each PCB folder has one project file (.PrjPcb) which can be opened in Altium Designer. Each project file refers to only one PcbDoc file, making it easy to figure out what you should look at to see the board.
*The SiPM digital control board project has 4 shelved polygons which should be restored (Tools->Polygon Pours->Restore 4 shelved polyons) to see the state of the board as it was last manufactured. Revisions from the testing process have not yet been entered into Altium but can be reviewed on this wiki: [[Digital control board debugging notes]]
*The SiPM amplifier (analog) board project will give an error message that it was unable to find "Test PCB.PcbDoc". Please ignore this. The file was intentionally omitted to prevent confusion, and is not related to the actual design.
*The backplane project will give an error message that it was unable to find "Backplane_New.PcbDoc". Please ignore this. The file was intentionally omitted to prevent confusion, and is not related to the actual design.

=== End of Semester Update ===
This semester, a lot of progress has been made on the tagger electronics. The digital control board is now onto revision 2.0, the amplifier board is in production, and the backplane is awaiting completion of the purchase order for production to begin. It is exciting to say that the bulk of the work is now finally complete. Remaining for the spring are the tasks of testing the amplifier board, and seeing that everything fits into the backplane. Here are some details about what I accomplished this semester, as well as links to the most recent project files.

==== Digital Control Board ====
The semester began with the digital control board prototypes sitting on lab bench waiting to be tested. My job was primarily to design the boards, not to debug them, though I still played an integral part in the testing process. We were all relieved that none of the boards appeared to smoke immediately when we first applied power, though there were a few confusing problems that had to be sorted out. Most of these problems are described in detail on the [[Digital control board debugging notes]] page. More or less, we had to solder a pin that wasn't connected, replace the crystal oscillator with a CMOS oscillator, and rewire few traces that were accidentally connected to pins intended for other signals. I won't repeat all of the changes we made here since it would be redundant to the page that already discusses it, but the important part is that we have one board that is fully operational, and the version 2.0 schematics/layout reflecting all these changes are complete. I anticipate that production of the version 2.0 boards will occur at the beginning of the spring 2010 semester.

There is still one lingering problem with the digital board design that has not yet been resolved, however. Even after all of the version 2.0 changes were implemented on the version 1.0 boards, only one of the three boards produced actually functioned properly. For a reason unknown to us, two of the boards ended up with their digital to analog converters burning up and smoking. We thoroughly reviewed the schematics and the layout, and found nothing miswired. Furthermore, we analyzed the placement of the ball grid array DAC to the best of our ability, and determined that a misalignment of balls is not the cause of the failure. All of our power supplies are stable, properly decoupled, and grounded as called for by DAC's manufacturer. Currently, the best hypothesis for the failure of 2 of the 3 DACs is that one or more of the absolute maximum ratings must have been exceeded at some point during the assembly process. Analog Devices lists fairly specific specs with small tolerances relating to maximum temperature and the length of time which the DAC may spend inside a reflow oven. We have run into some difficultly trying to find out from the boards' assembler whether they followed the published specs for the assembly process, but we intend to keep trying until the cause of the DAC failure has been resolved.

==== Amplifier Board ====
Throughout the summer and the beginning of the fall semester, I completed the design for the SiPM Amplifier Board, version 1.0. All 30 channels have been implemented along with their summing circuits. As I mentioned in the mid semester update above, this board is being manufactured and assembled by Sierra Circuits, Inc. Some unexpected setbacks occurred in the assembly process that delayed the boards somewhat, but I believe everything is now on track for delivery of the finished product before the start of the spring semester. A number of problems relating to minimum quantities of parts, as well as part naming conventions have now been resolved, and the assembly process should be complete in several weeks.

==== Backplane ====
The backplane design, version 1.0, has also been completed. Sierra Circuits will be manufacturing the backplane, which we will assemble ourselves. The backplane is a particularly interesting PCB from a manufacturing standpoint, because it is designed to be completely light proof. Since the backplane is the only material standing between the whole of Hall D and the inside of the tagger microscope dark box, opacity of the board is particularly important.

Most PCBs with internal copper layers are already fairly opaque, because the copper blocks light from transmitting through the FR-4 and prepreg. Through hole components do not particulary compromise board opacity, because the holes are plugged with component pins and solder. What does have a greater affect on the opaqueness of a board, however, is the thermal reliefs by which through hole pins and vias connect to internal plane layers. These reliefs are designed to aid in the soldering process by minimizing the amount of copper that is directly connected to the plating in the hole. A typical relief consists of four 7-10 mil traces connecting the hole's plating to the internal plane. The plane itself remains about 20 mil away from the hole, to prevent conduction of heat during the soldering process. Unfortunately, this means that there is a small gap in which there is only FR-4 to stop light from passing through the board. Since FR-4 is transparent, this poses a problem for our design. We were able work with Sierra Circuits to come up with a board design that includes an internal layer of special black FR-4 to prevent light leakage through the heat reliefs. While this is certainly not a standard feature, Sierra was confident that they could implement it for us, and we look forward to testing the boards' opacity in the spring.

Woody Underwood

2009-12-17T22:00:45Z

Underwood: /* Backplane */

== About Me ==
My name is Woody Underwood. I'm a junior entering my seventh semester in the physics program at UConn. Since the summer of 2008, I've been working in the lab of Dr. Richard Jones designing electronics for the US Department of Energy's GlueX experiment. My assignment is to develop three circuit boards that work together to tag photons coming from the diamond radiator. My circuitry essentially measures (indirectly) the energy of these photons in order to determine if they are of interest to GlueX. The three boards I am designing consist of a digital board, an analog board, and a connecting backplane.

== About My Circuitry ==
Electrons leaving the diamond radiator are deflected by a magnetic field into an array of scintillating fibres, producing photons. Wave guides carry these photons to SiPMs (silicon photomultipliers) mounted on the analog circuit board. The analog board contains transimpedance amplifiers and summing circuitry to condition the signals for digitization.

The sensitivity of the SiPMs and the gain of the amplifiers on the analog board are controlled both by the power supply VCC and bias voltages supplied from the digital board. The digital board receives commands from a computer via ethernet, and uses a 32-channel DAC to output appropriate bias voltages to the SiPMs on the analog board. The digital and analog boards are connected by means of a backplane, which is also responsible for providing power and grounds to both boards.

== Summary of Fall 2008 Work ==
All circuitry design work was done using Altium Designer. The digital board was the first to be designed. The first step in designing the digital board was to review the list of key components that had already been selected by Igor and Dr. Jones. These components included such things as the Xilinx Spartan-3A FPGA, and the Analog Devices AD5535 DAC. I began by looking through datasheets for these components to find out their needs, including power and decoupling requirements. I reviewed the pinout diagrams, and then looked through Altium’s standard libraries to find components that matched (in many cases the particular component I was looking for was not in the library, but a similar footprint or schematic symbol was). For components without matching schematic symbols, I entered pinout information from the datasheets into Microsoft Excel, using a layout compatible with Altium’s Smart Grid Insert function. Then, I was able to literally copy and paste pin information from Excel into Altium to generate the schematic symbols I needed.

Once I had appropriate schematic symbols available for all parts, I began making appropriate connections in the schematic view in Altium. Though tedious, this task was not exceedingly difficult. I finished the schematics in several days, and then moved on to PCB design. I switched into Altium's PCB view. The footprints corresponding to the components I used in the schematics were automatically inserted by Altium. My job was then to position these components in logical places on the board and make all of the connections corresponding to the nets defined in the schematics.

Due to the large number of components being placed in the limited space available on the digital board, Altium's auto-router proved completely useless. Therefore, I routed the board manually. Despite Altium's revolutionary convergence of schematic and PCB design into a single program, this was no easy task. During the routing process, I had to take into account not only the connections that had to be made, but also things such as avoiding crosstalk and minimizing trace length for sensitive components. I was able to complete routing after several weeks of work. The digital board design has since been completed and the board has been printed. It is currently awaiting assembly.

The analog board provided a host of new challenges. The basic schematic for the transimpedance amplifier on the analog board was completed by Igor and Dr. Jones before the semester. Inputting the schematic into Altium was not very difficult. However, one problem I encountered was that the analog board contains 32 copies of this amplifier circuitry. After failing to find any way to insert multiple copies of both the schematic and its corresponding PCB layout, I decided to insert only single copies of each schematic page, and copy and paste the PCB layout to produce 32 copies of the amplifier circuitry. At first this seemed like a quick and easy way to get all of the necessary circuitry onto the PCB. However, I eventually discovered that this procedure would lead to major problems with the board assembly process (due to duplicate component designators, and for other reasons). Fortunately, this revelation came around the same time that Igor and Dr. Jones found a problem with the performance of the amplifier circuit. Making any changes to the amplifier circuit at this point will require a major reroute of all the traces on the analog board. Since the board needs to be completely redesigned anyway, this will give me another chance to find a way to match schematics with all 32 copies of the amplifier circuitry.

The backplane design is currently in progress. It should be relatively easy to complete. All that remains to be done is to add the LEMO connectors and power inputs. The board is simple enough that it can be routed completely by the auto-router, though a quick hand routing will probably be superior. I anticipate that I can complete the backplane with a few days of concentrated work over break.

Included below are links to the files I have been working on. Included in the files for each board is a "SmartPDF," viewable in Adobe Reader. For those without Altium Designer, these may be the best files to look at. They include complete schematics and PCB layout, and are also indexed by component.

Any questions about the tagger circuitry can be directed to me at [mailto:mitchell.underwood@uconn.edu mitchell.underwood@uconn.edu]

=== Related Files ===
* [http://zeus.phys.uconn.edu/halld/tagger/electronics/design-12-2008/DigitalBoard.zip DigitalBoard.zip]:
**Altium Project File (SiPM Control Board.PrjPcb)
**Altium PCB Layout File (Prototype1.PcbDoc)
**Altium Schematic Files (*.SchDoc)
**Altium Annotation Document (SiPM Control Board.Annotation)
***Not used, but generated by Altium when opening the project
**Altium PRJPCBSTRUCTURE File (SiPM Control Board.PRJPCBSTRUCTURE)
***Not used, but generated by Altium when opening the project)
**“SmartPDF” of the board and schematics (SiPM Control Board.pdf)
***Can be used to explore the PCB layout and schematics without needing Altium
**Pick and Place File for board population (Pick Place for Prototype1.txt)
***Used by board assembler
**NC Drill Files (Prototype1.txt, Prototype1.DRR, Prototype1.DRL)
***Used by board printer
**Gerber Files for all layers (in folder Gerbers)
***Used by board printer
**Altium CAMtastic file (CAMtastic4 FINAL.Cam)
***Basically a composite of all the Gerbers
**Photos and 3D rendering of populated board
***In folder “Photos”
**EMF Files showing different layers
***In folder “EMF Renderings”
**AutoCad File of PCB (Prototype1 Autocad.DWG)
**Altium Library of Custom Footprints for Digital Board (GlueX IC Library.SchLib)
***Current as of completion of digital board
***This library has since been updated for the backplane

*[http://zeus.phys.uconn.edu/halld/tagger/electronics/design-12-2008/Analog%20Board%2020081211.zip Analog Board 20081211.zip]:
**Altium Project File (AnalogBoard.PrjPcb)
**Altium PCB Layout File (AnalogBoardPCB.PcbDoc)
**Altium Schematic Files (Amplifer1.SchDoc, Summer.SchDoc)
**“SmartPDF” of the board and schematics (AnalogBoard.pdf)
**Altium Component Definition for SiPM (SiPM Library.PcbLib)
***Contains part footprint and pin information for the SiPM component

*[http://zeus.phys.uconn.edu/halld/tagger/electronics/design-12-2008/Backplane%2020081211.zip Backplane 20081211.zip]
**Altium Project File (Backplane.PrjPcb)
**Alitum PCB Layout File (Backplane.PcbDoc)
**Altium Schematic Files (Analog Connector.SchDoc, Digital Connector.SchDoc)
***Analog Connector = Eurocard to analog board
***Digital Connector = Eurocard to digital board, +3.3V voltage regulator, and location identifier jumper
***LEMO connections not yet included in these schematics
**“SmartPDF” of the board and schematics (Backplane.pdf)
**Pin layout files used to define pinouts for custom components (Pin Layout, 96 pin connector.xlsx, Pinouts.xlsx)
***Pin Layout, 96 pin connector = pinout definition for 96 pin Eurocard connector
***Pinouts.xlsx = pinout definitions for digital board, which were reused for the 48 pin digital Eurocard receptacle on backplane
**Altium Library of Custom Components (GlueX IC Library.SchLib)
***UPDATED to include new backplane components
***An older version of this library was used for the digital board

==Summary of Spring 2009 Work==

At the end of the fall semester, Dr. Jones, Igor, and I determined that the amplifier/summing circuit we had designed simply didn’t have sufficient performance characteristics to be useful for GlueX. During the beginning of the spring semester, Igor came up with a new design, utilizing more transistors, to provide the high gain, fast response, picosecond resolution amplifier that we needed. The design performed flawlessly both in MatLab simulations and in a handmade single channel prototype. The first of my goals for the spring 2009 semester was to capture the schematic for this new amplifier into Altium designer, and layout a new amplifier board. The second of my goals, of course, was to complete production of the digital control board prototypes.

[[Image:Digital Board, Populated.JPG|thumb|The populated digital board, with a tube of Chap-BlockTM for size comparison.]] Since the fall semester left us with three unpopulated digital control board PCBs, getting those PCBs assembled with their components was the first priority. I began the semester by tracking down all of the components we needed (some of which were selected at the end of the fall semester), and making appropriate substitutions for components whose availability had changed since the fall. In the process of selecting these components, I noticed several places where it seemed like power consumption on the board may be somewhat high. To fix this, I developed a spreadsheet in Microsoft Excel that calculates optimal resistor values to use for to obtain a specified voltage divider stiffness. With this tool, I was able to optimize power consumption across the board, and select appropriate components. Once all components had been selected, ordered, and received, we sent the order out to Screamin’ Circuits for assembly. The boards came back several weeks later, and are currently awaiting testing by some undergraduates who will be in the lab this summer.

While Igor was finalizing his amplifier/summing circuit, I worked briefly on design of the backplane. A number of details regarding trace impedance and board dimensions were ironed out. Nonetheless, many problems still remain which I will need to tackle over the summer. The first of these problems is that we have yet to find an appropriate low cost coaxial connector to route signals off the backplane. In addition, screws with which to mount the backplane to the tagger must be selected so that appropriate holes can be created for them on the PCB.

Once we were satisfied that the amplifier/summing circuit performed as required, I shifted work from the backplane to the amplifier board. Around the same time, I began working on a poster to present my work at the Frontiers in Undergraduate Research Exhibition held during Open House Weekend here at UConn. If you’re interested in my poster, check it out here.

[[Image:Amplifier-Summer-Laid-out.gif|thumb|A prototype layout of 5 amplifier channels and a summing circuit. Actual size is ~1.6" tall. Areas in green represent problems to be resolved over summer 2009. A prototype amplifier with no green spots has been designed and will be replicated to this design soon.]] To start the amplifier/summing circuit project, I searched high and low for information about how to handle multi-channel designs in Altium. Not surprisingly, the first Google result on the query “multichannel design Altium” had everything I was missing during the fall when I was trying to lay out the original amplifier circuit. Using my new knowledge of Altium’s multichannel capabilities, I captured Igor’s new design into the schematics editor of Altium Designer. With proper nested schematic sheets, the entire 30 channel amplifier/6 channel summer design was compressed into just 4 schematic sheets, vs. the ~40 or so that would have been required had I laid out the complete schematics of the old design.

I spent about a week and a half trying to figure out how to handle nesting independent nets from a repeated subsheet into another repeated subsheet which also produces independent nets from the nets of the first sheet. This sounds somewhat complicated, and I suppose perhaps it is a somewhat unique situation, since none of the ~5 sample multichannel projects included with Altium had such a construction in them. Basically, each summing circuit has five amplifier subcircuits, each of which puts out its own signal independent of the other four. From the perspective of the entire board, there are 6 summers, each of which has five independent signals coming from the amplifiers, and one summed signal. Determining how to get Altium to realize the proper connections from each individual amplifier, through that amplifier’s summer, to the main schematic was a complicated mess of naming conventions, but eventually I was able to make Altium reflect all of the appropriate connections in the PCB view. Though there are a few net naming issues still to be resolved, this problem has mostly been ironed out.

The final few weeks of the semester were spent laying out amplifier components in the PCB view of Altium. As of right now, a compact design for an amplifier measuring 0.183”x~1.3” has been completed. Making use of 0201 size components, this amplifier is approximately .2” shorter than the old design, despite incorporating an extra transistor. The amplifier design features an isolating ground trace running the length of the amplifier to prevent crosstalk between channels. A prototype layout of the summing circuit has also been completed, though some layout issues there remain to be resolved over the summer.

===Related Files===
*[http://zeus.phys.uconn.edu/halld/tagger/electronics/design-6-2009/Progress20090505.zip Design Snapshot 5/5/2009]
**Backplane
***Backplane.PrjPcb (Altium Project File)
***Backplane.PcbDoc (Altium PCB File)
***Analog Connector.SchDoc, Digital Connector.SchDoc, LEMO.SchDoc (Altium Schematics)
***Backplane.pdf (SmartPDF File of the schematics and PCB layout)
**Amplifier Board
***Analog Board.PrjPcb (Altium Project File)
***Amplifier Board.PcbDoc (Altium PCB File)
***Main.SchDoc, Amplifier.SchDoc, Summer.SchDoc, Voltage References.SchDoc (Altium Schematics)
***Analog Board.pdf (SmartPDF File of the schematics and PCB layout
****The SmartPDF shows the entire PCB workspace, including components that have not yet been placed on the physical PCB.
****The bottom left corner of the PCB view shows a proof-of-concept 5 amplifiers/1 summer layout.
****Finding AMP6 using the PDF bookmarks shows the prototype amplifier layout that resolves mismatched footprint issues (indicated in green in the image farther up on this page).

== Fall 2009 Work ==

=== Mid-Semester Update, 11/12/2009 ===
We now have one fully working prototype of the SiPM Digital Control Board, and the SiPM Amplifier Board is currently being manufactured and assembled by Sierra Circuits, Inc. The backplane design is nearly complete and will be going out for quoting within a week.

Here is a zip file containing the most recent versions of the tagger files: [http://zeus.phys.uconn.edu/halld/tagger/electronics/design-11-2009/TaggerMicroscopeProgress20091112.zip Design Snapshot 11/12/2009]

A few notes about these files:
*There are four subfolders in the zip file. The folders for the three PCBs are clearly labelled. Each PCB folder has one project file (.PrjPcb) which can be opened in Altium Designer. Each project file refers to only one PcbDoc file, making it easy to figure out what you should look at to see the board.
*The SiPM digital control board project has 4 shelved polygons which should be restored (Tools->Polygon Pours->Restore 4 shelved polyons) to see the state of the board as it was last manufactured. Revisions from the testing process have not yet been entered into Altium but can be reviewed on this wiki: [[Digital control board debugging notes]]
*The SiPM amplifier (analog) board project will give an error message that it was unable to find "Test PCB.PcbDoc". Please ignore this. The file was intentionally omitted to prevent confusion, and is not related to the actual design.
*The backplane project will give an error message that it was unable to find "Backplane_New.PcbDoc". Please ignore this. The file was intentionally omitted to prevent confusion, and is not related to the actual design.

=== End of Semester Update ===
This semester, a lot of progress has been made on the tagger electronics. The digital control board is now onto revision 2.0, the amplifier board is in production, and the backplane is awaiting completion of the purchase order for production to begin. It is exciting to say that the bulk of the work is now finally complete. Remaining for the spring are the tasks of testing the amplifier board, and seeing that everything fits into the backplane. Here are some details about what I accomplished this semester, as well as links to the most recent project files.

==== Digital Control Board ====
The semester began with the digital control board prototypes sitting on lab bench waiting to be tested. My job was primarily to design the boards, not to debug them, though I still played an integral part in the testing process. We were all relieved that none of the boards appeared to smoke immediately when we first applied power, though there were a few confusing problems that had to be sorted out. Most of these problems are described in detail on the [[Digital control board debugging notes]] page. More or less, we had to solder a pin that wasn't connected, replace the crystal oscillator with a CMOS oscillator, and rewire few traces that were accidentally connected to pins intended for other signals. I won't repeat all of the changes we made here since it would be redundant to the page that already discusses it, but the important part is that we have one board that is fully operational, and the version 2.0 schematics/layout reflecting all these changes are complete. I anticipate that production of the version 2.0 boards will occur at the beginning of the spring 2010 semester.

There is still one lingering problem with the digital board design that has not yet been resolved, however. Even after all of the version 2.0 changes were implemented on the version 1.0 boards, only one of the three boards produced actually functioned properly. For a reason unknown to us, two of the boards ended up with their digital to analog converters burning up and smoking. We thoroughly reviewed the schematics and the layout, and found nothing miswired. Furthermore, we analyzed the placement of the ball grid array DAC to the best of our ability, and determined that a misalignment of balls is not the cause of the failure. All of our power supplies are stable, properly decoupled, and grounded as called for by DAC's manufacturer. Currently, the best hypothesis for the failure of 2 of the 3 DACs is that one or more of the absolute maximum ratings must have been exceeded at some point during the assembly process. Analog Devices lists fairly specific specs with small tolerances relating to maximum temperature and the length of time which the DAC may spend inside a reflow oven. We have run into some difficultly trying to find out from the boards' assembler whether they followed the published specs for the assembly process, but we intend to keep trying until the cause of the DAC failure has been resolved.

==== Amplifier Board ====
Throughout the summer and the beginning of the fall semester, I completed the design for the SiPM Amplifier Board, version 1.0. All 30 channels have been implemented along with their summing circuits. As I mentioned in the mid semester update above, this board is being manufactured and assembled by Sierra Circuits, Inc. Some unexpected setbacks occurred in the assembly process that delayed the boards somewhat, but I believe everything is now on track for delivery of the finished product before the start of the spring semester. A number of problems relating to minimum quantities of parts, as well as part naming conventions have now been resolved, and the assembly process should be complete in several weeks.

==== Backplane ====
The backplane design, version 1.0, has also been completed. Sierra Circuits will be manufacturing the backplane, which we will assemble ourselves. The backplane is a particularly interesting PCB from a manufacturing standpoint, because it is designed to be completely light proof. Since the backplane is the only material standing between the whole of Hall D and the inside of the tagger microscope dark box, opacity of the board is particularly important.

Most PCBs with internal copper layers are already fairly opaque, because the copper blocks light from transmitting through the FR-4 and prepreg. Through hole components do not particulary compromise board opacity, because the holes are plugged with component pins and solder. What does have a greater affect on the opaqueness of a board, however, is the thermal reliefs by which through hole pins and vias connect to internal plane layers. These reliefs are designed to aid in the soldering process by minimizing the amount of copper that is directly connected to the plating in the hole. A typical relief consists of four 7-10 mil traces connecting the hole's plating to the internal plane. The plane itself remains about 20 mil away from the hole, to prevent conduction of heat during the soldering process. Unfortunately, this means that there is a small gap in which there is only FR-4 to stop light from passing through the board. Since FR-4 is transparent, this poses a problem for our design. We were able work with Sierra Circuits to come up with a board design that includes an internal layer of special black FR-4 to prevent light leakage through the heat reliefs. While this is certainly not a standard feature, Sierra was confident that they could implement it for us, and we look forward to testing the boards' opacity in the spring.

Woody Underwood

2009-12-17T21:58:58Z

Underwood: /* Digital Control Board */ wording

== About Me ==
My name is Woody Underwood. I'm a junior entering my seventh semester in the physics program at UConn. Since the summer of 2008, I've been working in the lab of Dr. Richard Jones designing electronics for the US Department of Energy's GlueX experiment. My assignment is to develop three circuit boards that work together to tag photons coming from the diamond radiator. My circuitry essentially measures (indirectly) the energy of these photons in order to determine if they are of interest to GlueX. The three boards I am designing consist of a digital board, an analog board, and a connecting backplane.

== About My Circuitry ==
Electrons leaving the diamond radiator are deflected by a magnetic field into an array of scintillating fibres, producing photons. Wave guides carry these photons to SiPMs (silicon photomultipliers) mounted on the analog circuit board. The analog board contains transimpedance amplifiers and summing circuitry to condition the signals for digitization.

The sensitivity of the SiPMs and the gain of the amplifiers on the analog board are controlled both by the power supply VCC and bias voltages supplied from the digital board. The digital board receives commands from a computer via ethernet, and uses a 32-channel DAC to output appropriate bias voltages to the SiPMs on the analog board. The digital and analog boards are connected by means of a backplane, which is also responsible for providing power and grounds to both boards.

== Summary of Fall 2008 Work ==
All circuitry design work was done using Altium Designer. The digital board was the first to be designed. The first step in designing the digital board was to review the list of key components that had already been selected by Igor and Dr. Jones. These components included such things as the Xilinx Spartan-3A FPGA, and the Analog Devices AD5535 DAC. I began by looking through datasheets for these components to find out their needs, including power and decoupling requirements. I reviewed the pinout diagrams, and then looked through Altium’s standard libraries to find components that matched (in many cases the particular component I was looking for was not in the library, but a similar footprint or schematic symbol was). For components without matching schematic symbols, I entered pinout information from the datasheets into Microsoft Excel, using a layout compatible with Altium’s Smart Grid Insert function. Then, I was able to literally copy and paste pin information from Excel into Altium to generate the schematic symbols I needed.

Once I had appropriate schematic symbols available for all parts, I began making appropriate connections in the schematic view in Altium. Though tedious, this task was not exceedingly difficult. I finished the schematics in several days, and then moved on to PCB design. I switched into Altium's PCB view. The footprints corresponding to the components I used in the schematics were automatically inserted by Altium. My job was then to position these components in logical places on the board and make all of the connections corresponding to the nets defined in the schematics.

Due to the large number of components being placed in the limited space available on the digital board, Altium's auto-router proved completely useless. Therefore, I routed the board manually. Despite Altium's revolutionary convergence of schematic and PCB design into a single program, this was no easy task. During the routing process, I had to take into account not only the connections that had to be made, but also things such as avoiding crosstalk and minimizing trace length for sensitive components. I was able to complete routing after several weeks of work. The digital board design has since been completed and the board has been printed. It is currently awaiting assembly.

The analog board provided a host of new challenges. The basic schematic for the transimpedance amplifier on the analog board was completed by Igor and Dr. Jones before the semester. Inputting the schematic into Altium was not very difficult. However, one problem I encountered was that the analog board contains 32 copies of this amplifier circuitry. After failing to find any way to insert multiple copies of both the schematic and its corresponding PCB layout, I decided to insert only single copies of each schematic page, and copy and paste the PCB layout to produce 32 copies of the amplifier circuitry. At first this seemed like a quick and easy way to get all of the necessary circuitry onto the PCB. However, I eventually discovered that this procedure would lead to major problems with the board assembly process (due to duplicate component designators, and for other reasons). Fortunately, this revelation came around the same time that Igor and Dr. Jones found a problem with the performance of the amplifier circuit. Making any changes to the amplifier circuit at this point will require a major reroute of all the traces on the analog board. Since the board needs to be completely redesigned anyway, this will give me another chance to find a way to match schematics with all 32 copies of the amplifier circuitry.

The backplane design is currently in progress. It should be relatively easy to complete. All that remains to be done is to add the LEMO connectors and power inputs. The board is simple enough that it can be routed completely by the auto-router, though a quick hand routing will probably be superior. I anticipate that I can complete the backplane with a few days of concentrated work over break.

Included below are links to the files I have been working on. Included in the files for each board is a "SmartPDF," viewable in Adobe Reader. For those without Altium Designer, these may be the best files to look at. They include complete schematics and PCB layout, and are also indexed by component.

Any questions about the tagger circuitry can be directed to me at [mailto:mitchell.underwood@uconn.edu mitchell.underwood@uconn.edu]

=== Related Files ===
* [http://zeus.phys.uconn.edu/halld/tagger/electronics/design-12-2008/DigitalBoard.zip DigitalBoard.zip]:
**Altium Project File (SiPM Control Board.PrjPcb)
**Altium PCB Layout File (Prototype1.PcbDoc)
**Altium Schematic Files (*.SchDoc)
**Altium Annotation Document (SiPM Control Board.Annotation)
***Not used, but generated by Altium when opening the project
**Altium PRJPCBSTRUCTURE File (SiPM Control Board.PRJPCBSTRUCTURE)
***Not used, but generated by Altium when opening the project)
**“SmartPDF” of the board and schematics (SiPM Control Board.pdf)
***Can be used to explore the PCB layout and schematics without needing Altium
**Pick and Place File for board population (Pick Place for Prototype1.txt)
***Used by board assembler
**NC Drill Files (Prototype1.txt, Prototype1.DRR, Prototype1.DRL)
***Used by board printer
**Gerber Files for all layers (in folder Gerbers)
***Used by board printer
**Altium CAMtastic file (CAMtastic4 FINAL.Cam)
***Basically a composite of all the Gerbers
**Photos and 3D rendering of populated board
***In folder “Photos”
**EMF Files showing different layers
***In folder “EMF Renderings”
**AutoCad File of PCB (Prototype1 Autocad.DWG)
**Altium Library of Custom Footprints for Digital Board (GlueX IC Library.SchLib)
***Current as of completion of digital board
***This library has since been updated for the backplane

*[http://zeus.phys.uconn.edu/halld/tagger/electronics/design-12-2008/Analog%20Board%2020081211.zip Analog Board 20081211.zip]:
**Altium Project File (AnalogBoard.PrjPcb)
**Altium PCB Layout File (AnalogBoardPCB.PcbDoc)
**Altium Schematic Files (Amplifer1.SchDoc, Summer.SchDoc)
**“SmartPDF” of the board and schematics (AnalogBoard.pdf)
**Altium Component Definition for SiPM (SiPM Library.PcbLib)
***Contains part footprint and pin information for the SiPM component

*[http://zeus.phys.uconn.edu/halld/tagger/electronics/design-12-2008/Backplane%2020081211.zip Backplane 20081211.zip]
**Altium Project File (Backplane.PrjPcb)
**Alitum PCB Layout File (Backplane.PcbDoc)
**Altium Schematic Files (Analog Connector.SchDoc, Digital Connector.SchDoc)
***Analog Connector = Eurocard to analog board
***Digital Connector = Eurocard to digital board, +3.3V voltage regulator, and location identifier jumper
***LEMO connections not yet included in these schematics
**“SmartPDF” of the board and schematics (Backplane.pdf)
**Pin layout files used to define pinouts for custom components (Pin Layout, 96 pin connector.xlsx, Pinouts.xlsx)
***Pin Layout, 96 pin connector = pinout definition for 96 pin Eurocard connector
***Pinouts.xlsx = pinout definitions for digital board, which were reused for the 48 pin digital Eurocard receptacle on backplane
**Altium Library of Custom Components (GlueX IC Library.SchLib)
***UPDATED to include new backplane components
***An older version of this library was used for the digital board

==Summary of Spring 2009 Work==

At the end of the fall semester, Dr. Jones, Igor, and I determined that the amplifier/summing circuit we had designed simply didn’t have sufficient performance characteristics to be useful for GlueX. During the beginning of the spring semester, Igor came up with a new design, utilizing more transistors, to provide the high gain, fast response, picosecond resolution amplifier that we needed. The design performed flawlessly both in MatLab simulations and in a handmade single channel prototype. The first of my goals for the spring 2009 semester was to capture the schematic for this new amplifier into Altium designer, and layout a new amplifier board. The second of my goals, of course, was to complete production of the digital control board prototypes.

[[Image:Digital Board, Populated.JPG|thumb|The populated digital board, with a tube of Chap-BlockTM for size comparison.]] Since the fall semester left us with three unpopulated digital control board PCBs, getting those PCBs assembled with their components was the first priority. I began the semester by tracking down all of the components we needed (some of which were selected at the end of the fall semester), and making appropriate substitutions for components whose availability had changed since the fall. In the process of selecting these components, I noticed several places where it seemed like power consumption on the board may be somewhat high. To fix this, I developed a spreadsheet in Microsoft Excel that calculates optimal resistor values to use for to obtain a specified voltage divider stiffness. With this tool, I was able to optimize power consumption across the board, and select appropriate components. Once all components had been selected, ordered, and received, we sent the order out to Screamin’ Circuits for assembly. The boards came back several weeks later, and are currently awaiting testing by some undergraduates who will be in the lab this summer.

While Igor was finalizing his amplifier/summing circuit, I worked briefly on design of the backplane. A number of details regarding trace impedance and board dimensions were ironed out. Nonetheless, many problems still remain which I will need to tackle over the summer. The first of these problems is that we have yet to find an appropriate low cost coaxial connector to route signals off the backplane. In addition, screws with which to mount the backplane to the tagger must be selected so that appropriate holes can be created for them on the PCB.

Once we were satisfied that the amplifier/summing circuit performed as required, I shifted work from the backplane to the amplifier board. Around the same time, I began working on a poster to present my work at the Frontiers in Undergraduate Research Exhibition held during Open House Weekend here at UConn. If you’re interested in my poster, check it out here.

[[Image:Amplifier-Summer-Laid-out.gif|thumb|A prototype layout of 5 amplifier channels and a summing circuit. Actual size is ~1.6" tall. Areas in green represent problems to be resolved over summer 2009. A prototype amplifier with no green spots has been designed and will be replicated to this design soon.]] To start the amplifier/summing circuit project, I searched high and low for information about how to handle multi-channel designs in Altium. Not surprisingly, the first Google result on the query “multichannel design Altium” had everything I was missing during the fall when I was trying to lay out the original amplifier circuit. Using my new knowledge of Altium’s multichannel capabilities, I captured Igor’s new design into the schematics editor of Altium Designer. With proper nested schematic sheets, the entire 30 channel amplifier/6 channel summer design was compressed into just 4 schematic sheets, vs. the ~40 or so that would have been required had I laid out the complete schematics of the old design.

I spent about a week and a half trying to figure out how to handle nesting independent nets from a repeated subsheet into another repeated subsheet which also produces independent nets from the nets of the first sheet. This sounds somewhat complicated, and I suppose perhaps it is a somewhat unique situation, since none of the ~5 sample multichannel projects included with Altium had such a construction in them. Basically, each summing circuit has five amplifier subcircuits, each of which puts out its own signal independent of the other four. From the perspective of the entire board, there are 6 summers, each of which has five independent signals coming from the amplifiers, and one summed signal. Determining how to get Altium to realize the proper connections from each individual amplifier, through that amplifier’s summer, to the main schematic was a complicated mess of naming conventions, but eventually I was able to make Altium reflect all of the appropriate connections in the PCB view. Though there are a few net naming issues still to be resolved, this problem has mostly been ironed out.

The final few weeks of the semester were spent laying out amplifier components in the PCB view of Altium. As of right now, a compact design for an amplifier measuring 0.183”x~1.3” has been completed. Making use of 0201 size components, this amplifier is approximately .2” shorter than the old design, despite incorporating an extra transistor. The amplifier design features an isolating ground trace running the length of the amplifier to prevent crosstalk between channels. A prototype layout of the summing circuit has also been completed, though some layout issues there remain to be resolved over the summer.

===Related Files===
*[http://zeus.phys.uconn.edu/halld/tagger/electronics/design-6-2009/Progress20090505.zip Design Snapshot 5/5/2009]
**Backplane
***Backplane.PrjPcb (Altium Project File)
***Backplane.PcbDoc (Altium PCB File)
***Analog Connector.SchDoc, Digital Connector.SchDoc, LEMO.SchDoc (Altium Schematics)
***Backplane.pdf (SmartPDF File of the schematics and PCB layout)
**Amplifier Board
***Analog Board.PrjPcb (Altium Project File)
***Amplifier Board.PcbDoc (Altium PCB File)
***Main.SchDoc, Amplifier.SchDoc, Summer.SchDoc, Voltage References.SchDoc (Altium Schematics)
***Analog Board.pdf (SmartPDF File of the schematics and PCB layout
****The SmartPDF shows the entire PCB workspace, including components that have not yet been placed on the physical PCB.
****The bottom left corner of the PCB view shows a proof-of-concept 5 amplifiers/1 summer layout.
****Finding AMP6 using the PDF bookmarks shows the prototype amplifier layout that resolves mismatched footprint issues (indicated in green in the image farther up on this page).

== Fall 2009 Work ==

=== Mid-Semester Update, 11/12/2009 ===
We now have one fully working prototype of the SiPM Digital Control Board, and the SiPM Amplifier Board is currently being manufactured and assembled by Sierra Circuits, Inc. The backplane design is nearly complete and will be going out for quoting within a week.

Here is a zip file containing the most recent versions of the tagger files: [http://zeus.phys.uconn.edu/halld/tagger/electronics/design-11-2009/TaggerMicroscopeProgress20091112.zip Design Snapshot 11/12/2009]

A few notes about these files:
*There are four subfolders in the zip file. The folders for the three PCBs are clearly labelled. Each PCB folder has one project file (.PrjPcb) which can be opened in Altium Designer. Each project file refers to only one PcbDoc file, making it easy to figure out what you should look at to see the board.
*The SiPM digital control board project has 4 shelved polygons which should be restored (Tools->Polygon Pours->Restore 4 shelved polyons) to see the state of the board as it was last manufactured. Revisions from the testing process have not yet been entered into Altium but can be reviewed on this wiki: [[Digital control board debugging notes]]
*The SiPM amplifier (analog) board project will give an error message that it was unable to find "Test PCB.PcbDoc". Please ignore this. The file was intentionally omitted to prevent confusion, and is not related to the actual design.
*The backplane project will give an error message that it was unable to find "Backplane_New.PcbDoc". Please ignore this. The file was intentionally omitted to prevent confusion, and is not related to the actual design.

=== End of Semester Update ===
This semester, a lot of progress has been made on the tagger electronics. The digital control board is now onto revision 2.0, the amplifier board is in production, and the backplane is awaiting completion of the purchase order for production to begin. It is exciting to say that the bulk of the work is now finally complete. Remaining for the spring are the tasks of testing the amplifier board, and seeing that everything fits into the backplane. Here are some details about what I accomplished this semester, as well as links to the most recent project files.

==== Digital Control Board ====
The semester began with the digital control board prototypes sitting on lab bench waiting to be tested. My job was primarily to design the boards, not to debug them, though I still played an integral part in the testing process. We were all relieved that none of the boards appeared to smoke immediately when we first applied power, though there were a few confusing problems that had to be sorted out. Most of these problems are described in detail on the [[Digital control board debugging notes]] page. More or less, we had to solder a pin that wasn't connected, replace the crystal oscillator with a CMOS oscillator, and rewire few traces that were accidentally connected to pins intended for other signals. I won't repeat all of the changes we made here since it would be redundant to the page that already discusses it, but the important part is that we have one board that is fully operational, and the version 2.0 schematics/layout reflecting all these changes are complete. I anticipate that production of the version 2.0 boards will occur at the beginning of the spring 2010 semester.

There is still one lingering problem with the digital board design that has not yet been resolved, however. Even after all of the version 2.0 changes were implemented on the version 1.0 boards, only one of the three boards produced actually functioned properly. For a reason unknown to us, two of the boards ended up with their digital to analog converters burning up and smoking. We thoroughly reviewed the schematics and the layout, and found nothing miswired. Furthermore, we analyzed the placement of the ball grid array DAC to the best of our ability, and determined that a misalignment of balls is not the cause of the failure. All of our power supplies are stable, properly decoupled, and grounded as called for by DAC's manufacturer. Currently, the best hypothesis for the failure of 2 of the 3 DACs is that one or more of the absolute maximum ratings must have been exceeded at some point during the assembly process. Analog Devices lists fairly specific specs with small tolerances relating to maximum temperature and the length of time which the DAC may spend inside a reflow oven. We have run into some difficultly trying to find out from the boards' assembler whether they followed the published specs for the assembly process, but we intend to keep trying until the cause of the DAC failure has been resolved.

==== Amplifier Board ====
Throughout the summer and the beginning of the fall semester, I completed the design for the SiPM Amplifier Board, version 1.0. All 30 channels have been implemented along with their summing circuits. As I mentioned in the mid semester update above, this board is being manufactured and assembled by Sierra Circuits, Inc. Some unexpected setbacks occurred in the assembly process that delayed the boards somewhat, but I believe everything is now on track for delivery of the finished product before the start of the spring semester. A number of problems relating to minimum quantities of parts, as well as part naming conventions have now been resolved, and the assembly process should be complete in several weeks.

==== Backplane ====
The backplane design, version 1.0, has also been completed. Sierra Circuits will be manufacturing the backplane, which we will assemble ourselves. The backplane is a particularly intersting PCB from a manufacturing standpoint, because it is designed to be completely light proof. Since the backplane is the only material standing between the whole of Hall D and the inside of the tagger microscope dark box, opacity of the board is particularly important.

Most PCBs with internal copper layers are already fairly opaque, because the copper blocks light from transmitting through the FR-4 and prepreg. Through hole components do not particulary compromise board opacity, because they are plugged with component pins and solder. What does have a greater affect on the opaqueness of a board, however, is the thermal reliefs by which through hole pins and vias connect to internal plane layers. These reliefs are designed to aid in the soldering process by minimizing the amount of copper that is directly connected to the plating in the hole. A typical relief consists of four 7-10 mil traces connecting the hole's plating to the internal plane. The plane itself remains about 20 mil away from the hole, to prevent conduction of heat during the soldering process. Unfortunately, this means that there is a small gap in which there is only FR-4 to stop light from passing through the board. Since FR-4 is transparent, this poses a problem for our design. We were able work with Sierra Circuits to come up with a board design that includes an internal layer of special black FR-4 to prevent light leakage through the heat reliefs. While this is certainly not a standard feature, Sierra was confident that they could implement it for us, and we look forward to testing the boards' opacity in the spring.

Woody Underwood

2009-12-17T21:55:53Z

Underwood: /* Digital Control Board */ formatting error

== About Me ==
My name is Woody Underwood. I'm a junior entering my seventh semester in the physics program at UConn. Since the summer of 2008, I've been working in the lab of Dr. Richard Jones designing electronics for the US Department of Energy's GlueX experiment. My assignment is to develop three circuit boards that work together to tag photons coming from the diamond radiator. My circuitry essentially measures (indirectly) the energy of these photons in order to determine if they are of interest to GlueX. The three boards I am designing consist of a digital board, an analog board, and a connecting backplane.

== About My Circuitry ==
Electrons leaving the diamond radiator are deflected by a magnetic field into an array of scintillating fibres, producing photons. Wave guides carry these photons to SiPMs (silicon photomultipliers) mounted on the analog circuit board. The analog board contains transimpedance amplifiers and summing circuitry to condition the signals for digitization.

The sensitivity of the SiPMs and the gain of the amplifiers on the analog board are controlled both by the power supply VCC and bias voltages supplied from the digital board. The digital board receives commands from a computer via ethernet, and uses a 32-channel DAC to output appropriate bias voltages to the SiPMs on the analog board. The digital and analog boards are connected by means of a backplane, which is also responsible for providing power and grounds to both boards.

== Summary of Fall 2008 Work ==
All circuitry design work was done using Altium Designer. The digital board was the first to be designed. The first step in designing the digital board was to review the list of key components that had already been selected by Igor and Dr. Jones. These components included such things as the Xilinx Spartan-3A FPGA, and the Analog Devices AD5535 DAC. I began by looking through datasheets for these components to find out their needs, including power and decoupling requirements. I reviewed the pinout diagrams, and then looked through Altium’s standard libraries to find components that matched (in many cases the particular component I was looking for was not in the library, but a similar footprint or schematic symbol was). For components without matching schematic symbols, I entered pinout information from the datasheets into Microsoft Excel, using a layout compatible with Altium’s Smart Grid Insert function. Then, I was able to literally copy and paste pin information from Excel into Altium to generate the schematic symbols I needed.

Once I had appropriate schematic symbols available for all parts, I began making appropriate connections in the schematic view in Altium. Though tedious, this task was not exceedingly difficult. I finished the schematics in several days, and then moved on to PCB design. I switched into Altium's PCB view. The footprints corresponding to the components I used in the schematics were automatically inserted by Altium. My job was then to position these components in logical places on the board and make all of the connections corresponding to the nets defined in the schematics.

Due to the large number of components being placed in the limited space available on the digital board, Altium's auto-router proved completely useless. Therefore, I routed the board manually. Despite Altium's revolutionary convergence of schematic and PCB design into a single program, this was no easy task. During the routing process, I had to take into account not only the connections that had to be made, but also things such as avoiding crosstalk and minimizing trace length for sensitive components. I was able to complete routing after several weeks of work. The digital board design has since been completed and the board has been printed. It is currently awaiting assembly.

The analog board provided a host of new challenges. The basic schematic for the transimpedance amplifier on the analog board was completed by Igor and Dr. Jones before the semester. Inputting the schematic into Altium was not very difficult. However, one problem I encountered was that the analog board contains 32 copies of this amplifier circuitry. After failing to find any way to insert multiple copies of both the schematic and its corresponding PCB layout, I decided to insert only single copies of each schematic page, and copy and paste the PCB layout to produce 32 copies of the amplifier circuitry. At first this seemed like a quick and easy way to get all of the necessary circuitry onto the PCB. However, I eventually discovered that this procedure would lead to major problems with the board assembly process (due to duplicate component designators, and for other reasons). Fortunately, this revelation came around the same time that Igor and Dr. Jones found a problem with the performance of the amplifier circuit. Making any changes to the amplifier circuit at this point will require a major reroute of all the traces on the analog board. Since the board needs to be completely redesigned anyway, this will give me another chance to find a way to match schematics with all 32 copies of the amplifier circuitry.

The backplane design is currently in progress. It should be relatively easy to complete. All that remains to be done is to add the LEMO connectors and power inputs. The board is simple enough that it can be routed completely by the auto-router, though a quick hand routing will probably be superior. I anticipate that I can complete the backplane with a few days of concentrated work over break.

Included below are links to the files I have been working on. Included in the files for each board is a "SmartPDF," viewable in Adobe Reader. For those without Altium Designer, these may be the best files to look at. They include complete schematics and PCB layout, and are also indexed by component.

Any questions about the tagger circuitry can be directed to me at [mailto:mitchell.underwood@uconn.edu mitchell.underwood@uconn.edu]

=== Related Files ===
* [http://zeus.phys.uconn.edu/halld/tagger/electronics/design-12-2008/DigitalBoard.zip DigitalBoard.zip]:
**Altium Project File (SiPM Control Board.PrjPcb)
**Altium PCB Layout File (Prototype1.PcbDoc)
**Altium Schematic Files (*.SchDoc)
**Altium Annotation Document (SiPM Control Board.Annotation)
***Not used, but generated by Altium when opening the project
**Altium PRJPCBSTRUCTURE File (SiPM Control Board.PRJPCBSTRUCTURE)
***Not used, but generated by Altium when opening the project)
**“SmartPDF” of the board and schematics (SiPM Control Board.pdf)
***Can be used to explore the PCB layout and schematics without needing Altium
**Pick and Place File for board population (Pick Place for Prototype1.txt)
***Used by board assembler
**NC Drill Files (Prototype1.txt, Prototype1.DRR, Prototype1.DRL)
***Used by board printer
**Gerber Files for all layers (in folder Gerbers)
***Used by board printer
**Altium CAMtastic file (CAMtastic4 FINAL.Cam)
***Basically a composite of all the Gerbers
**Photos and 3D rendering of populated board
***In folder “Photos”
**EMF Files showing different layers
***In folder “EMF Renderings”
**AutoCad File of PCB (Prototype1 Autocad.DWG)
**Altium Library of Custom Footprints for Digital Board (GlueX IC Library.SchLib)
***Current as of completion of digital board
***This library has since been updated for the backplane

*[http://zeus.phys.uconn.edu/halld/tagger/electronics/design-12-2008/Analog%20Board%2020081211.zip Analog Board 20081211.zip]:
**Altium Project File (AnalogBoard.PrjPcb)
**Altium PCB Layout File (AnalogBoardPCB.PcbDoc)
**Altium Schematic Files (Amplifer1.SchDoc, Summer.SchDoc)
**“SmartPDF” of the board and schematics (AnalogBoard.pdf)
**Altium Component Definition for SiPM (SiPM Library.PcbLib)
***Contains part footprint and pin information for the SiPM component

*[http://zeus.phys.uconn.edu/halld/tagger/electronics/design-12-2008/Backplane%2020081211.zip Backplane 20081211.zip]
**Altium Project File (Backplane.PrjPcb)
**Alitum PCB Layout File (Backplane.PcbDoc)
**Altium Schematic Files (Analog Connector.SchDoc, Digital Connector.SchDoc)
***Analog Connector = Eurocard to analog board
***Digital Connector = Eurocard to digital board, +3.3V voltage regulator, and location identifier jumper
***LEMO connections not yet included in these schematics
**“SmartPDF” of the board and schematics (Backplane.pdf)
**Pin layout files used to define pinouts for custom components (Pin Layout, 96 pin connector.xlsx, Pinouts.xlsx)
***Pin Layout, 96 pin connector = pinout definition for 96 pin Eurocard connector
***Pinouts.xlsx = pinout definitions for digital board, which were reused for the 48 pin digital Eurocard receptacle on backplane
**Altium Library of Custom Components (GlueX IC Library.SchLib)
***UPDATED to include new backplane components
***An older version of this library was used for the digital board

==Summary of Spring 2009 Work==

At the end of the fall semester, Dr. Jones, Igor, and I determined that the amplifier/summing circuit we had designed simply didn’t have sufficient performance characteristics to be useful for GlueX. During the beginning of the spring semester, Igor came up with a new design, utilizing more transistors, to provide the high gain, fast response, picosecond resolution amplifier that we needed. The design performed flawlessly both in MatLab simulations and in a handmade single channel prototype. The first of my goals for the spring 2009 semester was to capture the schematic for this new amplifier into Altium designer, and layout a new amplifier board. The second of my goals, of course, was to complete production of the digital control board prototypes.

[[Image:Digital Board, Populated.JPG|thumb|The populated digital board, with a tube of Chap-BlockTM for size comparison.]] Since the fall semester left us with three unpopulated digital control board PCBs, getting those PCBs assembled with their components was the first priority. I began the semester by tracking down all of the components we needed (some of which were selected at the end of the fall semester), and making appropriate substitutions for components whose availability had changed since the fall. In the process of selecting these components, I noticed several places where it seemed like power consumption on the board may be somewhat high. To fix this, I developed a spreadsheet in Microsoft Excel that calculates optimal resistor values to use for to obtain a specified voltage divider stiffness. With this tool, I was able to optimize power consumption across the board, and select appropriate components. Once all components had been selected, ordered, and received, we sent the order out to Screamin’ Circuits for assembly. The boards came back several weeks later, and are currently awaiting testing by some undergraduates who will be in the lab this summer.

While Igor was finalizing his amplifier/summing circuit, I worked briefly on design of the backplane. A number of details regarding trace impedance and board dimensions were ironed out. Nonetheless, many problems still remain which I will need to tackle over the summer. The first of these problems is that we have yet to find an appropriate low cost coaxial connector to route signals off the backplane. In addition, screws with which to mount the backplane to the tagger must be selected so that appropriate holes can be created for them on the PCB.

Once we were satisfied that the amplifier/summing circuit performed as required, I shifted work from the backplane to the amplifier board. Around the same time, I began working on a poster to present my work at the Frontiers in Undergraduate Research Exhibition held during Open House Weekend here at UConn. If you’re interested in my poster, check it out here.

[[Image:Amplifier-Summer-Laid-out.gif|thumb|A prototype layout of 5 amplifier channels and a summing circuit. Actual size is ~1.6" tall. Areas in green represent problems to be resolved over summer 2009. A prototype amplifier with no green spots has been designed and will be replicated to this design soon.]] To start the amplifier/summing circuit project, I searched high and low for information about how to handle multi-channel designs in Altium. Not surprisingly, the first Google result on the query “multichannel design Altium” had everything I was missing during the fall when I was trying to lay out the original amplifier circuit. Using my new knowledge of Altium’s multichannel capabilities, I captured Igor’s new design into the schematics editor of Altium Designer. With proper nested schematic sheets, the entire 30 channel amplifier/6 channel summer design was compressed into just 4 schematic sheets, vs. the ~40 or so that would have been required had I laid out the complete schematics of the old design.

I spent about a week and a half trying to figure out how to handle nesting independent nets from a repeated subsheet into another repeated subsheet which also produces independent nets from the nets of the first sheet. This sounds somewhat complicated, and I suppose perhaps it is a somewhat unique situation, since none of the ~5 sample multichannel projects included with Altium had such a construction in them. Basically, each summing circuit has five amplifier subcircuits, each of which puts out its own signal independent of the other four. From the perspective of the entire board, there are 6 summers, each of which has five independent signals coming from the amplifiers, and one summed signal. Determining how to get Altium to realize the proper connections from each individual amplifier, through that amplifier’s summer, to the main schematic was a complicated mess of naming conventions, but eventually I was able to make Altium reflect all of the appropriate connections in the PCB view. Though there are a few net naming issues still to be resolved, this problem has mostly been ironed out.

The final few weeks of the semester were spent laying out amplifier components in the PCB view of Altium. As of right now, a compact design for an amplifier measuring 0.183”x~1.3” has been completed. Making use of 0201 size components, this amplifier is approximately .2” shorter than the old design, despite incorporating an extra transistor. The amplifier design features an isolating ground trace running the length of the amplifier to prevent crosstalk between channels. A prototype layout of the summing circuit has also been completed, though some layout issues there remain to be resolved over the summer.

===Related Files===
*[http://zeus.phys.uconn.edu/halld/tagger/electronics/design-6-2009/Progress20090505.zip Design Snapshot 5/5/2009]
**Backplane
***Backplane.PrjPcb (Altium Project File)
***Backplane.PcbDoc (Altium PCB File)
***Analog Connector.SchDoc, Digital Connector.SchDoc, LEMO.SchDoc (Altium Schematics)
***Backplane.pdf (SmartPDF File of the schematics and PCB layout)
**Amplifier Board
***Analog Board.PrjPcb (Altium Project File)
***Amplifier Board.PcbDoc (Altium PCB File)
***Main.SchDoc, Amplifier.SchDoc, Summer.SchDoc, Voltage References.SchDoc (Altium Schematics)
***Analog Board.pdf (SmartPDF File of the schematics and PCB layout
****The SmartPDF shows the entire PCB workspace, including components that have not yet been placed on the physical PCB.
****The bottom left corner of the PCB view shows a proof-of-concept 5 amplifiers/1 summer layout.
****Finding AMP6 using the PDF bookmarks shows the prototype amplifier layout that resolves mismatched footprint issues (indicated in green in the image farther up on this page).

== Fall 2009 Work ==

=== Mid-Semester Update, 11/12/2009 ===
We now have one fully working prototype of the SiPM Digital Control Board, and the SiPM Amplifier Board is currently being manufactured and assembled by Sierra Circuits, Inc. The backplane design is nearly complete and will be going out for quoting within a week.

Here is a zip file containing the most recent versions of the tagger files: [http://zeus.phys.uconn.edu/halld/tagger/electronics/design-11-2009/TaggerMicroscopeProgress20091112.zip Design Snapshot 11/12/2009]

A few notes about these files:
*There are four subfolders in the zip file. The folders for the three PCBs are clearly labelled. Each PCB folder has one project file (.PrjPcb) which can be opened in Altium Designer. Each project file refers to only one PcbDoc file, making it easy to figure out what you should look at to see the board.
*The SiPM digital control board project has 4 shelved polygons which should be restored (Tools->Polygon Pours->Restore 4 shelved polyons) to see the state of the board as it was last manufactured. Revisions from the testing process have not yet been entered into Altium but can be reviewed on this wiki: [[Digital control board debugging notes]]
*The SiPM amplifier (analog) board project will give an error message that it was unable to find "Test PCB.PcbDoc". Please ignore this. The file was intentionally omitted to prevent confusion, and is not related to the actual design.
*The backplane project will give an error message that it was unable to find "Backplane_New.PcbDoc". Please ignore this. The file was intentionally omitted to prevent confusion, and is not related to the actual design.

=== End of Semester Update ===
This semester, a lot of progress has been made on the tagger electronics. The digital control board is now onto revision 2.0, the amplifier board is in production, and the backplane is awaiting completion of the purchase order for production to begin. It is exciting to say that the bulk of the work is now finally complete. Remaining for the spring are the tasks of testing the amplifier board, and seeing that everything fits into the backplane. Here are some details about what I accomplished this semester, as well as links to the most recent project files.

==== Digital Control Board ====
The semester began with the digital control board prototypes sitting on lab bench waiting to be tested. My job was primarily to design the boards, not to debug them, though I still played an integral part in the testing process. We were all relieved that none of the boards appeared to smoke immediately when we first applied power, though there were a few confusing problems that had to be sorted out. Most of these problems are described in detail on the [[Digital control board debugging notes]] page. More or less, we had to solder a pin that wasn't connected, replace the crystal oscillator with a CMOS oscillator, and rewire few traces that had were accidentally connected to pins intended for other signals. I won't repeat all of the changes we made here since it would be redundant to the page that already discusses it, but the important part is that we have one board that is fully operational, and the version 2.0 schematics/layout reflecting all these changes are complete. I anticipate that production of the version 2.0 boards will occur at the beginning of the spring 2010 semester.

There is still one lingering problem with the digital board design that has not yet been resolved, however. Even after all of the version 2.0 changes were made to the version 1.0 boards, only one of the three boards produced actually functioned properly. For a reason unknown to us, two of the boards ended up with their digital to analog converters burning up and smoking. We thoroughly reviewed the schematics and the layout, and found nothing miswired. Furthermore, we analyzed the placement of the ball grid array DAC to the best of our ability, and determined that a misalignment of balls is not the cause of the failure. All of our power supplies are stable, properly decoupled, and grounded as called for by DAC's manufacturer. Currently, the best hypothesis for the failure of 2 of the 3 DACs is that one or more of the absolute maximum ratings must have been exceeded at some point during the assembly process. Analog Devices lists fairly specific specs with small tolerances relating to maximum temperature and the length of time which the DAC may spend inside a reflow oven. We have run into some difficultly trying to find out from the boards' assembler whether they followed the published specs for the assembly process, but we intend to keep trying until we get an answer.

==== Amplifier Board ====
Throughout the summer and the beginning of the fall semester, I completed the design for the SiPM Amplifier Board, version 1.0. All 30 channels have been implemented along with their summing circuits. As I mentioned in the mid semester update above, this board is being manufactured and assembled by Sierra Circuits, Inc. Some unexpected setbacks occurred in the assembly process that delayed the boards somewhat, but I believe everything is now on track for delivery of the finished product before the start of the spring semester. A number of problems relating to minimum quantities of parts, as well as part naming conventions have now been resolved, and the assembly process should be complete in several weeks.

==== Backplane ====
The backplane design, version 1.0, has also been completed. Sierra Circuits will be manufacturing the backplane, which we will assemble ourselves. The backplane is a particularly intersting PCB from a manufacturing standpoint, because it is designed to be completely light proof. Since the backplane is the only material standing between the whole of Hall D and the inside of the tagger microscope dark box, opacity of the board is particularly important.

Most PCBs with internal copper layers are already fairly opaque, because the copper blocks light from transmitting through the FR-4 and prepreg. Through hole components do not particulary compromise board opacity, because they are plugged with component pins and solder. What does have a greater affect on the opaqueness of a board, however, is the thermal reliefs by which through hole pins and vias connect to internal plane layers. These reliefs are designed to aid in the soldering process by minimizing the amount of copper that is directly connected to the plating in the hole. A typical relief consists of four 7-10 mil traces connecting the hole's plating to the internal plane. The plane itself remains about 20 mil away from the hole, to prevent conduction of heat during the soldering process. Unfortunately, this means that there is a small gap in which there is only FR-4 to stop light from passing through the board. Since FR-4 is transparent, this poses a problem for our design. We were able work with Sierra Circuits to come up with a board design that includes an internal layer of special black FR-4 to prevent light leakage through the heat reliefs. While this is certainly not a standard feature, Sierra was confident that they could implement it for us, and we look forward to testing the boards' opacity in the spring.

Woody Underwood

2009-12-17T21:54:51Z

Underwood: added fall 2009 end of semester update

== About Me ==
My name is Woody Underwood. I'm a junior entering my seventh semester in the physics program at UConn. Since the summer of 2008, I've been working in the lab of Dr. Richard Jones designing electronics for the US Department of Energy's GlueX experiment. My assignment is to develop three circuit boards that work together to tag photons coming from the diamond radiator. My circuitry essentially measures (indirectly) the energy of these photons in order to determine if they are of interest to GlueX. The three boards I am designing consist of a digital board, an analog board, and a connecting backplane.

== About My Circuitry ==
Electrons leaving the diamond radiator are deflected by a magnetic field into an array of scintillating fibres, producing photons. Wave guides carry these photons to SiPMs (silicon photomultipliers) mounted on the analog circuit board. The analog board contains transimpedance amplifiers and summing circuitry to condition the signals for digitization.

The sensitivity of the SiPMs and the gain of the amplifiers on the analog board are controlled both by the power supply VCC and bias voltages supplied from the digital board. The digital board receives commands from a computer via ethernet, and uses a 32-channel DAC to output appropriate bias voltages to the SiPMs on the analog board. The digital and analog boards are connected by means of a backplane, which is also responsible for providing power and grounds to both boards.

== Summary of Fall 2008 Work ==
All circuitry design work was done using Altium Designer. The digital board was the first to be designed. The first step in designing the digital board was to review the list of key components that had already been selected by Igor and Dr. Jones. These components included such things as the Xilinx Spartan-3A FPGA, and the Analog Devices AD5535 DAC. I began by looking through datasheets for these components to find out their needs, including power and decoupling requirements. I reviewed the pinout diagrams, and then looked through Altium’s standard libraries to find components that matched (in many cases the particular component I was looking for was not in the library, but a similar footprint or schematic symbol was). For components without matching schematic symbols, I entered pinout information from the datasheets into Microsoft Excel, using a layout compatible with Altium’s Smart Grid Insert function. Then, I was able to literally copy and paste pin information from Excel into Altium to generate the schematic symbols I needed.

Once I had appropriate schematic symbols available for all parts, I began making appropriate connections in the schematic view in Altium. Though tedious, this task was not exceedingly difficult. I finished the schematics in several days, and then moved on to PCB design. I switched into Altium's PCB view. The footprints corresponding to the components I used in the schematics were automatically inserted by Altium. My job was then to position these components in logical places on the board and make all of the connections corresponding to the nets defined in the schematics.

Due to the large number of components being placed in the limited space available on the digital board, Altium's auto-router proved completely useless. Therefore, I routed the board manually. Despite Altium's revolutionary convergence of schematic and PCB design into a single program, this was no easy task. During the routing process, I had to take into account not only the connections that had to be made, but also things such as avoiding crosstalk and minimizing trace length for sensitive components. I was able to complete routing after several weeks of work. The digital board design has since been completed and the board has been printed. It is currently awaiting assembly.

The analog board provided a host of new challenges. The basic schematic for the transimpedance amplifier on the analog board was completed by Igor and Dr. Jones before the semester. Inputting the schematic into Altium was not very difficult. However, one problem I encountered was that the analog board contains 32 copies of this amplifier circuitry. After failing to find any way to insert multiple copies of both the schematic and its corresponding PCB layout, I decided to insert only single copies of each schematic page, and copy and paste the PCB layout to produce 32 copies of the amplifier circuitry. At first this seemed like a quick and easy way to get all of the necessary circuitry onto the PCB. However, I eventually discovered that this procedure would lead to major problems with the board assembly process (due to duplicate component designators, and for other reasons). Fortunately, this revelation came around the same time that Igor and Dr. Jones found a problem with the performance of the amplifier circuit. Making any changes to the amplifier circuit at this point will require a major reroute of all the traces on the analog board. Since the board needs to be completely redesigned anyway, this will give me another chance to find a way to match schematics with all 32 copies of the amplifier circuitry.

The backplane design is currently in progress. It should be relatively easy to complete. All that remains to be done is to add the LEMO connectors and power inputs. The board is simple enough that it can be routed completely by the auto-router, though a quick hand routing will probably be superior. I anticipate that I can complete the backplane with a few days of concentrated work over break.

Included below are links to the files I have been working on. Included in the files for each board is a "SmartPDF," viewable in Adobe Reader. For those without Altium Designer, these may be the best files to look at. They include complete schematics and PCB layout, and are also indexed by component.

Any questions about the tagger circuitry can be directed to me at [mailto:mitchell.underwood@uconn.edu mitchell.underwood@uconn.edu]

=== Related Files ===
* [http://zeus.phys.uconn.edu/halld/tagger/electronics/design-12-2008/DigitalBoard.zip DigitalBoard.zip]:
**Altium Project File (SiPM Control Board.PrjPcb)
**Altium PCB Layout File (Prototype1.PcbDoc)
**Altium Schematic Files (*.SchDoc)
**Altium Annotation Document (SiPM Control Board.Annotation)
***Not used, but generated by Altium when opening the project
**Altium PRJPCBSTRUCTURE File (SiPM Control Board.PRJPCBSTRUCTURE)
***Not used, but generated by Altium when opening the project)
**“SmartPDF” of the board and schematics (SiPM Control Board.pdf)
***Can be used to explore the PCB layout and schematics without needing Altium
**Pick and Place File for board population (Pick Place for Prototype1.txt)
***Used by board assembler
**NC Drill Files (Prototype1.txt, Prototype1.DRR, Prototype1.DRL)
***Used by board printer
**Gerber Files for all layers (in folder Gerbers)
***Used by board printer
**Altium CAMtastic file (CAMtastic4 FINAL.Cam)
***Basically a composite of all the Gerbers
**Photos and 3D rendering of populated board
***In folder “Photos”
**EMF Files showing different layers
***In folder “EMF Renderings”
**AutoCad File of PCB (Prototype1 Autocad.DWG)
**Altium Library of Custom Footprints for Digital Board (GlueX IC Library.SchLib)
***Current as of completion of digital board
***This library has since been updated for the backplane

*[http://zeus.phys.uconn.edu/halld/tagger/electronics/design-12-2008/Analog%20Board%2020081211.zip Analog Board 20081211.zip]:
**Altium Project File (AnalogBoard.PrjPcb)
**Altium PCB Layout File (AnalogBoardPCB.PcbDoc)
**Altium Schematic Files (Amplifer1.SchDoc, Summer.SchDoc)
**“SmartPDF” of the board and schematics (AnalogBoard.pdf)
**Altium Component Definition for SiPM (SiPM Library.PcbLib)
***Contains part footprint and pin information for the SiPM component

*[http://zeus.phys.uconn.edu/halld/tagger/electronics/design-12-2008/Backplane%2020081211.zip Backplane 20081211.zip]
**Altium Project File (Backplane.PrjPcb)
**Alitum PCB Layout File (Backplane.PcbDoc)
**Altium Schematic Files (Analog Connector.SchDoc, Digital Connector.SchDoc)
***Analog Connector = Eurocard to analog board
***Digital Connector = Eurocard to digital board, +3.3V voltage regulator, and location identifier jumper
***LEMO connections not yet included in these schematics
**“SmartPDF” of the board and schematics (Backplane.pdf)
**Pin layout files used to define pinouts for custom components (Pin Layout, 96 pin connector.xlsx, Pinouts.xlsx)
***Pin Layout, 96 pin connector = pinout definition for 96 pin Eurocard connector
***Pinouts.xlsx = pinout definitions for digital board, which were reused for the 48 pin digital Eurocard receptacle on backplane
**Altium Library of Custom Components (GlueX IC Library.SchLib)
***UPDATED to include new backplane components
***An older version of this library was used for the digital board

==Summary of Spring 2009 Work==

At the end of the fall semester, Dr. Jones, Igor, and I determined that the amplifier/summing circuit we had designed simply didn’t have sufficient performance characteristics to be useful for GlueX. During the beginning of the spring semester, Igor came up with a new design, utilizing more transistors, to provide the high gain, fast response, picosecond resolution amplifier that we needed. The design performed flawlessly both in MatLab simulations and in a handmade single channel prototype. The first of my goals for the spring 2009 semester was to capture the schematic for this new amplifier into Altium designer, and layout a new amplifier board. The second of my goals, of course, was to complete production of the digital control board prototypes.

[[Image:Digital Board, Populated.JPG|thumb|The populated digital board, with a tube of Chap-BlockTM for size comparison.]] Since the fall semester left us with three unpopulated digital control board PCBs, getting those PCBs assembled with their components was the first priority. I began the semester by tracking down all of the components we needed (some of which were selected at the end of the fall semester), and making appropriate substitutions for components whose availability had changed since the fall. In the process of selecting these components, I noticed several places where it seemed like power consumption on the board may be somewhat high. To fix this, I developed a spreadsheet in Microsoft Excel that calculates optimal resistor values to use for to obtain a specified voltage divider stiffness. With this tool, I was able to optimize power consumption across the board, and select appropriate components. Once all components had been selected, ordered, and received, we sent the order out to Screamin’ Circuits for assembly. The boards came back several weeks later, and are currently awaiting testing by some undergraduates who will be in the lab this summer.

While Igor was finalizing his amplifier/summing circuit, I worked briefly on design of the backplane. A number of details regarding trace impedance and board dimensions were ironed out. Nonetheless, many problems still remain which I will need to tackle over the summer. The first of these problems is that we have yet to find an appropriate low cost coaxial connector to route signals off the backplane. In addition, screws with which to mount the backplane to the tagger must be selected so that appropriate holes can be created for them on the PCB.

Once we were satisfied that the amplifier/summing circuit performed as required, I shifted work from the backplane to the amplifier board. Around the same time, I began working on a poster to present my work at the Frontiers in Undergraduate Research Exhibition held during Open House Weekend here at UConn. If you’re interested in my poster, check it out here.

[[Image:Amplifier-Summer-Laid-out.gif|thumb|A prototype layout of 5 amplifier channels and a summing circuit. Actual size is ~1.6" tall. Areas in green represent problems to be resolved over summer 2009. A prototype amplifier with no green spots has been designed and will be replicated to this design soon.]] To start the amplifier/summing circuit project, I searched high and low for information about how to handle multi-channel designs in Altium. Not surprisingly, the first Google result on the query “multichannel design Altium” had everything I was missing during the fall when I was trying to lay out the original amplifier circuit. Using my new knowledge of Altium’s multichannel capabilities, I captured Igor’s new design into the schematics editor of Altium Designer. With proper nested schematic sheets, the entire 30 channel amplifier/6 channel summer design was compressed into just 4 schematic sheets, vs. the ~40 or so that would have been required had I laid out the complete schematics of the old design.

I spent about a week and a half trying to figure out how to handle nesting independent nets from a repeated subsheet into another repeated subsheet which also produces independent nets from the nets of the first sheet. This sounds somewhat complicated, and I suppose perhaps it is a somewhat unique situation, since none of the ~5 sample multichannel projects included with Altium had such a construction in them. Basically, each summing circuit has five amplifier subcircuits, each of which puts out its own signal independent of the other four. From the perspective of the entire board, there are 6 summers, each of which has five independent signals coming from the amplifiers, and one summed signal. Determining how to get Altium to realize the proper connections from each individual amplifier, through that amplifier’s summer, to the main schematic was a complicated mess of naming conventions, but eventually I was able to make Altium reflect all of the appropriate connections in the PCB view. Though there are a few net naming issues still to be resolved, this problem has mostly been ironed out.

The final few weeks of the semester were spent laying out amplifier components in the PCB view of Altium. As of right now, a compact design for an amplifier measuring 0.183”x~1.3” has been completed. Making use of 0201 size components, this amplifier is approximately .2” shorter than the old design, despite incorporating an extra transistor. The amplifier design features an isolating ground trace running the length of the amplifier to prevent crosstalk between channels. A prototype layout of the summing circuit has also been completed, though some layout issues there remain to be resolved over the summer.

===Related Files===
*[http://zeus.phys.uconn.edu/halld/tagger/electronics/design-6-2009/Progress20090505.zip Design Snapshot 5/5/2009]
**Backplane
***Backplane.PrjPcb (Altium Project File)
***Backplane.PcbDoc (Altium PCB File)
***Analog Connector.SchDoc, Digital Connector.SchDoc, LEMO.SchDoc (Altium Schematics)
***Backplane.pdf (SmartPDF File of the schematics and PCB layout)
**Amplifier Board
***Analog Board.PrjPcb (Altium Project File)
***Amplifier Board.PcbDoc (Altium PCB File)
***Main.SchDoc, Amplifier.SchDoc, Summer.SchDoc, Voltage References.SchDoc (Altium Schematics)
***Analog Board.pdf (SmartPDF File of the schematics and PCB layout
****The SmartPDF shows the entire PCB workspace, including components that have not yet been placed on the physical PCB.
****The bottom left corner of the PCB view shows a proof-of-concept 5 amplifiers/1 summer layout.
****Finding AMP6 using the PDF bookmarks shows the prototype amplifier layout that resolves mismatched footprint issues (indicated in green in the image farther up on this page).

== Fall 2009 Work ==

=== Mid-Semester Update, 11/12/2009 ===
We now have one fully working prototype of the SiPM Digital Control Board, and the SiPM Amplifier Board is currently being manufactured and assembled by Sierra Circuits, Inc. The backplane design is nearly complete and will be going out for quoting within a week.

Here is a zip file containing the most recent versions of the tagger files: [http://zeus.phys.uconn.edu/halld/tagger/electronics/design-11-2009/TaggerMicroscopeProgress20091112.zip Design Snapshot 11/12/2009]

A few notes about these files:
*There are four subfolders in the zip file. The folders for the three PCBs are clearly labelled. Each PCB folder has one project file (.PrjPcb) which can be opened in Altium Designer. Each project file refers to only one PcbDoc file, making it easy to figure out what you should look at to see the board.
*The SiPM digital control board project has 4 shelved polygons which should be restored (Tools->Polygon Pours->Restore 4 shelved polyons) to see the state of the board as it was last manufactured. Revisions from the testing process have not yet been entered into Altium but can be reviewed on this wiki: [[Digital control board debugging notes]]
*The SiPM amplifier (analog) board project will give an error message that it was unable to find "Test PCB.PcbDoc". Please ignore this. The file was intentionally omitted to prevent confusion, and is not related to the actual design.
*The backplane project will give an error message that it was unable to find "Backplane_New.PcbDoc". Please ignore this. The file was intentionally omitted to prevent confusion, and is not related to the actual design.

=== End of Semester Update ===
This semester, a lot of progress has been made on the tagger electronics. The digital control board is now onto revision 2.0, the amplifier board is in production, and the backplane is awaiting completion of the purchase order for production to begin. It is exciting to say that the bulk of the work is now finally complete. Remaining for the spring are the tasks of testing the amplifier board, and seeing that everything fits into the backplane. Here are some details about what I accomplished this semester, as well as links to the most recent project files.

==== Digital Control Board ====
The semester began with the digital control board prototypes sitting on lab bench waiting to be tested. My job was primarily to design the boards, not to debug them, though I still played an integral part in the testing process. We were all relieved that none of the boards appeared to smoke immediately when we first applied power, though there were a few confusing problems that had to be sorted out. Most of these problems are described in detail on the [[Digital control board debugging notes]]
page. More or less, we had to solder a pin that wasn't connected, replace the crystal oscillator with a CMOS oscillator, and rewire few traces that had were accidentally connected to pins intended for other signals. I won't repeat all of the changes we made here since it would be redundant to the page that already discusses it, but the important part is that we have one board that is fully operational, and the version 2.0 schematics/layout reflecting all these changes are complete. I anticipate that production of the version 2.0 boards will occur at the beginning of the spring 2010 semester.

There is still one lingering problem with the digital board design that has not yet been resolved, however. Even after all of the version 2.0 changes were made to the version 1.0 boards, only one of the three boards produced actually functioned properly. For a reason unknown to us, two of the boards ended up with their digital to analog converters burning up and smoking. We thoroughly reviewed the schematics and the layout, and found nothing miswired. Furthermore, we analyzed the placement of the ball grid array DAC to the best of our ability, and determined that a misalignment of balls is not the cause of the failure. All of our power supplies are stable, properly decoupled, and grounded as called for by DAC's manufacturer. Currently, the best hypothesis for the failure of 2 of the 3 DACs is that one or more of the absolute maximum ratings must have been exceeded at some point during the assembly process. Analog Devices lists fairly specific specs with small tolerances relating to maximum temperature and the length of time which the DAC may spend inside a reflow oven. We have run into some difficultly trying to find out from the boards' assembler whether they followed the published specs for the assembly process, but we intend to keep trying until we get an answer.

==== Amplifier Board ====
Throughout the summer and the beginning of the fall semester, I completed the design for the SiPM Amplifier Board, version 1.0. All 30 channels have been implemented along with their summing circuits. As I mentioned in the mid semester update above, this board is being manufactured and assembled by Sierra Circuits, Inc. Some unexpected setbacks occurred in the assembly process that delayed the boards somewhat, but I believe everything is now on track for delivery of the finished product before the start of the spring semester. A number of problems relating to minimum quantities of parts, as well as part naming conventions have now been resolved, and the assembly process should be complete in several weeks.

==== Backplane ====
The backplane design, version 1.0, has also been completed. Sierra Circuits will be manufacturing the backplane, which we will assemble ourselves. The backplane is a particularly intersting PCB from a manufacturing standpoint, because it is designed to be completely light proof. Since the backplane is the only material standing between the whole of Hall D and the inside of the tagger microscope dark box, opacity of the board is particularly important.

Most PCBs with internal copper layers are already fairly opaque, because the copper blocks light from transmitting through the FR-4 and prepreg. Through hole components do not particulary compromise board opacity, because they are plugged with component pins and solder. What does have a greater affect on the opaqueness of a board, however, is the thermal reliefs by which through hole pins and vias connect to internal plane layers. These reliefs are designed to aid in the soldering process by minimizing the amount of copper that is directly connected to the plating in the hole. A typical relief consists of four 7-10 mil traces connecting the hole's plating to the internal plane. The plane itself remains about 20 mil away from the hole, to prevent conduction of heat during the soldering process. Unfortunately, this means that there is a small gap in which there is only FR-4 to stop light from passing through the board. Since FR-4 is transparent, this poses a problem for our design. We were able work with Sierra Circuits to come up with a board design that includes an internal layer of special black FR-4 to prevent light leakage through the heat reliefs. While this is certainly not a standard feature, Sierra was confident that they could implement it for us, and we look forward to testing the boards' opacity in the spring.

Woody Underwood

2009-12-17T20:01:04Z

Underwood: /* Fall 2009, Current Progress */ changed section title

== About Me ==
My name is Woody Underwood. I'm a junior entering my seventh semester in the physics program at UConn. Since the summer of 2008, I've been working in the lab of Dr. Richard Jones designing electronics for the US Department of Energy's GlueX experiment. My assignment is to develop three circuit boards that work together to tag photons coming from the diamond radiator. My circuitry essentially measures (indirectly) the energy of these photons in order to determine if they are of interest to GlueX. The three boards I am designing consist of a digital board, an analog board, and a connecting backplane.

== About My Circuitry ==
Electrons leaving the diamond radiator are deflected by a magnetic field into an array of scintillating fibres, producing photons. Wave guides carry these photons to SiPMs (silicon photomultipliers) mounted on the analog circuit board. The analog board contains transimpedance amplifiers and summing circuitry to condition the signals for digitization.

The sensitivity of the SiPMs and the gain of the amplifiers on the analog board are controlled both by the power supply VCC and bias voltages supplied from the digital board. The digital board receives commands from a computer via ethernet, and uses a 32-channel DAC to output appropriate bias voltages to the SiPMs on the analog board. The digital and analog boards are connected by means of a backplane, which is also responsible for providing power and grounds to both boards.

== Summary of Fall 2008 Work ==
All circuitry design work was done using Altium Designer. The digital board was the first to be designed. The first step in designing the digital board was to review the list of key components that had already been selected by Igor and Dr. Jones. These components included such things as the Xilinx Spartan-3A FPGA, and the Analog Devices AD5535 DAC. I began by looking through datasheets for these components to find out their needs, including power and decoupling requirements. I reviewed the pinout diagrams, and then looked through Altium’s standard libraries to find components that matched (in many cases the particular component I was looking for was not in the library, but a similar footprint or schematic symbol was). For components without matching schematic symbols, I entered pinout information from the datasheets into Microsoft Excel, using a layout compatible with Altium’s Smart Grid Insert function. Then, I was able to literally copy and paste pin information from Excel into Altium to generate the schematic symbols I needed.

Once I had appropriate schematic symbols available for all parts, I began making appropriate connections in the schematic view in Altium. Though tedious, this task was not exceedingly difficult. I finished the schematics in several days, and then moved on to PCB design. I switched into Altium's PCB view. The footprints corresponding to the components I used in the schematics were automatically inserted by Altium. My job was then to position these components in logical places on the board and make all of the connections corresponding to the nets defined in the schematics.

Due to the large number of components being placed in the limited space available on the digital board, Altium's auto-router proved completely useless. Therefore, I routed the board manually. Despite Altium's revolutionary convergence of schematic and PCB design into a single program, this was no easy task. During the routing process, I had to take into account not only the connections that had to be made, but also things such as avoiding crosstalk and minimizing trace length for sensitive components. I was able to complete routing after several weeks of work. The digital board design has since been completed and the board has been printed. It is currently awaiting assembly.

The analog board provided a host of new challenges. The basic schematic for the transimpedance amplifier on the analog board was completed by Igor and Dr. Jones before the semester. Inputting the schematic into Altium was not very difficult. However, one problem I encountered was that the analog board contains 32 copies of this amplifier circuitry. After failing to find any way to insert multiple copies of both the schematic and its corresponding PCB layout, I decided to insert only single copies of each schematic page, and copy and paste the PCB layout to produce 32 copies of the amplifier circuitry. At first this seemed like a quick and easy way to get all of the necessary circuitry onto the PCB. However, I eventually discovered that this procedure would lead to major problems with the board assembly process (due to duplicate component designators, and for other reasons). Fortunately, this revelation came around the same time that Igor and Dr. Jones found a problem with the performance of the amplifier circuit. Making any changes to the amplifier circuit at this point will require a major reroute of all the traces on the analog board. Since the board needs to be completely redesigned anyway, this will give me another chance to find a way to match schematics with all 32 copies of the amplifier circuitry.

The backplane design is currently in progress. It should be relatively easy to complete. All that remains to be done is to add the LEMO connectors and power inputs. The board is simple enough that it can be routed completely by the auto-router, though a quick hand routing will probably be superior. I anticipate that I can complete the backplane with a few days of concentrated work over break.

Included below are links to the files I have been working on. Included in the files for each board is a "SmartPDF," viewable in Adobe Reader. For those without Altium Designer, these may be the best files to look at. They include complete schematics and PCB layout, and are also indexed by component.

Any questions about the tagger circuitry can be directed to me at [mailto:mitchell.underwood@uconn.edu mitchell.underwood@uconn.edu]

=== Related Files ===
* [http://zeus.phys.uconn.edu/halld/tagger/electronics/design-12-2008/DigitalBoard.zip DigitalBoard.zip]:
**Altium Project File (SiPM Control Board.PrjPcb)
**Altium PCB Layout File (Prototype1.PcbDoc)
**Altium Schematic Files (*.SchDoc)
**Altium Annotation Document (SiPM Control Board.Annotation)
***Not used, but generated by Altium when opening the project
**Altium PRJPCBSTRUCTURE File (SiPM Control Board.PRJPCBSTRUCTURE)
***Not used, but generated by Altium when opening the project)
**“SmartPDF” of the board and schematics (SiPM Control Board.pdf)
***Can be used to explore the PCB layout and schematics without needing Altium
**Pick and Place File for board population (Pick Place for Prototype1.txt)
***Used by board assembler
**NC Drill Files (Prototype1.txt, Prototype1.DRR, Prototype1.DRL)
***Used by board printer
**Gerber Files for all layers (in folder Gerbers)
***Used by board printer
**Altium CAMtastic file (CAMtastic4 FINAL.Cam)
***Basically a composite of all the Gerbers
**Photos and 3D rendering of populated board
***In folder “Photos”
**EMF Files showing different layers
***In folder “EMF Renderings”
**AutoCad File of PCB (Prototype1 Autocad.DWG)
**Altium Library of Custom Footprints for Digital Board (GlueX IC Library.SchLib)
***Current as of completion of digital board
***This library has since been updated for the backplane

*[http://zeus.phys.uconn.edu/halld/tagger/electronics/design-12-2008/Analog%20Board%2020081211.zip Analog Board 20081211.zip]:
**Altium Project File (AnalogBoard.PrjPcb)
**Altium PCB Layout File (AnalogBoardPCB.PcbDoc)
**Altium Schematic Files (Amplifer1.SchDoc, Summer.SchDoc)
**“SmartPDF” of the board and schematics (AnalogBoard.pdf)
**Altium Component Definition for SiPM (SiPM Library.PcbLib)
***Contains part footprint and pin information for the SiPM component

*[http://zeus.phys.uconn.edu/halld/tagger/electronics/design-12-2008/Backplane%2020081211.zip Backplane 20081211.zip]
**Altium Project File (Backplane.PrjPcb)
**Alitum PCB Layout File (Backplane.PcbDoc)
**Altium Schematic Files (Analog Connector.SchDoc, Digital Connector.SchDoc)
***Analog Connector = Eurocard to analog board
***Digital Connector = Eurocard to digital board, +3.3V voltage regulator, and location identifier jumper
***LEMO connections not yet included in these schematics
**“SmartPDF” of the board and schematics (Backplane.pdf)
**Pin layout files used to define pinouts for custom components (Pin Layout, 96 pin connector.xlsx, Pinouts.xlsx)
***Pin Layout, 96 pin connector = pinout definition for 96 pin Eurocard connector
***Pinouts.xlsx = pinout definitions for digital board, which were reused for the 48 pin digital Eurocard receptacle on backplane
**Altium Library of Custom Components (GlueX IC Library.SchLib)
***UPDATED to include new backplane components
***An older version of this library was used for the digital board

==Summary of Spring 2009 Work==

At the end of the fall semester, Dr. Jones, Igor, and I determined that the amplifier/summing circuit we had designed simply didn’t have sufficient performance characteristics to be useful for GlueX. During the beginning of the spring semester, Igor came up with a new design, utilizing more transistors, to provide the high gain, fast response, picosecond resolution amplifier that we needed. The design performed flawlessly both in MatLab simulations and in a handmade single channel prototype. The first of my goals for the spring 2009 semester was to capture the schematic for this new amplifier into Altium designer, and layout a new amplifier board. The second of my goals, of course, was to complete production of the digital control board prototypes.

[[Image:Digital Board, Populated.JPG|thumb|The populated digital board, with a tube of Chap-BlockTM for size comparison.]] Since the fall semester left us with three unpopulated digital control board PCBs, getting those PCBs assembled with their components was the first priority. I began the semester by tracking down all of the components we needed (some of which were selected at the end of the fall semester), and making appropriate substitutions for components whose availability had changed since the fall. In the process of selecting these components, I noticed several places where it seemed like power consumption on the board may be somewhat high. To fix this, I developed a spreadsheet in Microsoft Excel that calculates optimal resistor values to use for to obtain a specified voltage divider stiffness. With this tool, I was able to optimize power consumption across the board, and select appropriate components. Once all components had been selected, ordered, and received, we sent the order out to Screamin’ Circuits for assembly. The boards came back several weeks later, and are currently awaiting testing by some undergraduates who will be in the lab this summer.

While Igor was finalizing his amplifier/summing circuit, I worked briefly on design of the backplane. A number of details regarding trace impedance and board dimensions were ironed out. Nonetheless, many problems still remain which I will need to tackle over the summer. The first of these problems is that we have yet to find an appropriate low cost coaxial connector to route signals off the backplane. In addition, screws with which to mount the backplane to the tagger must be selected so that appropriate holes can be created for them on the PCB.

Once we were satisfied that the amplifier/summing circuit performed as required, I shifted work from the backplane to the amplifier board. Around the same time, I began working on a poster to present my work at the Frontiers in Undergraduate Research Exhibition held during Open House Weekend here at UConn. If you’re interested in my poster, check it out here.

[[Image:Amplifier-Summer-Laid-out.gif|thumb|A prototype layout of 5 amplifier channels and a summing circuit. Actual size is ~1.6" tall. Areas in green represent problems to be resolved over summer 2009. A prototype amplifier with no green spots has been designed and will be replicated to this design soon.]] To start the amplifier/summing circuit project, I searched high and low for information about how to handle multi-channel designs in Altium. Not surprisingly, the first Google result on the query “multichannel design Altium” had everything I was missing during the fall when I was trying to lay out the original amplifier circuit. Using my new knowledge of Altium’s multichannel capabilities, I captured Igor’s new design into the schematics editor of Altium Designer. With proper nested schematic sheets, the entire 30 channel amplifier/6 channel summer design was compressed into just 4 schematic sheets, vs. the ~40 or so that would have been required had I laid out the complete schematics of the old design.

I spent about a week and a half trying to figure out how to handle nesting independent nets from a repeated subsheet into another repeated subsheet which also produces independent nets from the nets of the first sheet. This sounds somewhat complicated, and I suppose perhaps it is a somewhat unique situation, since none of the ~5 sample multichannel projects included with Altium had such a construction in them. Basically, each summing circuit has five amplifier subcircuits, each of which puts out its own signal independent of the other four. From the perspective of the entire board, there are 6 summers, each of which has five independent signals coming from the amplifiers, and one summed signal. Determining how to get Altium to realize the proper connections from each individual amplifier, through that amplifier’s summer, to the main schematic was a complicated mess of naming conventions, but eventually I was able to make Altium reflect all of the appropriate connections in the PCB view. Though there are a few net naming issues still to be resolved, this problem has mostly been ironed out.

The final few weeks of the semester were spent laying out amplifier components in the PCB view of Altium. As of right now, a compact design for an amplifier measuring 0.183”x~1.3” has been completed. Making use of 0201 size components, this amplifier is approximately .2” shorter than the old design, despite incorporating an extra transistor. The amplifier design features an isolating ground trace running the length of the amplifier to prevent crosstalk between channels. A prototype layout of the summing circuit has also been completed, though some layout issues there remain to be resolved over the summer.

===Related Files===
*[http://zeus.phys.uconn.edu/halld/tagger/electronics/design-6-2009/Progress20090505.zip Design Snapshot 5/5/2009]
**Backplane
***Backplane.PrjPcb (Altium Project File)
***Backplane.PcbDoc (Altium PCB File)
***Analog Connector.SchDoc, Digital Connector.SchDoc, LEMO.SchDoc (Altium Schematics)
***Backplane.pdf (SmartPDF File of the schematics and PCB layout)
**Amplifier Board
***Analog Board.PrjPcb (Altium Project File)
***Amplifier Board.PcbDoc (Altium PCB File)
***Main.SchDoc, Amplifier.SchDoc, Summer.SchDoc, Voltage References.SchDoc (Altium Schematics)
***Analog Board.pdf (SmartPDF File of the schematics and PCB layout
****The SmartPDF shows the entire PCB workspace, including components that have not yet been placed on the physical PCB.
****The bottom left corner of the PCB view shows a proof-of-concept 5 amplifiers/1 summer layout.
****Finding AMP6 using the PDF bookmarks shows the prototype amplifier layout that resolves mismatched footprint issues (indicated in green in the image farther up on this page).

== Fall 2009, Mid-Semester Update ==
We now have one fully working prototype of the SiPM Digital Control Board, and the SiPM Amplifier Board is currently being manufactured and assembled by Sierra Circuits, Inc. The backplane design is nearly complete and will be going out for quoting within a week.

Here is a zip file containing the most recent versions of the tagger files: [http://zeus.phys.uconn.edu/halld/tagger/electronics/design-11-2009/TaggerMicroscopeProgress20091112.zip Design Snapshot 11/12/2009]

A few notes about these files:
*There are four subfolders in the zip file. The folders for the three PCBs are clearly labelled. Each PCB folder has one project file (.PrjPcb) which can be opened in Altium Designer. Each project file refers to only one PcbDoc file, making it easy to figure out what you should look at to see the board.
*The SiPM digital control board project has 4 shelved polygons which should be restored (Tools->Polygon Pours->Restore 4 shelved polyons) to see the state of the board as it was last manufactured. Revisions from the testing process have not yet been entered into Altium but can be reviewed on this wiki: [[Digital control board debugging notes]]
*The SiPM amplifier (analog) board project will give an error message that it was unable to find "Test PCB.PcbDoc". Please ignore this. The file was intentionally omitted to prevent confusion, and is not related to the actual design.
*The backplane project will give an error message that it was unable to find "Backplane_New.PcbDoc". Please ignore this. The file was intentionally omitted to prevent confusion, and is not related to the actual design.

Woody Underwood

2009-11-12T15:43:36Z

Underwood: /* Fall 2009, Current Progress */ added link to debugging notes

== About Me ==
My name is Woody Underwood. I'm a junior entering my seventh semester in the physics program at UConn. Since the summer of 2008, I've been working in the lab of Dr. Richard Jones designing electronics for the US Department of Energy's GlueX experiment. My assignment is to develop three circuit boards that work together to tag photons coming from the diamond radiator. My circuitry essentially measures (indirectly) the energy of these photons in order to determine if they are of interest to GlueX. The three boards I am designing consist of a digital board, an analog board, and a connecting backplane.

== About My Circuitry ==
Electrons leaving the diamond radiator are deflected by a magnetic field into an array of scintillating fibres, producing photons. Wave guides carry these photons to SiPMs (silicon photomultipliers) mounted on the analog circuit board. The analog board contains transimpedance amplifiers and summing circuitry to condition the signals for digitization.

The sensitivity of the SiPMs and the gain of the amplifiers on the analog board are controlled both by the power supply VCC and bias voltages supplied from the digital board. The digital board receives commands from a computer via ethernet, and uses a 32-channel DAC to output appropriate bias voltages to the SiPMs on the analog board. The digital and analog boards are connected by means of a backplane, which is also responsible for providing power and grounds to both boards.

== Summary of Fall 2008 Work ==
All circuitry design work was done using Altium Designer. The digital board was the first to be designed. The first step in designing the digital board was to review the list of key components that had already been selected by Igor and Dr. Jones. These components included such things as the Xilinx Spartan-3A FPGA, and the Analog Devices AD5535 DAC. I began by looking through datasheets for these components to find out their needs, including power and decoupling requirements. I reviewed the pinout diagrams, and then looked through Altium’s standard libraries to find components that matched (in many cases the particular component I was looking for was not in the library, but a similar footprint or schematic symbol was). For components without matching schematic symbols, I entered pinout information from the datasheets into Microsoft Excel, using a layout compatible with Altium’s Smart Grid Insert function. Then, I was able to literally copy and paste pin information from Excel into Altium to generate the schematic symbols I needed.

Once I had appropriate schematic symbols available for all parts, I began making appropriate connections in the schematic view in Altium. Though tedious, this task was not exceedingly difficult. I finished the schematics in several days, and then moved on to PCB design. I switched into Altium's PCB view. The footprints corresponding to the components I used in the schematics were automatically inserted by Altium. My job was then to position these components in logical places on the board and make all of the connections corresponding to the nets defined in the schematics.

Due to the large number of components being placed in the limited space available on the digital board, Altium's auto-router proved completely useless. Therefore, I routed the board manually. Despite Altium's revolutionary convergence of schematic and PCB design into a single program, this was no easy task. During the routing process, I had to take into account not only the connections that had to be made, but also things such as avoiding crosstalk and minimizing trace length for sensitive components. I was able to complete routing after several weeks of work. The digital board design has since been completed and the board has been printed. It is currently awaiting assembly.

The analog board provided a host of new challenges. The basic schematic for the transimpedance amplifier on the analog board was completed by Igor and Dr. Jones before the semester. Inputting the schematic into Altium was not very difficult. However, one problem I encountered was that the analog board contains 32 copies of this amplifier circuitry. After failing to find any way to insert multiple copies of both the schematic and its corresponding PCB layout, I decided to insert only single copies of each schematic page, and copy and paste the PCB layout to produce 32 copies of the amplifier circuitry. At first this seemed like a quick and easy way to get all of the necessary circuitry onto the PCB. However, I eventually discovered that this procedure would lead to major problems with the board assembly process (due to duplicate component designators, and for other reasons). Fortunately, this revelation came around the same time that Igor and Dr. Jones found a problem with the performance of the amplifier circuit. Making any changes to the amplifier circuit at this point will require a major reroute of all the traces on the analog board. Since the board needs to be completely redesigned anyway, this will give me another chance to find a way to match schematics with all 32 copies of the amplifier circuitry.

The backplane design is currently in progress. It should be relatively easy to complete. All that remains to be done is to add the LEMO connectors and power inputs. The board is simple enough that it can be routed completely by the auto-router, though a quick hand routing will probably be superior. I anticipate that I can complete the backplane with a few days of concentrated work over break.

Included below are links to the files I have been working on. Included in the files for each board is a "SmartPDF," viewable in Adobe Reader. For those without Altium Designer, these may be the best files to look at. They include complete schematics and PCB layout, and are also indexed by component.

Any questions about the tagger circuitry can be directed to me at [mailto:mitchell.underwood@uconn.edu mitchell.underwood@uconn.edu]

=== Related Files ===
* [http://zeus.phys.uconn.edu/halld/tagger/electronics/design-12-2008/DigitalBoard.zip DigitalBoard.zip]:
**Altium Project File (SiPM Control Board.PrjPcb)
**Altium PCB Layout File (Prototype1.PcbDoc)
**Altium Schematic Files (*.SchDoc)
**Altium Annotation Document (SiPM Control Board.Annotation)
***Not used, but generated by Altium when opening the project
**Altium PRJPCBSTRUCTURE File (SiPM Control Board.PRJPCBSTRUCTURE)
***Not used, but generated by Altium when opening the project)
**“SmartPDF” of the board and schematics (SiPM Control Board.pdf)
***Can be used to explore the PCB layout and schematics without needing Altium
**Pick and Place File for board population (Pick Place for Prototype1.txt)
***Used by board assembler
**NC Drill Files (Prototype1.txt, Prototype1.DRR, Prototype1.DRL)
***Used by board printer
**Gerber Files for all layers (in folder Gerbers)
***Used by board printer
**Altium CAMtastic file (CAMtastic4 FINAL.Cam)
***Basically a composite of all the Gerbers
**Photos and 3D rendering of populated board
***In folder “Photos”
**EMF Files showing different layers
***In folder “EMF Renderings”
**AutoCad File of PCB (Prototype1 Autocad.DWG)
**Altium Library of Custom Footprints for Digital Board (GlueX IC Library.SchLib)
***Current as of completion of digital board
***This library has since been updated for the backplane

*[http://zeus.phys.uconn.edu/halld/tagger/electronics/design-12-2008/Analog%20Board%2020081211.zip Analog Board 20081211.zip]:
**Altium Project File (AnalogBoard.PrjPcb)
**Altium PCB Layout File (AnalogBoardPCB.PcbDoc)
**Altium Schematic Files (Amplifer1.SchDoc, Summer.SchDoc)
**“SmartPDF” of the board and schematics (AnalogBoard.pdf)
**Altium Component Definition for SiPM (SiPM Library.PcbLib)
***Contains part footprint and pin information for the SiPM component

*[http://zeus.phys.uconn.edu/halld/tagger/electronics/design-12-2008/Backplane%2020081211.zip Backplane 20081211.zip]
**Altium Project File (Backplane.PrjPcb)
**Alitum PCB Layout File (Backplane.PcbDoc)
**Altium Schematic Files (Analog Connector.SchDoc, Digital Connector.SchDoc)
***Analog Connector = Eurocard to analog board
***Digital Connector = Eurocard to digital board, +3.3V voltage regulator, and location identifier jumper
***LEMO connections not yet included in these schematics
**“SmartPDF” of the board and schematics (Backplane.pdf)
**Pin layout files used to define pinouts for custom components (Pin Layout, 96 pin connector.xlsx, Pinouts.xlsx)
***Pin Layout, 96 pin connector = pinout definition for 96 pin Eurocard connector
***Pinouts.xlsx = pinout definitions for digital board, which were reused for the 48 pin digital Eurocard receptacle on backplane
**Altium Library of Custom Components (GlueX IC Library.SchLib)
***UPDATED to include new backplane components
***An older version of this library was used for the digital board

==Summary of Spring 2009 Work==

At the end of the fall semester, Dr. Jones, Igor, and I determined that the amplifier/summing circuit we had designed simply didn’t have sufficient performance characteristics to be useful for GlueX. During the beginning of the spring semester, Igor came up with a new design, utilizing more transistors, to provide the high gain, fast response, picosecond resolution amplifier that we needed. The design performed flawlessly both in MatLab simulations and in a handmade single channel prototype. The first of my goals for the spring 2009 semester was to capture the schematic for this new amplifier into Altium designer, and layout a new amplifier board. The second of my goals, of course, was to complete production of the digital control board prototypes.

[[Image:Digital Board, Populated.JPG|thumb|The populated digital board, with a tube of Chap-BlockTM for size comparison.]] Since the fall semester left us with three unpopulated digital control board PCBs, getting those PCBs assembled with their components was the first priority. I began the semester by tracking down all of the components we needed (some of which were selected at the end of the fall semester), and making appropriate substitutions for components whose availability had changed since the fall. In the process of selecting these components, I noticed several places where it seemed like power consumption on the board may be somewhat high. To fix this, I developed a spreadsheet in Microsoft Excel that calculates optimal resistor values to use for to obtain a specified voltage divider stiffness. With this tool, I was able to optimize power consumption across the board, and select appropriate components. Once all components had been selected, ordered, and received, we sent the order out to Screamin’ Circuits for assembly. The boards came back several weeks later, and are currently awaiting testing by some undergraduates who will be in the lab this summer.

While Igor was finalizing his amplifier/summing circuit, I worked briefly on design of the backplane. A number of details regarding trace impedance and board dimensions were ironed out. Nonetheless, many problems still remain which I will need to tackle over the summer. The first of these problems is that we have yet to find an appropriate low cost coaxial connector to route signals off the backplane. In addition, screws with which to mount the backplane to the tagger must be selected so that appropriate holes can be created for them on the PCB.

Once we were satisfied that the amplifier/summing circuit performed as required, I shifted work from the backplane to the amplifier board. Around the same time, I began working on a poster to present my work at the Frontiers in Undergraduate Research Exhibition held during Open House Weekend here at UConn. If you’re interested in my poster, check it out here.

[[Image:Amplifier-Summer-Laid-out.gif|thumb|A prototype layout of 5 amplifier channels and a summing circuit. Actual size is ~1.6" tall. Areas in green represent problems to be resolved over summer 2009. A prototype amplifier with no green spots has been designed and will be replicated to this design soon.]] To start the amplifier/summing circuit project, I searched high and low for information about how to handle multi-channel designs in Altium. Not surprisingly, the first Google result on the query “multichannel design Altium” had everything I was missing during the fall when I was trying to lay out the original amplifier circuit. Using my new knowledge of Altium’s multichannel capabilities, I captured Igor’s new design into the schematics editor of Altium Designer. With proper nested schematic sheets, the entire 30 channel amplifier/6 channel summer design was compressed into just 4 schematic sheets, vs. the ~40 or so that would have been required had I laid out the complete schematics of the old design.

I spent about a week and a half trying to figure out how to handle nesting independent nets from a repeated subsheet into another repeated subsheet which also produces independent nets from the nets of the first sheet. This sounds somewhat complicated, and I suppose perhaps it is a somewhat unique situation, since none of the ~5 sample multichannel projects included with Altium had such a construction in them. Basically, each summing circuit has five amplifier subcircuits, each of which puts out its own signal independent of the other four. From the perspective of the entire board, there are 6 summers, each of which has five independent signals coming from the amplifiers, and one summed signal. Determining how to get Altium to realize the proper connections from each individual amplifier, through that amplifier’s summer, to the main schematic was a complicated mess of naming conventions, but eventually I was able to make Altium reflect all of the appropriate connections in the PCB view. Though there are a few net naming issues still to be resolved, this problem has mostly been ironed out.

The final few weeks of the semester were spent laying out amplifier components in the PCB view of Altium. As of right now, a compact design for an amplifier measuring 0.183”x~1.3” has been completed. Making use of 0201 size components, this amplifier is approximately .2” shorter than the old design, despite incorporating an extra transistor. The amplifier design features an isolating ground trace running the length of the amplifier to prevent crosstalk between channels. A prototype layout of the summing circuit has also been completed, though some layout issues there remain to be resolved over the summer.

===Related Files===
*[http://zeus.phys.uconn.edu/halld/tagger/electronics/design-6-2009/Progress20090505.zip Design Snapshot 5/5/2009]
**Backplane
***Backplane.PrjPcb (Altium Project File)
***Backplane.PcbDoc (Altium PCB File)
***Analog Connector.SchDoc, Digital Connector.SchDoc, LEMO.SchDoc (Altium Schematics)
***Backplane.pdf (SmartPDF File of the schematics and PCB layout)
**Amplifier Board
***Analog Board.PrjPcb (Altium Project File)
***Amplifier Board.PcbDoc (Altium PCB File)
***Main.SchDoc, Amplifier.SchDoc, Summer.SchDoc, Voltage References.SchDoc (Altium Schematics)
***Analog Board.pdf (SmartPDF File of the schematics and PCB layout
****The SmartPDF shows the entire PCB workspace, including components that have not yet been placed on the physical PCB.
****The bottom left corner of the PCB view shows a proof-of-concept 5 amplifiers/1 summer layout.
****Finding AMP6 using the PDF bookmarks shows the prototype amplifier layout that resolves mismatched footprint issues (indicated in green in the image farther up on this page).

== Fall 2009, Current Progress ==
We now have one fully working prototype of the SiPM Digital Control Board, and the SiPM Amplifier Board is currently being manufactured and assembled by Sierra Circuits, Inc. The backplane design is nearly complete and will be going out for quoting within a week.

Here is a zip file containing the most recent versions of the tagger files: [http://zeus.phys.uconn.edu/~underwood/TaggerDocs/TaggerMicroscopeProgress20091112.zip Design Snapshot 11/12/2009]

A few notes about these files:
*There are four subfolders in the zip file. The folders for the three PCBs are clearly labelled. Each PCB folder has one project file (.PrjPcb) which can be opened in Altium Designer. Each project file refers to only one PcbDoc file, making it easy to figure out what you should look at to see the board.
*The SiPM digital control board project has 4 shelved polygons which should be restored (Tools->Polygon Pours->Restore 4 shelved polyons) to see the state of the board as it was last manufactured. Revisions from the testing process have not yet been entered into Altium but can be reviewed on this wiki: [[Digital control board debugging notes]]
*The SiPM amplifier (analog) board project will give an error message that it was unable to find "Test PCB.PcbDoc". Please ignore this. The file was intentionally omitted to prevent confusion, and is not related to the actual design.
*The backplane project will give an error message that it was unable to find "Backplane_New.PcbDoc". Please ignore this. The file was intentionally omitted to prevent confusion, and is not related to the actual design.

Woody Underwood

2009-11-12T15:42:20Z

Underwood: changed bulletting

== About Me ==
My name is Woody Underwood. I'm a junior entering my seventh semester in the physics program at UConn. Since the summer of 2008, I've been working in the lab of Dr. Richard Jones designing electronics for the US Department of Energy's GlueX experiment. My assignment is to develop three circuit boards that work together to tag photons coming from the diamond radiator. My circuitry essentially measures (indirectly) the energy of these photons in order to determine if they are of interest to GlueX. The three boards I am designing consist of a digital board, an analog board, and a connecting backplane.

== About My Circuitry ==
Electrons leaving the diamond radiator are deflected by a magnetic field into an array of scintillating fibres, producing photons. Wave guides carry these photons to SiPMs (silicon photomultipliers) mounted on the analog circuit board. The analog board contains transimpedance amplifiers and summing circuitry to condition the signals for digitization.

The sensitivity of the SiPMs and the gain of the amplifiers on the analog board are controlled both by the power supply VCC and bias voltages supplied from the digital board. The digital board receives commands from a computer via ethernet, and uses a 32-channel DAC to output appropriate bias voltages to the SiPMs on the analog board. The digital and analog boards are connected by means of a backplane, which is also responsible for providing power and grounds to both boards.

== Summary of Fall 2008 Work ==
All circuitry design work was done using Altium Designer. The digital board was the first to be designed. The first step in designing the digital board was to review the list of key components that had already been selected by Igor and Dr. Jones. These components included such things as the Xilinx Spartan-3A FPGA, and the Analog Devices AD5535 DAC. I began by looking through datasheets for these components to find out their needs, including power and decoupling requirements. I reviewed the pinout diagrams, and then looked through Altium’s standard libraries to find components that matched (in many cases the particular component I was looking for was not in the library, but a similar footprint or schematic symbol was). For components without matching schematic symbols, I entered pinout information from the datasheets into Microsoft Excel, using a layout compatible with Altium’s Smart Grid Insert function. Then, I was able to literally copy and paste pin information from Excel into Altium to generate the schematic symbols I needed.

Once I had appropriate schematic symbols available for all parts, I began making appropriate connections in the schematic view in Altium. Though tedious, this task was not exceedingly difficult. I finished the schematics in several days, and then moved on to PCB design. I switched into Altium's PCB view. The footprints corresponding to the components I used in the schematics were automatically inserted by Altium. My job was then to position these components in logical places on the board and make all of the connections corresponding to the nets defined in the schematics.

Due to the large number of components being placed in the limited space available on the digital board, Altium's auto-router proved completely useless. Therefore, I routed the board manually. Despite Altium's revolutionary convergence of schematic and PCB design into a single program, this was no easy task. During the routing process, I had to take into account not only the connections that had to be made, but also things such as avoiding crosstalk and minimizing trace length for sensitive components. I was able to complete routing after several weeks of work. The digital board design has since been completed and the board has been printed. It is currently awaiting assembly.

The analog board provided a host of new challenges. The basic schematic for the transimpedance amplifier on the analog board was completed by Igor and Dr. Jones before the semester. Inputting the schematic into Altium was not very difficult. However, one problem I encountered was that the analog board contains 32 copies of this amplifier circuitry. After failing to find any way to insert multiple copies of both the schematic and its corresponding PCB layout, I decided to insert only single copies of each schematic page, and copy and paste the PCB layout to produce 32 copies of the amplifier circuitry. At first this seemed like a quick and easy way to get all of the necessary circuitry onto the PCB. However, I eventually discovered that this procedure would lead to major problems with the board assembly process (due to duplicate component designators, and for other reasons). Fortunately, this revelation came around the same time that Igor and Dr. Jones found a problem with the performance of the amplifier circuit. Making any changes to the amplifier circuit at this point will require a major reroute of all the traces on the analog board. Since the board needs to be completely redesigned anyway, this will give me another chance to find a way to match schematics with all 32 copies of the amplifier circuitry.

The backplane design is currently in progress. It should be relatively easy to complete. All that remains to be done is to add the LEMO connectors and power inputs. The board is simple enough that it can be routed completely by the auto-router, though a quick hand routing will probably be superior. I anticipate that I can complete the backplane with a few days of concentrated work over break.

Included below are links to the files I have been working on. Included in the files for each board is a "SmartPDF," viewable in Adobe Reader. For those without Altium Designer, these may be the best files to look at. They include complete schematics and PCB layout, and are also indexed by component.

Any questions about the tagger circuitry can be directed to me at [mailto:mitchell.underwood@uconn.edu mitchell.underwood@uconn.edu]

=== Related Files ===
* [http://zeus.phys.uconn.edu/halld/tagger/electronics/design-12-2008/DigitalBoard.zip DigitalBoard.zip]:
**Altium Project File (SiPM Control Board.PrjPcb)
**Altium PCB Layout File (Prototype1.PcbDoc)
**Altium Schematic Files (*.SchDoc)
**Altium Annotation Document (SiPM Control Board.Annotation)
***Not used, but generated by Altium when opening the project
**Altium PRJPCBSTRUCTURE File (SiPM Control Board.PRJPCBSTRUCTURE)
***Not used, but generated by Altium when opening the project)
**“SmartPDF” of the board and schematics (SiPM Control Board.pdf)
***Can be used to explore the PCB layout and schematics without needing Altium
**Pick and Place File for board population (Pick Place for Prototype1.txt)
***Used by board assembler
**NC Drill Files (Prototype1.txt, Prototype1.DRR, Prototype1.DRL)
***Used by board printer
**Gerber Files for all layers (in folder Gerbers)
***Used by board printer
**Altium CAMtastic file (CAMtastic4 FINAL.Cam)
***Basically a composite of all the Gerbers
**Photos and 3D rendering of populated board
***In folder “Photos”
**EMF Files showing different layers
***In folder “EMF Renderings”
**AutoCad File of PCB (Prototype1 Autocad.DWG)
**Altium Library of Custom Footprints for Digital Board (GlueX IC Library.SchLib)
***Current as of completion of digital board
***This library has since been updated for the backplane

*[http://zeus.phys.uconn.edu/halld/tagger/electronics/design-12-2008/Analog%20Board%2020081211.zip Analog Board 20081211.zip]:
**Altium Project File (AnalogBoard.PrjPcb)
**Altium PCB Layout File (AnalogBoardPCB.PcbDoc)
**Altium Schematic Files (Amplifer1.SchDoc, Summer.SchDoc)
**“SmartPDF” of the board and schematics (AnalogBoard.pdf)
**Altium Component Definition for SiPM (SiPM Library.PcbLib)
***Contains part footprint and pin information for the SiPM component

*[http://zeus.phys.uconn.edu/halld/tagger/electronics/design-12-2008/Backplane%2020081211.zip Backplane 20081211.zip]
**Altium Project File (Backplane.PrjPcb)
**Alitum PCB Layout File (Backplane.PcbDoc)
**Altium Schematic Files (Analog Connector.SchDoc, Digital Connector.SchDoc)
***Analog Connector = Eurocard to analog board
***Digital Connector = Eurocard to digital board, +3.3V voltage regulator, and location identifier jumper
***LEMO connections not yet included in these schematics
**“SmartPDF” of the board and schematics (Backplane.pdf)
**Pin layout files used to define pinouts for custom components (Pin Layout, 96 pin connector.xlsx, Pinouts.xlsx)
***Pin Layout, 96 pin connector = pinout definition for 96 pin Eurocard connector
***Pinouts.xlsx = pinout definitions for digital board, which were reused for the 48 pin digital Eurocard receptacle on backplane
**Altium Library of Custom Components (GlueX IC Library.SchLib)
***UPDATED to include new backplane components
***An older version of this library was used for the digital board

==Summary of Spring 2009 Work==

At the end of the fall semester, Dr. Jones, Igor, and I determined that the amplifier/summing circuit we had designed simply didn’t have sufficient performance characteristics to be useful for GlueX. During the beginning of the spring semester, Igor came up with a new design, utilizing more transistors, to provide the high gain, fast response, picosecond resolution amplifier that we needed. The design performed flawlessly both in MatLab simulations and in a handmade single channel prototype. The first of my goals for the spring 2009 semester was to capture the schematic for this new amplifier into Altium designer, and layout a new amplifier board. The second of my goals, of course, was to complete production of the digital control board prototypes.

[[Image:Digital Board, Populated.JPG|thumb|The populated digital board, with a tube of Chap-BlockTM for size comparison.]] Since the fall semester left us with three unpopulated digital control board PCBs, getting those PCBs assembled with their components was the first priority. I began the semester by tracking down all of the components we needed (some of which were selected at the end of the fall semester), and making appropriate substitutions for components whose availability had changed since the fall. In the process of selecting these components, I noticed several places where it seemed like power consumption on the board may be somewhat high. To fix this, I developed a spreadsheet in Microsoft Excel that calculates optimal resistor values to use for to obtain a specified voltage divider stiffness. With this tool, I was able to optimize power consumption across the board, and select appropriate components. Once all components had been selected, ordered, and received, we sent the order out to Screamin’ Circuits for assembly. The boards came back several weeks later, and are currently awaiting testing by some undergraduates who will be in the lab this summer.

While Igor was finalizing his amplifier/summing circuit, I worked briefly on design of the backplane. A number of details regarding trace impedance and board dimensions were ironed out. Nonetheless, many problems still remain which I will need to tackle over the summer. The first of these problems is that we have yet to find an appropriate low cost coaxial connector to route signals off the backplane. In addition, screws with which to mount the backplane to the tagger must be selected so that appropriate holes can be created for them on the PCB.

Once we were satisfied that the amplifier/summing circuit performed as required, I shifted work from the backplane to the amplifier board. Around the same time, I began working on a poster to present my work at the Frontiers in Undergraduate Research Exhibition held during Open House Weekend here at UConn. If you’re interested in my poster, check it out here.

[[Image:Amplifier-Summer-Laid-out.gif|thumb|A prototype layout of 5 amplifier channels and a summing circuit. Actual size is ~1.6" tall. Areas in green represent problems to be resolved over summer 2009. A prototype amplifier with no green spots has been designed and will be replicated to this design soon.]] To start the amplifier/summing circuit project, I searched high and low for information about how to handle multi-channel designs in Altium. Not surprisingly, the first Google result on the query “multichannel design Altium” had everything I was missing during the fall when I was trying to lay out the original amplifier circuit. Using my new knowledge of Altium’s multichannel capabilities, I captured Igor’s new design into the schematics editor of Altium Designer. With proper nested schematic sheets, the entire 30 channel amplifier/6 channel summer design was compressed into just 4 schematic sheets, vs. the ~40 or so that would have been required had I laid out the complete schematics of the old design.

I spent about a week and a half trying to figure out how to handle nesting independent nets from a repeated subsheet into another repeated subsheet which also produces independent nets from the nets of the first sheet. This sounds somewhat complicated, and I suppose perhaps it is a somewhat unique situation, since none of the ~5 sample multichannel projects included with Altium had such a construction in them. Basically, each summing circuit has five amplifier subcircuits, each of which puts out its own signal independent of the other four. From the perspective of the entire board, there are 6 summers, each of which has five independent signals coming from the amplifiers, and one summed signal. Determining how to get Altium to realize the proper connections from each individual amplifier, through that amplifier’s summer, to the main schematic was a complicated mess of naming conventions, but eventually I was able to make Altium reflect all of the appropriate connections in the PCB view. Though there are a few net naming issues still to be resolved, this problem has mostly been ironed out.

The final few weeks of the semester were spent laying out amplifier components in the PCB view of Altium. As of right now, a compact design for an amplifier measuring 0.183”x~1.3” has been completed. Making use of 0201 size components, this amplifier is approximately .2” shorter than the old design, despite incorporating an extra transistor. The amplifier design features an isolating ground trace running the length of the amplifier to prevent crosstalk between channels. A prototype layout of the summing circuit has also been completed, though some layout issues there remain to be resolved over the summer.

===Related Files===
*[http://zeus.phys.uconn.edu/halld/tagger/electronics/design-6-2009/Progress20090505.zip Design Snapshot 5/5/2009]
**Backplane
***Backplane.PrjPcb (Altium Project File)
***Backplane.PcbDoc (Altium PCB File)
***Analog Connector.SchDoc, Digital Connector.SchDoc, LEMO.SchDoc (Altium Schematics)
***Backplane.pdf (SmartPDF File of the schematics and PCB layout)
**Amplifier Board
***Analog Board.PrjPcb (Altium Project File)
***Amplifier Board.PcbDoc (Altium PCB File)
***Main.SchDoc, Amplifier.SchDoc, Summer.SchDoc, Voltage References.SchDoc (Altium Schematics)
***Analog Board.pdf (SmartPDF File of the schematics and PCB layout
****The SmartPDF shows the entire PCB workspace, including components that have not yet been placed on the physical PCB.
****The bottom left corner of the PCB view shows a proof-of-concept 5 amplifiers/1 summer layout.
****Finding AMP6 using the PDF bookmarks shows the prototype amplifier layout that resolves mismatched footprint issues (indicated in green in the image farther up on this page).

== Fall 2009, Current Progress ==
We now have one fully working prototype of the SiPM Digital Control Board, and the SiPM Amplifier Board is currently being manufactured and assembled by Sierra Circuits, Inc. The backplane design is nearly complete and will be going out for quoting within a week.

Here is a zip file containing the most recent versions of the tagger files: [http://zeus.phys.uconn.edu/~underwood/TaggerDocs/TaggerMicroscopeProgress20091112.zip Design Snapshot 11/12/2009]

A few notes about these files:
*There are four subfolders in the zip file. The folders for the three PCBs are clearly labelled. Each PCB folder has one project file (.PrjPcb) which can be opened in Altium Designer. Each project file refers to only one PcbDoc file, making it easy to figure out what you should look at to see the board.
*The SiPM digital control board project has 4 shelved polygons which should be restored (Tools->Polygon Pours->Restore 4 shelved polyons) to see the state of the board as it was last manufactured. Revisions from the testing process have not yet been entered into Altium but can be reviewed on this wiki.
*The SiPM amplifier (analog) board project will give an error message that it was unable to find "Test PCB.PcbDoc". Please ignore this. The file was intentionally omitted to prevent confusion, and is not related to the actual design.
*The backplane project will give an error message that it was unable to find "Backplane_New.PcbDoc". Please ignore this. The file was intentionally omitted to prevent confusion, and is not related to the actual design.

Woody Underwood

2009-11-12T15:40:26Z

Underwood: Added fall 2009 current progress

== About Me ==
My name is Woody Underwood. I'm a junior entering my seventh semester in the physics program at UConn. Since the summer of 2008, I've been working in the lab of Dr. Richard Jones designing electronics for the US Department of Energy's GlueX experiment. My assignment is to develop three circuit boards that work together to tag photons coming from the diamond radiator. My circuitry essentially measures (indirectly) the energy of these photons in order to determine if they are of interest to GlueX. The three boards I am designing consist of a digital board, an analog board, and a connecting backplane.

== About My Circuitry ==
Electrons leaving the diamond radiator are deflected by a magnetic field into an array of scintillating fibres, producing photons. Wave guides carry these photons to SiPMs (silicon photomultipliers) mounted on the analog circuit board. The analog board contains transimpedance amplifiers and summing circuitry to condition the signals for digitization.

The sensitivity of the SiPMs and the gain of the amplifiers on the analog board are controlled both by the power supply VCC and bias voltages supplied from the digital board. The digital board receives commands from a computer via ethernet, and uses a 32-channel DAC to output appropriate bias voltages to the SiPMs on the analog board. The digital and analog boards are connected by means of a backplane, which is also responsible for providing power and grounds to both boards.

== Summary of Fall 2008 Work ==
All circuitry design work was done using Altium Designer. The digital board was the first to be designed. The first step in designing the digital board was to review the list of key components that had already been selected by Igor and Dr. Jones. These components included such things as the Xilinx Spartan-3A FPGA, and the Analog Devices AD5535 DAC. I began by looking through datasheets for these components to find out their needs, including power and decoupling requirements. I reviewed the pinout diagrams, and then looked through Altium’s standard libraries to find components that matched (in many cases the particular component I was looking for was not in the library, but a similar footprint or schematic symbol was). For components without matching schematic symbols, I entered pinout information from the datasheets into Microsoft Excel, using a layout compatible with Altium’s Smart Grid Insert function. Then, I was able to literally copy and paste pin information from Excel into Altium to generate the schematic symbols I needed.

Once I had appropriate schematic symbols available for all parts, I began making appropriate connections in the schematic view in Altium. Though tedious, this task was not exceedingly difficult. I finished the schematics in several days, and then moved on to PCB design. I switched into Altium's PCB view. The footprints corresponding to the components I used in the schematics were automatically inserted by Altium. My job was then to position these components in logical places on the board and make all of the connections corresponding to the nets defined in the schematics.

Due to the large number of components being placed in the limited space available on the digital board, Altium's auto-router proved completely useless. Therefore, I routed the board manually. Despite Altium's revolutionary convergence of schematic and PCB design into a single program, this was no easy task. During the routing process, I had to take into account not only the connections that had to be made, but also things such as avoiding crosstalk and minimizing trace length for sensitive components. I was able to complete routing after several weeks of work. The digital board design has since been completed and the board has been printed. It is currently awaiting assembly.

The analog board provided a host of new challenges. The basic schematic for the transimpedance amplifier on the analog board was completed by Igor and Dr. Jones before the semester. Inputting the schematic into Altium was not very difficult. However, one problem I encountered was that the analog board contains 32 copies of this amplifier circuitry. After failing to find any way to insert multiple copies of both the schematic and its corresponding PCB layout, I decided to insert only single copies of each schematic page, and copy and paste the PCB layout to produce 32 copies of the amplifier circuitry. At first this seemed like a quick and easy way to get all of the necessary circuitry onto the PCB. However, I eventually discovered that this procedure would lead to major problems with the board assembly process (due to duplicate component designators, and for other reasons). Fortunately, this revelation came around the same time that Igor and Dr. Jones found a problem with the performance of the amplifier circuit. Making any changes to the amplifier circuit at this point will require a major reroute of all the traces on the analog board. Since the board needs to be completely redesigned anyway, this will give me another chance to find a way to match schematics with all 32 copies of the amplifier circuitry.

The backplane design is currently in progress. It should be relatively easy to complete. All that remains to be done is to add the LEMO connectors and power inputs. The board is simple enough that it can be routed completely by the auto-router, though a quick hand routing will probably be superior. I anticipate that I can complete the backplane with a few days of concentrated work over break.

Included below are links to the files I have been working on. Included in the files for each board is a "SmartPDF," viewable in Adobe Reader. For those without Altium Designer, these may be the best files to look at. They include complete schematics and PCB layout, and are also indexed by component.

Any questions about the tagger circuitry can be directed to me at [mailto:mitchell.underwood@uconn.edu mitchell.underwood@uconn.edu]

=== Related Files ===
* [http://zeus.phys.uconn.edu/halld/tagger/electronics/design-12-2008/DigitalBoard.zip DigitalBoard.zip]:
**Altium Project File (SiPM Control Board.PrjPcb)
**Altium PCB Layout File (Prototype1.PcbDoc)
**Altium Schematic Files (*.SchDoc)
**Altium Annotation Document (SiPM Control Board.Annotation)
***Not used, but generated by Altium when opening the project
**Altium PRJPCBSTRUCTURE File (SiPM Control Board.PRJPCBSTRUCTURE)
***Not used, but generated by Altium when opening the project)
**“SmartPDF” of the board and schematics (SiPM Control Board.pdf)
***Can be used to explore the PCB layout and schematics without needing Altium
**Pick and Place File for board population (Pick Place for Prototype1.txt)
***Used by board assembler
**NC Drill Files (Prototype1.txt, Prototype1.DRR, Prototype1.DRL)
***Used by board printer
**Gerber Files for all layers (in folder Gerbers)
***Used by board printer
**Altium CAMtastic file (CAMtastic4 FINAL.Cam)
***Basically a composite of all the Gerbers
**Photos and 3D rendering of populated board
***In folder “Photos”
**EMF Files showing different layers
***In folder “EMF Renderings”
**AutoCad File of PCB (Prototype1 Autocad.DWG)
**Altium Library of Custom Footprints for Digital Board (GlueX IC Library.SchLib)
***Current as of completion of digital board
***This library has since been updated for the backplane

*[http://zeus.phys.uconn.edu/halld/tagger/electronics/design-12-2008/Analog%20Board%2020081211.zip Analog Board 20081211.zip]:
**Altium Project File (AnalogBoard.PrjPcb)
**Altium PCB Layout File (AnalogBoardPCB.PcbDoc)
**Altium Schematic Files (Amplifer1.SchDoc, Summer.SchDoc)
**“SmartPDF” of the board and schematics (AnalogBoard.pdf)
**Altium Component Definition for SiPM (SiPM Library.PcbLib)
***Contains part footprint and pin information for the SiPM component

*[http://zeus.phys.uconn.edu/halld/tagger/electronics/design-12-2008/Backplane%2020081211.zip Backplane 20081211.zip]
**Altium Project File (Backplane.PrjPcb)
**Alitum PCB Layout File (Backplane.PcbDoc)
**Altium Schematic Files (Analog Connector.SchDoc, Digital Connector.SchDoc)
***Analog Connector = Eurocard to analog board
***Digital Connector = Eurocard to digital board, +3.3V voltage regulator, and location identifier jumper
***LEMO connections not yet included in these schematics
**“SmartPDF” of the board and schematics (Backplane.pdf)
**Pin layout files used to define pinouts for custom components (Pin Layout, 96 pin connector.xlsx, Pinouts.xlsx)
***Pin Layout, 96 pin connector = pinout definition for 96 pin Eurocard connector
***Pinouts.xlsx = pinout definitions for digital board, which were reused for the 48 pin digital Eurocard receptacle on backplane
**Altium Library of Custom Components (GlueX IC Library.SchLib)
***UPDATED to include new backplane components
***An older version of this library was used for the digital board

==Summary of Spring 2009 Work==

At the end of the fall semester, Dr. Jones, Igor, and I determined that the amplifier/summing circuit we had designed simply didn’t have sufficient performance characteristics to be useful for GlueX. During the beginning of the spring semester, Igor came up with a new design, utilizing more transistors, to provide the high gain, fast response, picosecond resolution amplifier that we needed. The design performed flawlessly both in MatLab simulations and in a handmade single channel prototype. The first of my goals for the spring 2009 semester was to capture the schematic for this new amplifier into Altium designer, and layout a new amplifier board. The second of my goals, of course, was to complete production of the digital control board prototypes.

[[Image:Digital Board, Populated.JPG|thumb|The populated digital board, with a tube of Chap-BlockTM for size comparison.]] Since the fall semester left us with three unpopulated digital control board PCBs, getting those PCBs assembled with their components was the first priority. I began the semester by tracking down all of the components we needed (some of which were selected at the end of the fall semester), and making appropriate substitutions for components whose availability had changed since the fall. In the process of selecting these components, I noticed several places where it seemed like power consumption on the board may be somewhat high. To fix this, I developed a spreadsheet in Microsoft Excel that calculates optimal resistor values to use for to obtain a specified voltage divider stiffness. With this tool, I was able to optimize power consumption across the board, and select appropriate components. Once all components had been selected, ordered, and received, we sent the order out to Screamin’ Circuits for assembly. The boards came back several weeks later, and are currently awaiting testing by some undergraduates who will be in the lab this summer.

While Igor was finalizing his amplifier/summing circuit, I worked briefly on design of the backplane. A number of details regarding trace impedance and board dimensions were ironed out. Nonetheless, many problems still remain which I will need to tackle over the summer. The first of these problems is that we have yet to find an appropriate low cost coaxial connector to route signals off the backplane. In addition, screws with which to mount the backplane to the tagger must be selected so that appropriate holes can be created for them on the PCB.

Once we were satisfied that the amplifier/summing circuit performed as required, I shifted work from the backplane to the amplifier board. Around the same time, I began working on a poster to present my work at the Frontiers in Undergraduate Research Exhibition held during Open House Weekend here at UConn. If you’re interested in my poster, check it out here.

[[Image:Amplifier-Summer-Laid-out.gif|thumb|A prototype layout of 5 amplifier channels and a summing circuit. Actual size is ~1.6" tall. Areas in green represent problems to be resolved over summer 2009. A prototype amplifier with no green spots has been designed and will be replicated to this design soon.]] To start the amplifier/summing circuit project, I searched high and low for information about how to handle multi-channel designs in Altium. Not surprisingly, the first Google result on the query “multichannel design Altium” had everything I was missing during the fall when I was trying to lay out the original amplifier circuit. Using my new knowledge of Altium’s multichannel capabilities, I captured Igor’s new design into the schematics editor of Altium Designer. With proper nested schematic sheets, the entire 30 channel amplifier/6 channel summer design was compressed into just 4 schematic sheets, vs. the ~40 or so that would have been required had I laid out the complete schematics of the old design.

I spent about a week and a half trying to figure out how to handle nesting independent nets from a repeated subsheet into another repeated subsheet which also produces independent nets from the nets of the first sheet. This sounds somewhat complicated, and I suppose perhaps it is a somewhat unique situation, since none of the ~5 sample multichannel projects included with Altium had such a construction in them. Basically, each summing circuit has five amplifier subcircuits, each of which puts out its own signal independent of the other four. From the perspective of the entire board, there are 6 summers, each of which has five independent signals coming from the amplifiers, and one summed signal. Determining how to get Altium to realize the proper connections from each individual amplifier, through that amplifier’s summer, to the main schematic was a complicated mess of naming conventions, but eventually I was able to make Altium reflect all of the appropriate connections in the PCB view. Though there are a few net naming issues still to be resolved, this problem has mostly been ironed out.

The final few weeks of the semester were spent laying out amplifier components in the PCB view of Altium. As of right now, a compact design for an amplifier measuring 0.183”x~1.3” has been completed. Making use of 0201 size components, this amplifier is approximately .2” shorter than the old design, despite incorporating an extra transistor. The amplifier design features an isolating ground trace running the length of the amplifier to prevent crosstalk between channels. A prototype layout of the summing circuit has also been completed, though some layout issues there remain to be resolved over the summer.

===Related Files===
*[http://zeus.phys.uconn.edu/halld/tagger/electronics/design-6-2009/Progress20090505.zip Design Snapshot 5/5/2009]
**Backplane
***Backplane.PrjPcb (Altium Project File)
***Backplane.PcbDoc (Altium PCB File)
***Analog Connector.SchDoc, Digital Connector.SchDoc, LEMO.SchDoc (Altium Schematics)
***Backplane.pdf (SmartPDF File of the schematics and PCB layout)
**Amplifier Board
***Analog Board.PrjPcb (Altium Project File)
***Amplifier Board.PcbDoc (Altium PCB File)
***Main.SchDoc, Amplifier.SchDoc, Summer.SchDoc, Voltage References.SchDoc (Altium Schematics)
***Analog Board.pdf (SmartPDF File of the schematics and PCB layout
****The SmartPDF shows the entire PCB workspace, including components that have not yet been placed on the physical PCB.
****The bottom left corner of the PCB view shows a proof-of-concept 5 amplifiers/1 summer layout.
****Finding AMP6 using the PDF bookmarks shows the prototype amplifier layout that resolves mismatched footprint issues (indicated in green in the image farther up on this page).

== Fall 2009, Current Progress ==
We now have one fully working prototype of the SiPM Digital Control Board, and the SiPM Amplifier Board is currently being manufactured and assembled by Sierra Circuits, Inc. The backplane design is nearly complete and will be going out for quoting within a week.

Here is a zip file containing the most recent versions of the tagger files: [http://zeus.phys.uconn.edu/~underwood/TaggerDocs/TaggerMicroscopeProgress20091112.zip Design Snapshot 11/12/2009]

A few notes about these files:
*There are four subfolders in the zip file. The folders for the three PCBs are clearly labelled. Each PCB folder has one project file (.PrjPcb) which can be opened in Altium Designer. Each project file refers to only one PcbDoc file, making it easy to figure out what you should look at to see the board.
**The SiPM digital control board project has 4 shelved polygons which should be restored (Tools->Polygon Pours->Restore 4 shelved polyons) to see the state of the board as it was last manufactured. Revisions from the testing process have not yet been entered into Altium but can be reviewed on this wiki.
**The SiPM amplifier (analog) board project will give an error message that it was unable to find "Test PCB.PcbDoc". Please ignore this. The file was intentionally omitted to prevent confusion, and is not related to the actual design.
**The backplane project will give an error message that it was unable to find "Backplane_New.PcbDoc". Please ignore this. The file was intentionally omitted to prevent confusion, and is not related to the actual design.

SiPM digital control board supporting components

2009-11-05T15:16:03Z

Underwood: /* LED-less RJ-45 Jack */

== Overview ==

While the FPGA, Ethernet controller, DAC, ADC and Temperature sensor are considered the main components of the SiPM digital control board, there are also many other supporting components that will be on the board. This page discusses many of the other minor components on the SiPM digital control board.

== Multipurpose Supporting Components ==

This section discusses components that function to support two or more of the major components on the control board.

=== 20MHz Crystal Oscillator ===

The SiPM digital control board is driven by a 20MHz clock generated from a crystal oscillator. This signal will be divided into a 5MHz signal by the FPGA for some components, but nonetheless, the 20MHz clock is the main timing signal on the board. The component most sensitive to this signal is the CP2201 Ethernet IC, so the oscillator will be selected to meet the requirements of this chip. According to the [http://www.silabs.com/public/documents/tpub_doc/dsheet/Microcontrollers/Interface/en/CP2200.pdf CP2201 data sheet], the CP2201 requires a 20MHz signal with an error of no more than ±50ppm. One crystal oscillator that meets the requirements of the CP2201 is the Epson Toyocom MA-505 20.0000M-C0 ([http://search.digikey.com/scripts/DkSearch/dksus.dll?Detail?name=SE2509CT-ND Digi-Key Part #SE2509CT-ND]). There are also many other similar oscillators available if the Epson Toyocom model proves insufficient.

== FPGA Supporting Components ==

=== XCF01S EEPROM ===

[[Image:SiPM FPGA and EEPROM Connections.gif|thumb|Connection diagram for XCF01S and Spartan-3A FPGA taken from [http://www.xilinx.com/support/documentation/data_sheets/ds123.pdf XCF01S specifications sheet].]]
The Xilinx XCF01S EEPROM is responsible for configuring the FPGA when the system is turned on or reset. We selected the XCF01S because it is recommended by Xilinx as the best solution for programming the Spartan-3A FPGA used on the control board. The XCF01S is ideal because it has sufficient memory to hold the entire FPGA program, and also minimizes the number of FPGA-to-EEPROM leads necessary for programming the FPGA. For more information on the mode of programming the FPGA, see [[FPGA programming modes]].

Both the EEPROM and the FPGA are designed to tolerate +3.3V CMOS logic levels, keeping the configuration logic at the same voltages as the other logic on the board.

=== Post-Configuration EEPROM Isolating Logic ===

Originally it was though that it may be necessary to introduce OR gates and NOR gates (with the FPGA's DONE pin) to keep EEPROM pins at the necessary logic values after programming is complete, if the configuration pins on the FPGA were to be reused as user I/O pins following configuration. However, the specifications sheet for the XCF01S says that when CE is held high, the D0 pin goes into a high impedance state. We believe this is sufficient to prevent unwanted EEPROM I/O operations due to changing logic levels on its pins following configuration, meaning post-configuration EEPROM isolating logic is not necessary. In addition, due to the large number of available I/O pins on the FPGA, there are sufficient dedicated I/O pins available so that these shared pins do not need to be reused in our design.

=== FPGA/EEPROM Pull-up Resistors ===

Despite being shown in the [[:Image:SiPM FPGA and EEPROM Connections.gif |connection diagram]], 4.7kΩ pull-up resistors are not necessary to pull up the DONE, INIT_B and PROG_B pins to VCCO, since we will be enabling internal pull-ups using the PUDC_B pin.

== CP2201 Ethernet Supporting Components ==

=== LED-less RJ-45 Jack ===

Since we want to keep the enclosure as dark as possible, we must use an Ethernet jack with no built-in activity/link LED. There are many suitable jacks available. The jack we have selected to use on the board is the Pulse Engineering J0012D21.

Digital control board debugging notes

2009-11-05T15:12:04Z

Underwood: /* Incorrect footprint for the Ethernet Jack used */ added info about part numbers

This page contains a list of all currently known problems with the digital control board.

= Problems =

== No Power on +1.2V Power Island ==
=== Description ===
The +1.2V island was found to be at 0.0V rather than +1.2V.

=== Cause ===
The +5V input (pin 2) on the +1.2V voltage regulator, VR3 (Analog Devices ADP1715), was not connected.

=== Solution ===
A dab of solder was used to short pins 1 and 2 on VR3. Pin 1 is an active high chip enable pin, which is permanently tied to +5V.

=== Other Details and Current Status ===
This problem was due to an unconnected pin in the original schematics. The schematics have '''not yet been updated''' to reflect the solution.

* June 22, 2009: One board has been modified to correct this problem.

== SPI Bus Miswired ==
=== Description ===
The SPI bus to the temperature sensor and the ADC is not wired correctly.

=== Cause ===
FPGA pin 5 (labelled SPI) is connected to DIN on the ADC, and DOUT of the temperature sensor. FPGA pin 97 (labelled AD7928/DOUT) is connected to DOUT on the ADC. SPI designates that all slave device DOUT traces be connected together. Chip select and HiZ logic are used to prevent devices from fighting over the signal line.

=== Solution ===
Pin 5 on the temperature sensor should be connected to pin 18 on the ADC and pin 97 on the FPGA. This can be accomplished by cutting the existing DOUT trace near the temperature sensor and soldering a wire to DOUT on the ADC. In this configuration, pin 5 on the FPGA will become the SPI MOSI (master out, slave in) line, and pin 97 on the FPGA will become the SPI MISO (master in, slave out) line. DIN on the temperature sensor is left tied to ground, since it is not needed.

=== Other Details and Current Status ===
This problem was due to errors int he original schematics. The schematics have '''not yet been updated''' to reflect the solution.

This modification has been implemented.

== Incorrect Oscillator ==
=== Description ===
The oscillator used was a standard crystal oscillator, however the FPGA requires an oscillator with a CMOS square wave input.

=== Solution ===
The crystal oscillator was replaced with a FOX FXO-HC53 HCMOS oscillator running at 20 Mhz. The output from the oscillator was connected to pin 27 on the FPGA. The load of having both the oscillator and the Ethernet controller connected to the output of the oscillator was to large. The clock input for the Ethernet controller Pin 28 was connected to pin 37 of the FPGA.
Schematic:[[Image:osc.png]]

=== Other Details and Current Status ===
The schematics have '''not yet been updated''' to reflect the solution.

This modification has been implemented.

== Wrong polarity of Zener Diode on -5V ==
=== Description ===
Zener diode D2 is reversed in the layout. It is correct in the schematics.

=== Solution ===
The diode was rotated on all the prototyping boards. This indication has '''not yet been entered into the layout'''.

=== Other Details and Current Status ===
This problem may be related to the overload on the -5V circuitry for of the DAC.

== Mismatched JTAG programming header ==
=== Description ===
The connector of the "Xilinx Platform USB II" kit seems to be a reduced size compared to the standard 0.1" spaced pin header with which the board is equipped.

=== Solution ===
For the testing stage, the flying lead connector is sufficient to bypass this problem. The layout must be corrected to the matching header (type?). Change entered already?

== Ethernet jack pinout mismatch ==

The wrong Ethernet jack was attached to the PCB, leading to a pinout mismatch. The part ordered was the Pulse J001'''1'''D21. The correct part is J001'''2'''D21. The correct part was ordered and soldered onto the prototype boards, but this change must be made in the Altium parts list.

= Suggested/Preferred Changes =

* <code>R12</code>, the pull-up resistor for the reset pins (header 2) is unnecessary, as the FPGA pin can be programmed to pull up.

Digital control board documentation

2009-07-23T16:02:39Z

Underwood: /* Channel Mapping */ fixed DACHEALTH problem

This documentation covers the most important things to know while testing the digital control board, including component pinouts, nets, and other information.

== Power Requirements ==
=== Required Voltages ===
All components on the digital board '''except the DAC''' can be tested using only a +5V source. The DAC requires +5V, -5V, and a high voltage corresponding to 10V higher than the maximum desired DAC output voltage (see [[#Setting the Output Range | Setting the Output Range]]). Digital and analog grounds must be connected as well before any testing takes place.

=== Power Pins ===
Power shall be connected to the board as follows:
{| cellpadding=3 border=1 |
| '''Voltage'''
| '''Eurocard Pin'''
|-
| DGND
| A6
|-
| AGND
| A5
|-
| +5V
| A4
|-
| -5V
| A3
|-
| High voltage (DAC max out +10)
| A2
|}

=== Power Supply Sequencing ===
The control board is designed such that voltages may be supplied in any order so long as AGND and DGND are connected properly. However, for initial testing, the preferred order for powering up the board is as follows:

# Ensure AGND/DGND are connected/grounded
# +5V
# -5V
# High voltage

== FPGA ==
The control board uses a Xilinx XC3S50A VQ100 FPGA. It has a 100 pin footprint and is located in the center of the control board.

=== Power Details ===
The FPGA is powered by the 3.3V power plane, which is regulated by VR1. The FPGA also obtains 1.2V for its internal logic from a 1.2V power island, regulated by VR3.

=== Logic Standard ===
The Xilinx XC3S50A supports several different digital logic standards. The control board is hard wired such that the FPGA will use a '''3.3V CMOS''' logic standard.

=== Pinout Table ===
{| cellpadding=3 border=1 |
| '''Pin #''' || '''Net Name''' || '''Signal Name'''
| '''Description'''
|-
| P1 || FPGA/TMS || [JTAG]
| JTAG
|-
| P2 || FPGA/TDI || [JTAG]
| JTAG
|-
| P3 || AD7928/CS || SPI_A_iCS
| SPI chip select for ADC
|-
| P4 || SPI || SPI_SDO
| '''Erroneously wired SPI bus trace''' Now connects to SDO on temp. sensor and on ADC
|-
| P5 || CLK_5MHZ || SPI_SCLK
| 5 MHz clock output for SPI bus (ADC and temp. sensor)
|-
| P6 || No connection ||
|
|-
| P7 || No connection ||
|
|-
| P8 || DGND ||
|
|-
| P9 || No connection ||
|
|-
| P10 || No connection ||
|
|-
| P11 || +3.3V ||
|
|-
| P12 || No connection ||
|
|-
| P13 || No connection ||
|
|-
| P14 || DGND ||
|
|-
| P15 || No connection ||
|
|-
| P16 || No connection ||
|
|-
| P17 || +1.2V ||
|
|-
| P18 || DGND ||
|
|-
| P19 || dBinfo_Start ||
|
|-
| P20 || dBinfo_Stream ||
|
|-
| P21 || No connection ||
|
|-
| P22 || +3.3V ||
|
|-
| P23 || DGND || [M1: JTAG prog. config.]
|
|-
| P24 || DGND || [M2: JTAG prog. config.]
|
|-
| P25 || DGND || [M0: JTAG prog. config.]
|
|-
| P26 || +3.3V ||
|
|-
| P27 || FPGA/CLK_IN || fClk
| 20 MHz clock input from crystal oscillator
|-
| P28 || No connection ||
|
|-
| P29 || No connection || (db) state_Q(0)
|
|-
| P30 || No connection ||
|
|-
| P31 || No connection || (db) state_Q(1)
|
|-
| P32 || No connection ||
|
|-
| P33 || No connection || (db) state_Q(2)
|
|-
| P34 || No connection ||
|
|-
| P35 || CP2201/INT || Eth_iINT
| Ethernet controller interrupt
|-
| P36 || MASTER_RESET || Rst
| Connects to RESET jumper in upper left of board (active-low, externally pulled up)
|-
| P37 || (manually wired) || fClk_out
|
|-
| P38 || +1.2V ||
|
|-
| P39 || No connection ||
|
|-
| P40 || CP2201/CS || iCS
| Chip select for ethernet controller
|-
| P41 || CP2201/WR || iWR
| Write enable for ethernet controller
|-
| P42 || DGND ||
|
|-
| P43 || CP2201/RD || iRD
| Read enable for ethernet controller
|-
| P44 || CP2201/ALE || ALE
| Address line enable for ethernet controller
|-
| P45 || +3.3V ||
|
|-
| P46 || CP2201/RESET || Eth_iRst
| Reset pin for ethernet controller
|-
| P47 || DGND ||
|
|-
| P48 || FPGA/INIT_B || [JTAG]
| Used during FPGA configuration - see Xilinx documentation
|-
| P49 || CP2201/AD0 || AD(0)
| Ethernet controller address/data bus, bit 0
|-
| P50 || CP2201/AD1 || AD(1)
| Ethernet controller address/data bus, bit 1
|-
| P51 || FPGA/DIN || [JTAG]
| Serial data input from EEPROM for configuration
|-
| P52 || CP2201/AD2 || AD(2)
| Ethernet controller address/data bus, bit 2
|-
| P53 || FPGA/CCLK || [JTAG]
| Configuration clock (signal generated by FPGA at power on to clock the configuration process) See Xilinx documentation
|-
| P54 || FPGA/DONE || [JTAG]
| Gives configuration status - see Xilinx documentation
|-
| P55 || +3.3V ||
|
|-
| P56 || CP2201/AD3 || AD(3)
| Ethernet controller address/data bus, bit 3
|-
| P57 || CP2201/AD4 || AD(4)
| Ethernet controller address/data bus, bit 4
|-
| P58 || DGND ||
|
|-
| P59 || CP2201/AD5 || AD(5)
| Ethernet controller address/data bus, bit 5
|-
| P60 || CP2201/AD6 || AD(6)
| Ethernet controller address/date bus, bit 6
|-
| P61 || CP2201/AD7 || AD(7)
| Ethernet controller address/date bus, bit 7
|-
| P62 || No connection ||
|
|-
| P63 || DGND ||
|
|-
| P64 || No connection ||
|
|-
| P65 || No connection ||
|
|-
| P66 || +1.2V ||
|
|-
| P67 || +3.3V ||
|
|-
| P68 || +3.3V ||
|
|-
| P69 || DGND ||
|
|-
| P70 || ID3 || LocStamp(3)
| Backplane location identifier jumper, pins 3 & 4 Active-low, FPGA should pull high
|-
| P71 || ID2 || LocStamp(2)
| Backplane location identifier jumper, pins 5 & 6 Active-low, FPGA should pull high
|-
| P72 || ID1 || LocStamp(1)
| Backplane location identifier jumper, pins 7 & 8 Active-low, FPGA should pull high
|-
| P73 || ID0 || LocStamp(0)
| Backplane location identifier jumper, pins 9 & 10 Active-low, FPGA should pull high
|-
| P74 || DGND ||
|
|-
| P75 || FPGA/TDO || [JTAG]
| JTAG
|-
| P76 || FPGA/TCK || [JTAG]
| JTAG
|-
| P77 || ID4 || LocStamp(4)
| Backplane location identifier jumper, pins 1 & 2 Active-low, FPGA should pull high
|-
| P78 || No connection ||
|
|-
| P79 || +3.3V ||
|
|-
| P80 || DGND ||
|
|-
| P81 || +1.2V ||
|
|-
| P82 || No connection || (db) dbShort
| Shorts out the waiting timer in FPGA for Ethernet controller initialization (pulled low)
|-
| P83 || CLK_5MHZ_2 || DAC_Clk
| 5 MHz clock output for DAC
|-
| P84 || No connection ||
|
|-
| P85 || AD5535/DIN || DAC_serData
| DAC serial data input (FPGA out -> DAC in)
|-
| P86 || No connection ||
|
|-
| P87 || DGND ||
|
|-
| P88 || AD5535/SYNC || DAC_setISync
|
|-
| P89 || No connection ||
|
|-
| P90 || No connection ||
|
|-
| P91 || DGND ||
|
|-
| P92 || +3.3V ||
|
|-
| P93 || AD7314/CE || SPI_TCE
| Chip enable for temperature sensor
|-
| P94 || No connection ||
|
|-
| P95 || DGND ||
|
|-
| P96 || +3.3V ||
|
|-
| P97 || (former AD7928/DOUT) ||
| '''Erroneously wired ADC SPI bus connection''' Connects to DOUT on ADC
|-
| P98 || AD5535/RESET || DAC_iRst
|Reset pin for DAC
|-
| P99 || DGND ||
| PUDC_B pin - enables pullup resistors on user IO and input-only pins during FPGA config.
|-
| P100 || FPGA/PROG_B || [JTAG]
| Used during FPGA configuration - see Xilinx documentation
|}

== EEPROM ==
To facilitate power-on configuration of the FPGA, the control board includes a Xilinx XCF01S EEPROM. The EEPROM is located to the left of the FPGA, above the JTAG header, and has a 20 pin footprint. The EEPROM is labelled U5.

=== Power Details ===
The EEPROM uses +3.3V exclusively, which it receives from the +3.3V power plane, regulated by VR1.

=== Flashing/Burning/Writing ===
Whatever you call it, this refers to storing data in the EEPROM so that it can configure the FPGA at power-on. The EEPROM is programmed using a JTAG interface and the Xilinx Platform USB II cable. It is important to note that in digital board's JTAG chain, the EEPROM is the first device in the chain, unlike in the Xilinx documentation where it is shown as the second device. This should not affect the operation of the board, but should be reflected in the Xilinx software when writing the EEPROM via JTAG.

=== FPGA Configuration ===
The EEPROM and FPGA are hardwired to use a master serial protocol to transfer the program from the EEPROM to the FPGA. This is the protocol recommended in the Xilinx documentation because it minimizes the number of traces necessary to run between the EEPROM and FPGA. All configuration data is sent over a single trace, FPGA/DIN (pin 1 on EEPROM), controlled by the configuration clock signal (FPGA/CCLK) which is automatically generated by the FPGA at power-on. When configuration is complete, FPGA/DONE (pin 10) is pulled high by the FPGA, and the EEPROM and configuration clock are deactivated.

=== Pinout Table ===
{| cellpadding=3 border=1 |
| '''Pin #'''
| '''Net Name'''
| '''Description'''
|-
| 1
| FPGA/DIN
| Serial data line Carries data from the EEPROM to the FPGA
|-
| 2
| No connection
|
|-
| 3
| FPGA/CCLK
| Configuration clock Auto generated by FPGA at power-on, disabled at end of configuration
|-
| 4
| EEPROM/TDI
| This is the EEPROM's TDI This is the entry point for the onboard JTAG chain
|-
| 5
| FPGA/TMS
| JTAG TMS Connects to both FPGA and EEPROM
|-
| 6
| FPGA/TCK
| JTAG TCK Connects to both FPGA and EEPROM
|-
| 7
| FPGA/PROG_B
| Used during configuration See Xilinx documentation
|-
| 8
| FPGA/INIT_B
| Used during configuration - can be used to intiate reconfiguration of FPGA See Xilinx documentation
|-
| 9
| No connection
|
|-
| 10
| FPGA/DONE
| Indicates completion of FPGA configuration High when complete
|-
| 11
| DGND
|
|-
| 12-16
| No connection
|
|-
| 17
| FPGA/TDI
| This is the EEPROM's TDO/FPGA's TDI
|-
| 18-20
| +3.3V
|
|}

== JTAG Header ==
To write the FPGA's program to the EEPROM, the board employs a JTAG based programming system consistent with Xilinx's recommendations. The system is designed to operate with Xilnx's Platform USB II cable and the flying lead adapter.

===Header Location and Size===
The header consists of 14 pins, 100 mil pitch, just below the EEPROM (U5). The header is labelled P1. The pitch of the pins in the header was erroneously selected to be 100 mil, which is not compatible with Xilinx's JTAG ribbon cable. Therefore, the Xilinx flying lead adapter must be used.

===Power Details===
The JTAG interface is powered by the +3.3V power plane, not by the computer's USB port. Power is supplied through pin 2 of the JTAG header.

===Pinout Table===
Note that the header is positioned on the board rotated 180 degrees from the position in which it is shown in the Xilinx documentation. Care must be taken when connecting the flying leads to ensure they are connected to the right pins. Improper wiring will certainly cause undesired operation, and may cause damage as well. Damage is most likely to occur if one of the flying leads is improperly connected to an odd numbered pin, since it will short to the PCB's ground plane.

{| cellpadding=3 border=1 |
| '''Pin #'''
| '''Net Name'''
| '''Flying Lead'''
| '''Description'''
|-
| 1, 3, 5, 7, 9, 11, 13 (odd pins)
| DGND
| Black (connect to any odd numbered pin)
| Ground pins for signal integrity '''Never connect a flying lead other than the black lead to an odd numbered pin''' Doing so will short to ground and may cause permanent damage if the Platform USB II cable does not have protection against this.
|-
| 2
| +3.3V
| Red/VREF
| Power source for all JTAG logic
|-
| 4
| FPGA/TMS
| Green/TMS
| JTAG TMS - connects to EEPROM and FPGA
|-
| 6
| FPGA/TCK
| Yellow/TCK
| JTAG TCK - connects to EEPROM and FPGA
|-
| 8
| FPGA/TDO
| Purple/TDO
| JTAG boundary scan chain endpoint
|-
| 10
| EEPROM/TDI
| White/TDI
| JTAG boundary scan chain start point
|-
| 12
| No connection
|
| Pin is floating
|-
| 14
| No connection
|
| Pin is floating
|}
''The gray HALT flying lead is not connected.''

===JTAG Overview===
The JTAG interface is clocked by the TCK signal. TCK is generated by the Platform USB II cable, and connects directly from the JTAG header to both the EEPROM and FPGA.

The TMS signal is directly connected to both the EEPROM and FPGA, and is the data line over which JTAG test results (in this case programming results) are sent. TMS is used by only one component at a time.

The TDI/TDO lines form a chain that connects to each JTAG component in series. On the control board, the first point in the chain is the EEPROM's TDI. Next is the EEPROM's TDO, which is the same as the FPGA's TDI. The FPGA's TDO then returns to the JTAG header and the Platform USB II cable.

== DAC ==
The control board uses the Analog Devices AD5535, 32-channel, 200V max, digital to analog converter. This chip has a modified BC-124 BGA footprint and is located above the Eurocard connector at the bottom of the board. It is labelled U3.

=== Power Details ===
The DAC is primarily powered by the +5V power island, regulated by an off-board power supply and extensively decoupled in the area of the DAC. The DAC also requires -5V, and a high voltage as discussed in [[#Power Requirements | Power Requirements]]. Both of these voltages are supplied by an off-board supply and decoupled near the DAC. In addition to these voltage levels, the DAC requires a precise +2.5V reference, created by the shunt-type voltage reference VR4.

=== Setting the Output Range ===
The output range of the DAC is set by the 2.5V reference voltage supplied by VR4. The high voltage power supply must supply at a minimum 50 times this voltage, plus 10. Thus, the high voltage power supply should be at least 135V for DAC to operate properly, even though the SiPMs are expected to need only 40V. If it is convenient to use a lower high voltage, VR4 must be replaced to provide lower reference voltage. The high voltage may then be decreased appropriately. To summarize:

* Max output voltage = VREF*50
* Minimum high voltage supply = VREF*50 + 10
* Acceptable range for VREF
** Min: 1V
** Max: 3.75V (AD5535 datasheet specifies 4V max, but this would require AVCC of 5.25V for the DAC, which is not possible in the current board design)

If relevant, R13 is a 100K resistor.

=== Thermal Diode ===
The DAC has a built in thermal diode. The diode drop from anode to cathode is typically 0.65V at 25°C. It changes at a rate of -2.20mV/°C. The anode of this diode is connected to the +5V power island, and the cathode is connected to a 270K resistor to ground. The voltage between the cathode and the resistor is connected to VIN1 (pin 15) on the ADC.

=== Pinout Table ===
See documentation from Analog Devices.

=== Channel Mapping ===
Due to the layout of the balls on the footprint of the DAC, the DAC's internal channel numbers (which must be referenced by the FPGA) have no correlation to the channel numbers on the amplifier board. This table summarizes the mapping between various pins that belong to each channel.

{| cellpadding=3 border=1 |
| '''DAC Channel #'''
| '''DAC Pin #'''
| '''Digital Board Eurocard Pin #'''
| '''Amplifier Board Eurocard Pin #'''
| '''Amplifier Channel #'''
|-
| 0
| B1
| B3
| B6
| 6
|-
| 1
| A2
| C4
| B7
| 7
|-
| 2
| D1
| B2
| B4
| 4
|-
| 3
| C2
| C3
| B5
| 5
|-
| 4
| B3
| B4
| B8
| 8
|-
| 5
| E2
| C2
| B3
| 3
|-
| 6
| F3
| B1
| B2
| 2
|-
| 7
| A4
| B5
| B10
| 10
|-
| 8
| E4
| C5
| B9
| 9
|-
| 9
| B5
| C6
| B11
| 11
|-
| 10
| F5
| C1
| B1
| 1
|-
| 11
| A6
| C7
| B13
| 13
|-
| 12
| E6
| B6
| B12
| 12
|-
| 13
| B7
| B7
| B14
| 14
|-
| 14
| F7
| C10
| B19
| 19
|-
| 15
| E8
| C8
| B15
| 15
|-
| 16
| A8
| B8
| B16
| 16
|-
| 17
| B9
| C9
| B17
| 17
|-
| 18
| F9
| C16
| B31
| GAINMODE
|-
| 19
| E10
| B11
| B22
| 22
|-
| 20
| A10
| B9
| B18
| 18
|-
| 21
| B11
| B10
| B20
| 20
|-
| 22
| C12
| B12
| B24
| 24
|-
| 23
| D13
| B13
| B26
| 26
|-
| 24
| E12
| B14
| B28
| 28
|-
| 25
| A12
| C11
| B21
| 21
|-
| 26
| B13
| C12
| B23
| 23
|-
| 27
| H13
| B16
| B30
| 30
|-
| 28
| G14
| B15
| B27
| 27
|-
| 29
| C14
| C13
| B25
| 25
|-
| 30
| F13
| C15
| B29
| 29
|-
| 31
| E14
| C14
| Not connected
| No amplifier connection DACHEALTH See [[#Channel Descriptions | ADC Channel Descriptions]].
|}

==ADC==
The board includes an Analog Devices AD7928 analog to digital converter. The ADC is located just to the right and slightly below the FPGA. It is labelled U4.

===Power Details===
The ADC is powered by the +5V power island, which is regulated by an off-board power supply and decoupled near the ADC. It also requires a precise (±1%) 2.5V reference to which it compares voltages when converting from analog to digital. Since the +5V power source is not used for comparison, it is flexible and may vary by ±0.25V without affecting ADC precision.

===Setting the Measuring Range===
The measuring range is set programmatically by the FPGA over the SPI bus. The way the ADC is connected on the digital board requires that its measuring range be set to 5V, so the RANGE bit should be set to 1 by the FPGA (see Analog Devices documentation).

===Data Interfacing===
The ADC uses an SPI bus to communicate with the FPGA. This bus is shared with the temperature sensor. SPI related pins include SCLK, CS, DIN, and DOUT. See the Pinout Table below.

===Channel Descriptions===
This table shows what signals are monitored by the ADC.

{| cellpadding=3 border=1 |
| '''ADC Channel #'''
| '''ADC Pin #'''
| '''Net Name'''
| '''Description'''
|-
| VIN0
| 16
| AD7928/VHEALTH
| This net helps to monitor to overall health of power on the board, but is specifically intended to monitor -5V. It's voltage is the output of a resistor divider between the +5 and -5V power supplies, with resistor values of 33.2K, and 100K. Assuming +5V and -5V are both correct, the output of the divider will be +2.51V. A reading of other than 2.51V indicates a problem with one of the power supplies. Problems with the +5V power supply can be ruled out by reading VIN3. Based on the reading from VIN3, the voltage of the -5V supply can be calculated.
|-
| VIN1
| 15
| AD5535/CATHODE
| This is the thermal diode output from the DAC. Should read 4.35V (typical) at 25°C. Drops 2.20mV/°C.
|-
| VIN2
| 14
| +3.3V
| This is the +3.3V power plane. A reading of other than +3.3V indicates a problem with VR1.
|-
| VIN3
| 13
| +5V
| This is the +5V power island. A reading of other than +5V indicates a problem with the +5V power supply.
|-
| VIN4
| 12
| ADC_EXT1
| This trace routes to the backplane via Eurocard pin A7. It is intended to measure the output of thermistor on the amplifier board.
|-
| VIN5
| 11
| +1.2V
| This is the +1.2V power island. This island powers the internal logic of the FPGA. A reading of other than 1.2V indicates a problem with VR3.
|-
| VIN6
| 10
| ADC_EXT2
| This trace routes to the backplane via Eurocard pin A8. It is intended to measure one of the transistor base voltages on the amplifier board.
|-
| VIN7
| 9
| DACHEALTH
| This channel monitors the output of a resistor divider connected to channel 31 of the DAC. The divider consists of three resistors of 200K, 200K, and 10.2K (in order). The ADC reads out the voltage level between the second 200K and then 10.2K resistor. These resistors were selected so that at 200V, the readout voltage will be 4.973V. Since the divider should be linear, the expected voltage at 20V is 0.4973V. Three resistors were used rather than two to avoid exceeding the resistors' power ratings when the DAC is set to its maximum voltage. Note that since this divider will consume up to 484uA of current at 200V, this DAC channel should not be used for anything that might require more than ~200uA of current (the DAC can source 700uA max). The channel is routed to the backplane nonetheless.
|}

===Pinout Table===
{| cellpadding=3 border=1 |
| '''Pin #'''
| '''Net Name'''
| '''Description'''
|-
| 1
| CLK_5MHZ
| SPI clock (SCLK), from FPGA Shared with temperature sensor
|-
| 2
| DIN
| SPI data in, from FPGA Shared with temperature sensor ''Currently wired wrong''
|-
| 3
| CS
| SPI chip select
|-
| 4
| AGND
|
|-
| 5
| +5V
| Power pin
|-
| 6
| +5V
| Power pin
|-
| 7
| AD7928/REF_IN
| +2.5V reference, set by VR2
|-
| 8
| AGND
|
|-
| 9-16
| VIN[7:0]
| See [[#Channel Descriptions | ADC Channel Descriptions]]
|-
| 17
| AGND
|
|-
| 18
| DOUT
| SPI data out ''Currently wired incorrectly''
|-
| 19
| +3.3V
| VDRIVE, powers the SPI logic
|-
| 20
| AGND
|
|}

== Ethernet Controller ==
The board uses a Silicon Laboratories CP2201, 28-pin, ethernet controller. The CP2201 is located just above the FPGA, and is labelled U2.

=== Power Details ===
The CP2201 uses only +3.3V, which is supplied by the +3.3V power plane and regulated by VR1. Appropriate decoupling capacitors can be found near the CP2201.

=== Ethernet Jack ===
To the right of the CP2201 is a Pulse J0011D21NL ethernet jack, labelled J1. This jack has a built-in 1:1 inductive coupling. For best results, connect this jack to a nearby ethernet switch. The jack may also be connected directly to a computer using a crossover cable. Though auto-crossover is not supported by the CP2201, if the computer's NIC supports it, a crossover cable is not necessary to connect directly to a computer.

==== Ethernet Jack Pins ====
These are visible only on the back side of the board. Pin 1 is indicated by a square pad. Pin 8 is the farthest pin from pin 1. Pins are numbered such that the 4 pins closer to the plastic thru-hole connectors are odd (1, 3, 5, 7), and the four pins closer to the CP2201 are are even (2, 4, 6, 8).

* Pin 1: TX+
* Pin 2: AC coupled to DGND
* Pin 3: TX-
* Pin 4: RX+
* Pin 5: AC coupled to DGND
* Pin 6: RX-
* Pin 7: No connection
* Pin 8: DGND (direct)

The two large thru-hole pins (not numbered) connect to the metal shielding on the outside of the jack. These are directly connected to DGND to shield against electrical noise inside the jack.

The two plastic thru-hole pins are not conductive and have no electrical connection. They are present only for structural purposes, presumably to prevent stress on the solder points when an ethernet wire is inserted or removed from the jack.

=== Crystal Oscillator ===
The CP2201 is responsible for driving the 20MHz crystal oscillator. This oscillator clocks both the CP2201 and the FPGA. The crystal oscillator can be found above the right corner of the FPGA. It can be identified by its four surface mount pads and roughly .3" length. It is labelled Y1, though this label is not visible after the oscillator is soldered on. The CP2201 uses an inverting driver to excite the crystal. The output of the crystal is then sent to the CP2201 and the FPGA.

=== Bus Format and Multiplexing ===
The 28-pin CP2201 used on the board only supports multiplexed operation. This means that both address and data information are passed over the same set of 8 traces. Hence, these traces are referred to as the address/data (AD) bus. A separate address line enable (ALE) trace prevents collisions from occuring on these traces. The communication protocol used is the Intel format. See the CP2201's datasheet for more information about this.

=== Pinout Table ===
{| cellpadding=3 border=1 |
| '''Pin #'''
| '''Net Name'''
| '''Description'''
|-
| 1
| CP2201/LA
| Link/activity indicator Routed to backplane but not implemented See CP2201 data sheet for information on how to connect to an LED
|-
| 2
| DGND
| By the data sheet, this pin should be AGND We deliberately set it to DGND to avoid noise on AGND plane
|-
| 3
| +3.3V
| AV+ power pin
|-
| 4
| CP2201/RX-
| Connects to RX- on ethernet jack
|-
| 5
| CP2201/RX+
| Connects to RX+ on ethernet jack
|-
| 6
| CP2201/TX+
| Connects to TX+ on ethernet jack
|-
| 7
| CP2201/TX-
| Connects to TX- on ethernet jack
|-
| 8
| +3.3V
| "VDD" power pin
|-
| 9
| DGND
| "DGND1" per the data sheet
|-
| 10
| CP2201/RESET
| "RST" per the data sheet Connects to FPGA - should be programmatically triggered upon reset of FPGA by RESET jumper
|-
| 11-18
| CP2201/AD[0:7]
| Bits 0-7 of the address/data bus Connect to FPGA
|-
| 19
| +3.3V
| "VDD" power pin
|-
| 20
| DGND
| "DGND2" per the data sheet
|-
| 21
| CP2201/ALE
| Address line enable Connects to FPGA See CP2201 documentation
|-
| 22
| CP2201/RD
| Read strobe for AD bus Connects to FPGA See CP2201 documentation
|-
| 23
| CP2201/WR
| Write strobe for AD bus Connects to FPGA See CP2201 documentation
|-
| 24
| CP2201/CS
| Chip select Connects to FPGA
|-
| 25
| CP2201/INT
| Interrupt request Connects to FPGA
|-
| 26
| DGND
| "MOTEN" (Motorola enable) per the datasheet Tied low to disable Motorola bus format (enable Intel format)
|-
| 27
| CP2201/XTAL2
| Crystal oscillator driver The CP2201 inverts the 20MHz clock signal and feeds it back to the crystal oscillator to encourage larger oscillations
|-
| 28
| FPGA/CLK_IN
| "XTAL1" per the data sheet This is the 20MHz clock input Also connects to the FPGA's clock input
|-
| 29*
| DGND
| This is not a pin but rather the base of the CP2201 package. It is connected to the DGND plane for thermal relief
|}

== Eurocard Connector ==
At the bottom of the control board is the Eurocard connector, labelled P2. The Eurocard connector connects the board to the backplane and also connects the board to its power supplies. The Eurocard has 48 pins arranged in three rows of 16 pins each. Rows B and C are exclusively used to pass SiPM bias voltages to the backplane as described in [[#Channel Mapping | DAC Channel Mapping]]. Here is a table describing the purpose of pins in row A:

=== Row A Pinout Table ===
Note that when viewing the front side of the board with the Eurocard at the bottom, these pins go from right to left. If you look closely at the pins, you will see that pin A1 has a square pad, unlike the round pads of the others.

{| cellpadding=3 border=1 |
| '''Pin #'''
| '''Net Name'''
| '''Description'''
|-
| A1
| CP2201/LA
| Ethernet link/activity indicator routed to backplane
|-
| A2
| High voltage input (+210V max)
| High voltage input for DAC. See [[#DAC | DAC]] for information about what voltage to input here.
|-
| A3
| -5V
| For DAC
|-
| A4
| +5V
| Powers most things on the board
|-
| A5
| AGND
|
|-
| A6
| DGND
|
|-
| A7
| ADC_EXT1
| Connects to ADC to monitor voltages on amplifier board See [[#ADC | ADC]]
|-
| A8
| ADC_EXT2
| Connects to ADC to monitor voltages on amplifier board See [[#ADC | ADC]]
|-
| A9
| No connection
|
|-
| A10
| No connection
|
|-
| A11
| No conneciton
|
|-
| A12
| ID4
| Location identifier bit 4 Used to identify which backplane board is connected to See [[#FPGA | FPGA]]
|-
| A13
| ID3
| Location identifier bit 3 Used to identify which backplane board is connected to See [[#FPGA | FPGA]]
|-
| A14
| ID2
| Location identifier bit 2 Used to identify which backplane board is connected to See [[#FPGA | FPGA]]
|-
| A15
| ID1
| Location identifier bit 1 Used to identify which backplane board is connected to See [[#FPGA | FPGA]]
|-
| A16
| ID0
| Location identifier bit 0 Used to identify which backplane board is connected to See [[#FPGA | FPGA]]
|}

Digital control board documentation

2009-07-23T15:39:29Z

Underwood: /* Channel Mapping */ corrections

This documentation covers the most important things to know while testing the digital control board, including component pinouts, nets, and other information.

== Power Requirements ==
=== Required Voltages ===
All components on the digital board '''except the DAC''' can be tested using only a +5V source. The DAC requires +5V, -5V, and a high voltage corresponding to 10V higher than the maximum desired DAC output voltage (see [[#Setting the Output Range | Setting the Output Range]]). Digital and analog grounds must be connected as well before any testing takes place.

=== Power Pins ===
Power shall be connected to the board as follows:
{| cellpadding=3 border=1 |
| '''Voltage'''
| '''Eurocard Pin'''
|-
| DGND
| A6
|-
| AGND
| A5
|-
| +5V
| A4
|-
| -5V
| A3
|-
| High voltage (DAC max out +10)
| A2
|}

=== Power Supply Sequencing ===
The control board is designed such that voltages may be supplied in any order so long as AGND and DGND are connected properly. However, for initial testing, the preferred order for powering up the board is as follows:

# Ensure AGND/DGND are connected/grounded
# +5V
# -5V
# High voltage

== FPGA ==
The control board uses a Xilinx XC3S50A VQ100 FPGA. It has a 100 pin footprint and is located in the center of the control board.

=== Power Details ===
The FPGA is powered by the 3.3V power plane, which is regulated by VR1. The FPGA also obtains 1.2V for its internal logic from a 1.2V power island, regulated by VR3.

=== Logic Standard ===
The Xilinx XC3S50A supports several different digital logic standards. The control board is hard wired such that the FPGA will use a '''3.3V CMOS''' logic standard.

=== Pinout Table ===
{| cellpadding=3 border=1 |
| '''Pin #''' || '''Net Name''' || '''Signal Name'''
| '''Description'''
|-
| P1 || FPGA/TMS || [JTAG]
| JTAG
|-
| P2 || FPGA/TDI || [JTAG]
| JTAG
|-
| P3 || AD7928/CS || SPI_A_iCS
| SPI chip select for ADC
|-
| P4 || SPI || SPI_SDO
| '''Erroneously wired SPI bus trace''' Now connects to SDO on temp. sensor and on ADC
|-
| P5 || CLK_5MHZ || SPI_SCLK
| 5 MHz clock output for SPI bus (ADC and temp. sensor)
|-
| P6 || No connection ||
|
|-
| P7 || No connection ||
|
|-
| P8 || DGND ||
|
|-
| P9 || No connection ||
|
|-
| P10 || No connection ||
|
|-
| P11 || +3.3V ||
|
|-
| P12 || No connection ||
|
|-
| P13 || No connection ||
|
|-
| P14 || DGND ||
|
|-
| P15 || No connection ||
|
|-
| P16 || No connection ||
|
|-
| P17 || +1.2V ||
|
|-
| P18 || DGND ||
|
|-
| P19 || dBinfo_Start ||
|
|-
| P20 || dBinfo_Stream ||
|
|-
| P21 || No connection ||
|
|-
| P22 || +3.3V ||
|
|-
| P23 || DGND || [M1: JTAG prog. config.]
|
|-
| P24 || DGND || [M2: JTAG prog. config.]
|
|-
| P25 || DGND || [M0: JTAG prog. config.]
|
|-
| P26 || +3.3V ||
|
|-
| P27 || FPGA/CLK_IN || fClk
| 20 MHz clock input from crystal oscillator
|-
| P28 || No connection ||
|
|-
| P29 || No connection || (db) state_Q(0)
|
|-
| P30 || No connection ||
|
|-
| P31 || No connection || (db) state_Q(1)
|
|-
| P32 || No connection ||
|
|-
| P33 || No connection || (db) state_Q(2)
|
|-
| P34 || No connection ||
|
|-
| P35 || CP2201/INT || Eth_iINT
| Ethernet controller interrupt
|-
| P36 || MASTER_RESET || Rst
| Connects to RESET jumper in upper left of board (active-low, externally pulled up)
|-
| P37 || (manually wired) || fClk_out
|
|-
| P38 || +1.2V ||
|
|-
| P39 || No connection ||
|
|-
| P40 || CP2201/CS || iCS
| Chip select for ethernet controller
|-
| P41 || CP2201/WR || iWR
| Write enable for ethernet controller
|-
| P42 || DGND ||
|
|-
| P43 || CP2201/RD || iRD
| Read enable for ethernet controller
|-
| P44 || CP2201/ALE || ALE
| Address line enable for ethernet controller
|-
| P45 || +3.3V ||
|
|-
| P46 || CP2201/RESET || Eth_iRst
| Reset pin for ethernet controller
|-
| P47 || DGND ||
|
|-
| P48 || FPGA/INIT_B || [JTAG]
| Used during FPGA configuration - see Xilinx documentation
|-
| P49 || CP2201/AD0 || AD(0)
| Ethernet controller address/data bus, bit 0
|-
| P50 || CP2201/AD1 || AD(1)
| Ethernet controller address/data bus, bit 1
|-
| P51 || FPGA/DIN || [JTAG]
| Serial data input from EEPROM for configuration
|-
| P52 || CP2201/AD2 || AD(2)
| Ethernet controller address/data bus, bit 2
|-
| P53 || FPGA/CCLK || [JTAG]
| Configuration clock (signal generated by FPGA at power on to clock the configuration process) See Xilinx documentation
|-
| P54 || FPGA/DONE || [JTAG]
| Gives configuration status - see Xilinx documentation
|-
| P55 || +3.3V ||
|
|-
| P56 || CP2201/AD3 || AD(3)
| Ethernet controller address/data bus, bit 3
|-
| P57 || CP2201/AD4 || AD(4)
| Ethernet controller address/data bus, bit 4
|-
| P58 || DGND ||
|
|-
| P59 || CP2201/AD5 || AD(5)
| Ethernet controller address/data bus, bit 5
|-
| P60 || CP2201/AD6 || AD(6)
| Ethernet controller address/date bus, bit 6
|-
| P61 || CP2201/AD7 || AD(7)
| Ethernet controller address/date bus, bit 7
|-
| P62 || No connection ||
|
|-
| P63 || DGND ||
|
|-
| P64 || No connection ||
|
|-
| P65 || No connection ||
|
|-
| P66 || +1.2V ||
|
|-
| P67 || +3.3V ||
|
|-
| P68 || +3.3V ||
|
|-
| P69 || DGND ||
|
|-
| P70 || ID3 || LocStamp(3)
| Backplane location identifier jumper, pins 3 & 4 Active-low, FPGA should pull high
|-
| P71 || ID2 || LocStamp(2)
| Backplane location identifier jumper, pins 5 & 6 Active-low, FPGA should pull high
|-
| P72 || ID1 || LocStamp(1)
| Backplane location identifier jumper, pins 7 & 8 Active-low, FPGA should pull high
|-
| P73 || ID0 || LocStamp(0)
| Backplane location identifier jumper, pins 9 & 10 Active-low, FPGA should pull high
|-
| P74 || DGND ||
|
|-
| P75 || FPGA/TDO || [JTAG]
| JTAG
|-
| P76 || FPGA/TCK || [JTAG]
| JTAG
|-
| P77 || ID4 || LocStamp(4)
| Backplane location identifier jumper, pins 1 & 2 Active-low, FPGA should pull high
|-
| P78 || No connection ||
|
|-
| P79 || +3.3V ||
|
|-
| P80 || DGND ||
|
|-
| P81 || +1.2V ||
|
|-
| P82 || No connection || (db) dbShort
| Shorts out the waiting timer in FPGA for Ethernet controller initialization (pulled low)
|-
| P83 || CLK_5MHZ_2 || DAC_Clk
| 5 MHz clock output for DAC
|-
| P84 || No connection ||
|
|-
| P85 || AD5535/DIN || DAC_serData
| DAC serial data input (FPGA out -> DAC in)
|-
| P86 || No connection ||
|
|-
| P87 || DGND ||
|
|-
| P88 || AD5535/SYNC || DAC_setISync
|
|-
| P89 || No connection ||
|
|-
| P90 || No connection ||
|
|-
| P91 || DGND ||
|
|-
| P92 || +3.3V ||
|
|-
| P93 || AD7314/CE || SPI_TCE
| Chip enable for temperature sensor
|-
| P94 || No connection ||
|
|-
| P95 || DGND ||
|
|-
| P96 || +3.3V ||
|
|-
| P97 || (former AD7928/DOUT) ||
| '''Erroneously wired ADC SPI bus connection''' Connects to DOUT on ADC
|-
| P98 || AD5535/RESET || DAC_iRst
|Reset pin for DAC
|-
| P99 || DGND ||
| PUDC_B pin - enables pullup resistors on user IO and input-only pins during FPGA config.
|-
| P100 || FPGA/PROG_B || [JTAG]
| Used during FPGA configuration - see Xilinx documentation
|}

== EEPROM ==
To facilitate power-on configuration of the FPGA, the control board includes a Xilinx XCF01S EEPROM. The EEPROM is located to the left of the FPGA, above the JTAG header, and has a 20 pin footprint. The EEPROM is labelled U5.

=== Power Details ===
The EEPROM uses +3.3V exclusively, which it receives from the +3.3V power plane, regulated by VR1.

=== Flashing/Burning/Writing ===
Whatever you call it, this refers to storing data in the EEPROM so that it can configure the FPGA at power-on. The EEPROM is programmed using a JTAG interface and the Xilinx Platform USB II cable. It is important to note that in digital board's JTAG chain, the EEPROM is the first device in the chain, unlike in the Xilinx documentation where it is shown as the second device. This should not affect the operation of the board, but should be reflected in the Xilinx software when writing the EEPROM via JTAG.

=== FPGA Configuration ===
The EEPROM and FPGA are hardwired to use a master serial protocol to transfer the program from the EEPROM to the FPGA. This is the protocol recommended in the Xilinx documentation because it minimizes the number of traces necessary to run between the EEPROM and FPGA. All configuration data is sent over a single trace, FPGA/DIN (pin 1 on EEPROM), controlled by the configuration clock signal (FPGA/CCLK) which is automatically generated by the FPGA at power-on. When configuration is complete, FPGA/DONE (pin 10) is pulled high by the FPGA, and the EEPROM and configuration clock are deactivated.

=== Pinout Table ===
{| cellpadding=3 border=1 |
| '''Pin #'''
| '''Net Name'''
| '''Description'''
|-
| 1
| FPGA/DIN
| Serial data line Carries data from the EEPROM to the FPGA
|-
| 2
| No connection
|
|-
| 3
| FPGA/CCLK
| Configuration clock Auto generated by FPGA at power-on, disabled at end of configuration
|-
| 4
| EEPROM/TDI
| This is the EEPROM's TDI This is the entry point for the onboard JTAG chain
|-
| 5
| FPGA/TMS
| JTAG TMS Connects to both FPGA and EEPROM
|-
| 6
| FPGA/TCK
| JTAG TCK Connects to both FPGA and EEPROM
|-
| 7
| FPGA/PROG_B
| Used during configuration See Xilinx documentation
|-
| 8
| FPGA/INIT_B
| Used during configuration - can be used to intiate reconfiguration of FPGA See Xilinx documentation
|-
| 9
| No connection
|
|-
| 10
| FPGA/DONE
| Indicates completion of FPGA configuration High when complete
|-
| 11
| DGND
|
|-
| 12-16
| No connection
|
|-
| 17
| FPGA/TDI
| This is the EEPROM's TDO/FPGA's TDI
|-
| 18-20
| +3.3V
|
|}

== JTAG Header ==
To write the FPGA's program to the EEPROM, the board employs a JTAG based programming system consistent with Xilinx's recommendations. The system is designed to operate with Xilnx's Platform USB II cable and the flying lead adapter.

===Header Location and Size===
The header consists of 14 pins, 100 mil pitch, just below the EEPROM (U5). The header is labelled P1. The pitch of the pins in the header was erroneously selected to be 100 mil, which is not compatible with Xilinx's JTAG ribbon cable. Therefore, the Xilinx flying lead adapter must be used.

===Power Details===
The JTAG interface is powered by the +3.3V power plane, not by the computer's USB port. Power is supplied through pin 2 of the JTAG header.

===Pinout Table===
Note that the header is positioned on the board rotated 180 degrees from the position in which it is shown in the Xilinx documentation. Care must be taken when connecting the flying leads to ensure they are connected to the right pins. Improper wiring will certainly cause undesired operation, and may cause damage as well. Damage is most likely to occur if one of the flying leads is improperly connected to an odd numbered pin, since it will short to the PCB's ground plane.

{| cellpadding=3 border=1 |
| '''Pin #'''
| '''Net Name'''
| '''Flying Lead'''
| '''Description'''
|-
| 1, 3, 5, 7, 9, 11, 13 (odd pins)
| DGND
| Black (connect to any odd numbered pin)
| Ground pins for signal integrity '''Never connect a flying lead other than the black lead to an odd numbered pin''' Doing so will short to ground and may cause permanent damage if the Platform USB II cable does not have protection against this.
|-
| 2
| +3.3V
| Red/VREF
| Power source for all JTAG logic
|-
| 4
| FPGA/TMS
| Green/TMS
| JTAG TMS - connects to EEPROM and FPGA
|-
| 6
| FPGA/TCK
| Yellow/TCK
| JTAG TCK - connects to EEPROM and FPGA
|-
| 8
| FPGA/TDO
| Purple/TDO
| JTAG boundary scan chain endpoint
|-
| 10
| EEPROM/TDI
| White/TDI
| JTAG boundary scan chain start point
|-
| 12
| No connection
|
| Pin is floating
|-
| 14
| No connection
|
| Pin is floating
|}
''The gray HALT flying lead is not connected.''

===JTAG Overview===
The JTAG interface is clocked by the TCK signal. TCK is generated by the Platform USB II cable, and connects directly from the JTAG header to both the EEPROM and FPGA.

The TMS signal is directly connected to both the EEPROM and FPGA, and is the data line over which JTAG test results (in this case programming results) are sent. TMS is used by only one component at a time.

The TDI/TDO lines form a chain that connects to each JTAG component in series. On the control board, the first point in the chain is the EEPROM's TDI. Next is the EEPROM's TDO, which is the same as the FPGA's TDI. The FPGA's TDO then returns to the JTAG header and the Platform USB II cable.

== DAC ==
The control board uses the Analog Devices AD5535, 32-channel, 200V max, digital to analog converter. This chip has a modified BC-124 BGA footprint and is located above the Eurocard connector at the bottom of the board. It is labelled U3.

=== Power Details ===
The DAC is primarily powered by the +5V power island, regulated by an off-board power supply and extensively decoupled in the area of the DAC. The DAC also requires -5V, and a high voltage as discussed in [[#Power Requirements | Power Requirements]]. Both of these voltages are supplied by an off-board supply and decoupled near the DAC. In addition to these voltage levels, the DAC requires a precise +2.5V reference, created by the shunt-type voltage reference VR4.

=== Setting the Output Range ===
The output range of the DAC is set by the 2.5V reference voltage supplied by VR4. The high voltage power supply must supply at a minimum 50 times this voltage, plus 10. Thus, the high voltage power supply should be at least 135V for DAC to operate properly, even though the SiPMs are expected to need only 40V. If it is convenient to use a lower high voltage, VR4 must be replaced to provide lower reference voltage. The high voltage may then be decreased appropriately. To summarize:

* Max output voltage = VREF*50
* Minimum high voltage supply = VREF*50 + 10
* Acceptable range for VREF
** Min: 1V
** Max: 3.75V (AD5535 datasheet specifies 4V max, but this would require AVCC of 5.25V for the DAC, which is not possible in the current board design)

If relevant, R13 is a 100K resistor.

=== Thermal Diode ===
The DAC has a built in thermal diode. The diode drop from anode to cathode is typically 0.65V at 25°C. It changes at a rate of -2.20mV/°C. The anode of this diode is connected to the +5V power island, and the cathode is connected to a 270K resistor to ground. The voltage between the cathode and the resistor is connected to VIN1 (pin 15) on the ADC.

=== Pinout Table ===
See documentation from Analog Devices.

=== Channel Mapping ===
Due to the layout of the balls on the footprint of the DAC, the DAC's internal channel numbers (which must be referenced by the FPGA) have no correlation to the channel numbers on the amplifier board. This table summarizes the mapping between various pins that belong to each channel.

{| cellpadding=3 border=1 |
| '''DAC Channel #'''
| '''DAC Pin #'''
| '''Digital Board Eurocard Pin #'''
| '''Amplifier Board Eurocard Pin #'''
| '''Amplifier Channel #'''
|-
| 0
| B1
| B3
| B6
| 6
|-
| 1
| A2
| C4
| B7
| 7
|-
| 2
| D1
| B2
| B4
| 4
|-
| 3
| C2
| C3
| B5
| 5
|-
| 4
| B3
| B4
| B8
| 8
|-
| 5
| E2
| C2
| B3
| 3
|-
| 6
| F3
| B1
| B2
| 2
|-
| 7
| A4
| B5
| B10
| 10
|-
| 8
| E4
| C5
| B9
| 9
|-
| 9
| B5
| C6
| B11
| 11
|-
| 10
| F5
| C1
| B1
| 1
|-
| 11
| A6
| C7
| B13
| 13
|-
| 12
| E6
| B6
| B12
| 12
|-
| 13
| B7
| B7
| B14
| 14
|-
| 14
| F7
| C10
| B19
| 19
|-
| 15
| E8
| C8
| B15
| 15
|-
| 16
| A8
| B8
| B16
| 16
|-
| 17
| B9
| C9
| B17
| 17
|-
| 18
| F9
| C16
| B31
| GAINMODE
|-
| 19
| E10
| B11
| B22
| 22
|-
| 20
| A10
| B9
| B18
| 18
|-
| 21
| B11
| B10
| B20
| 20
|-
| 22
| C12
| B12
| B24
| 24
|-
| 23
| D13
| B13
| B26
| 26
|-
| 24
| E12
| B14
| B28
| 28
|-
| 25
| A12
| C11
| B21
| 21
|-
| 26
| B13
| C12
| B23
| 23
|-
| 27
| H13
| B16
| Not connected
| No amplifier connection
|-
| 28
| G14
| B15
| B30
| 30
|-
| 29
| C14
| C13
| B25
| 25
|-
| 30
| F13
| C15
| B29
| 29
|-
| 31
| E14
| C14
| B27
| 27 DACHEALTH See [[#Channel Descriptions | ADC Channel Descriptions]].
|}

==ADC==
The board includes an Analog Devices AD7928 analog to digital converter. The ADC is located just to the right and slightly below the FPGA. It is labelled U4.

===Power Details===
The ADC is powered by the +5V power island, which is regulated by an off-board power supply and decoupled near the ADC. It also requires a precise (±1%) 2.5V reference to which it compares voltages when converting from analog to digital. Since the +5V power source is not used for comparison, it is flexible and may vary by ±0.25V without affecting ADC precision.

===Setting the Measuring Range===
The measuring range is set programmatically by the FPGA over the SPI bus. The way the ADC is connected on the digital board requires that its measuring range be set to 5V, so the RANGE bit should be set to 1 by the FPGA (see Analog Devices documentation).

===Data Interfacing===
The ADC uses an SPI bus to communicate with the FPGA. This bus is shared with the temperature sensor. SPI related pins include SCLK, CS, DIN, and DOUT. See the Pinout Table below.

===Channel Descriptions===
This table shows what signals are monitored by the ADC.

{| cellpadding=3 border=1 |
| '''ADC Channel #'''
| '''ADC Pin #'''
| '''Net Name'''
| '''Description'''
|-
| VIN0
| 16
| AD7928/VHEALTH
| This net helps to monitor to overall health of power on the board, but is specifically intended to monitor -5V. It's voltage is the output of a resistor divider between the +5 and -5V power supplies, with resistor values of 33.2K, and 100K. Assuming +5V and -5V are both correct, the output of the divider will be +2.51V. A reading of other than 2.51V indicates a problem with one of the power supplies. Problems with the +5V power supply can be ruled out by reading VIN3. Based on the reading from VIN3, the voltage of the -5V supply can be calculated.
|-
| VIN1
| 15
| AD5535/CATHODE
| This is the thermal diode output from the DAC. Should read 4.35V (typical) at 25°C. Drops 2.20mV/°C.
|-
| VIN2
| 14
| +3.3V
| This is the +3.3V power plane. A reading of other than +3.3V indicates a problem with VR1.
|-
| VIN3
| 13
| +5V
| This is the +5V power island. A reading of other than +5V indicates a problem with the +5V power supply.
|-
| VIN4
| 12
| ADC_EXT1
| This trace routes to the backplane via Eurocard pin A7. It is intended to measure the output of thermistor on the amplifier board.
|-
| VIN5
| 11
| +1.2V
| This is the +1.2V power island. This island powers the internal logic of the FPGA. A reading of other than 1.2V indicates a problem with VR3.
|-
| VIN6
| 10
| ADC_EXT2
| This trace routes to the backplane via Eurocard pin A8. It is intended to measure one of the transistor base voltages on the amplifier board.
|-
| VIN7
| 9
| DACHEALTH
| This channel monitors the output of a resistor divider connected to channel 31 of the DAC. The divider consists of three resistors of 200K, 200K, and 10.2K (in order). The ADC reads out the voltage level between the second 200K and then 10.2K resistor. These resistors were selected so that at 200V, the readout voltage will be 4.973V. Since the divider should be linear, the expected voltage at 20V is 0.4973V. Three resistors were used rather than two to avoid exceeding the resistors' power ratings when the DAC is set to its maximum voltage. Note that since this divider will consume up to 484uA of current at 200V, this DAC channel should not be used for anything that might require more than ~200uA of current (the DAC can source 700uA max). The channel is routed to the backplane nonetheless.
|}

===Pinout Table===
{| cellpadding=3 border=1 |
| '''Pin #'''
| '''Net Name'''
| '''Description'''
|-
| 1
| CLK_5MHZ
| SPI clock (SCLK), from FPGA Shared with temperature sensor
|-
| 2
| DIN
| SPI data in, from FPGA Shared with temperature sensor ''Currently wired wrong''
|-
| 3
| CS
| SPI chip select
|-
| 4
| AGND
|
|-
| 5
| +5V
| Power pin
|-
| 6
| +5V
| Power pin
|-
| 7
| AD7928/REF_IN
| +2.5V reference, set by VR2
|-
| 8
| AGND
|
|-
| 9-16
| VIN[7:0]
| See [[#Channel Descriptions | ADC Channel Descriptions]]
|-
| 17
| AGND
|
|-
| 18
| DOUT
| SPI data out ''Currently wired incorrectly''
|-
| 19
| +3.3V
| VDRIVE, powers the SPI logic
|-
| 20
| AGND
|
|}

== Ethernet Controller ==
The board uses a Silicon Laboratories CP2201, 28-pin, ethernet controller. The CP2201 is located just above the FPGA, and is labelled U2.

=== Power Details ===
The CP2201 uses only +3.3V, which is supplied by the +3.3V power plane and regulated by VR1. Appropriate decoupling capacitors can be found near the CP2201.

=== Ethernet Jack ===
To the right of the CP2201 is a Pulse J0011D21NL ethernet jack, labelled J1. This jack has a built-in 1:1 inductive coupling. For best results, connect this jack to a nearby ethernet switch. The jack may also be connected directly to a computer using a crossover cable. Though auto-crossover is not supported by the CP2201, if the computer's NIC supports it, a crossover cable is not necessary to connect directly to a computer.

==== Ethernet Jack Pins ====
These are visible only on the back side of the board. Pin 1 is indicated by a square pad. Pin 8 is the farthest pin from pin 1. Pins are numbered such that the 4 pins closer to the plastic thru-hole connectors are odd (1, 3, 5, 7), and the four pins closer to the CP2201 are are even (2, 4, 6, 8).

* Pin 1: TX+
* Pin 2: AC coupled to DGND
* Pin 3: TX-
* Pin 4: RX+
* Pin 5: AC coupled to DGND
* Pin 6: RX-
* Pin 7: No connection
* Pin 8: DGND (direct)

The two large thru-hole pins (not numbered) connect to the metal shielding on the outside of the jack. These are directly connected to DGND to shield against electrical noise inside the jack.

The two plastic thru-hole pins are not conductive and have no electrical connection. They are present only for structural purposes, presumably to prevent stress on the solder points when an ethernet wire is inserted or removed from the jack.

=== Crystal Oscillator ===
The CP2201 is responsible for driving the 20MHz crystal oscillator. This oscillator clocks both the CP2201 and the FPGA. The crystal oscillator can be found above the right corner of the FPGA. It can be identified by its four surface mount pads and roughly .3" length. It is labelled Y1, though this label is not visible after the oscillator is soldered on. The CP2201 uses an inverting driver to excite the crystal. The output of the crystal is then sent to the CP2201 and the FPGA.

=== Bus Format and Multiplexing ===
The 28-pin CP2201 used on the board only supports multiplexed operation. This means that both address and data information are passed over the same set of 8 traces. Hence, these traces are referred to as the address/data (AD) bus. A separate address line enable (ALE) trace prevents collisions from occuring on these traces. The communication protocol used is the Intel format. See the CP2201's datasheet for more information about this.

=== Pinout Table ===
{| cellpadding=3 border=1 |
| '''Pin #'''
| '''Net Name'''
| '''Description'''
|-
| 1
| CP2201/LA
| Link/activity indicator Routed to backplane but not implemented See CP2201 data sheet for information on how to connect to an LED
|-
| 2
| DGND
| By the data sheet, this pin should be AGND We deliberately set it to DGND to avoid noise on AGND plane
|-
| 3
| +3.3V
| AV+ power pin
|-
| 4
| CP2201/RX-
| Connects to RX- on ethernet jack
|-
| 5
| CP2201/RX+
| Connects to RX+ on ethernet jack
|-
| 6
| CP2201/TX+
| Connects to TX+ on ethernet jack
|-
| 7
| CP2201/TX-
| Connects to TX- on ethernet jack
|-
| 8
| +3.3V
| "VDD" power pin
|-
| 9
| DGND
| "DGND1" per the data sheet
|-
| 10
| CP2201/RESET
| "RST" per the data sheet Connects to FPGA - should be programmatically triggered upon reset of FPGA by RESET jumper
|-
| 11-18
| CP2201/AD[0:7]
| Bits 0-7 of the address/data bus Connect to FPGA
|-
| 19
| +3.3V
| "VDD" power pin
|-
| 20
| DGND
| "DGND2" per the data sheet
|-
| 21
| CP2201/ALE
| Address line enable Connects to FPGA See CP2201 documentation
|-
| 22
| CP2201/RD
| Read strobe for AD bus Connects to FPGA See CP2201 documentation
|-
| 23
| CP2201/WR
| Write strobe for AD bus Connects to FPGA See CP2201 documentation
|-
| 24
| CP2201/CS
| Chip select Connects to FPGA
|-
| 25
| CP2201/INT
| Interrupt request Connects to FPGA
|-
| 26
| DGND
| "MOTEN" (Motorola enable) per the datasheet Tied low to disable Motorola bus format (enable Intel format)
|-
| 27
| CP2201/XTAL2
| Crystal oscillator driver The CP2201 inverts the 20MHz clock signal and feeds it back to the crystal oscillator to encourage larger oscillations
|-
| 28
| FPGA/CLK_IN
| "XTAL1" per the data sheet This is the 20MHz clock input Also connects to the FPGA's clock input
|-
| 29*
| DGND
| This is not a pin but rather the base of the CP2201 package. It is connected to the DGND plane for thermal relief
|}

== Eurocard Connector ==
At the bottom of the control board is the Eurocard connector, labelled P2. The Eurocard connector connects the board to the backplane and also connects the board to its power supplies. The Eurocard has 48 pins arranged in three rows of 16 pins each. Rows B and C are exclusively used to pass SiPM bias voltages to the backplane as described in [[#Channel Mapping | DAC Channel Mapping]]. Here is a table describing the purpose of pins in row A:

=== Row A Pinout Table ===
Note that when viewing the front side of the board with the Eurocard at the bottom, these pins go from right to left. If you look closely at the pins, you will see that pin A1 has a square pad, unlike the round pads of the others.

{| cellpadding=3 border=1 |
| '''Pin #'''
| '''Net Name'''
| '''Description'''
|-
| A1
| CP2201/LA
| Ethernet link/activity indicator routed to backplane
|-
| A2
| High voltage input (+210V max)
| High voltage input for DAC. See [[#DAC | DAC]] for information about what voltage to input here.
|-
| A3
| -5V
| For DAC
|-
| A4
| +5V
| Powers most things on the board
|-
| A5
| AGND
|
|-
| A6
| DGND
|
|-
| A7
| ADC_EXT1
| Connects to ADC to monitor voltages on amplifier board See [[#ADC | ADC]]
|-
| A8
| ADC_EXT2
| Connects to ADC to monitor voltages on amplifier board See [[#ADC | ADC]]
|-
| A9
| No connection
|
|-
| A10
| No connection
|
|-
| A11
| No conneciton
|
|-
| A12
| ID4
| Location identifier bit 4 Used to identify which backplane board is connected to See [[#FPGA | FPGA]]
|-
| A13
| ID3
| Location identifier bit 3 Used to identify which backplane board is connected to See [[#FPGA | FPGA]]
|-
| A14
| ID2
| Location identifier bit 2 Used to identify which backplane board is connected to See [[#FPGA | FPGA]]
|-
| A15
| ID1
| Location identifier bit 1 Used to identify which backplane board is connected to See [[#FPGA | FPGA]]
|-
| A16
| ID0
| Location identifier bit 0 Used to identify which backplane board is connected to See [[#FPGA | FPGA]]
|}

Digital control board documentation

2009-07-23T15:35:05Z

Underwood: /* Channel Mapping */ completed amplifier channel mapping

This documentation covers the most important things to know while testing the digital control board, including component pinouts, nets, and other information.

== Power Requirements ==
=== Required Voltages ===
All components on the digital board '''except the DAC''' can be tested using only a +5V source. The DAC requires +5V, -5V, and a high voltage corresponding to 10V higher than the maximum desired DAC output voltage (see [[#Setting the Output Range | Setting the Output Range]]). Digital and analog grounds must be connected as well before any testing takes place.

=== Power Pins ===
Power shall be connected to the board as follows:
{| cellpadding=3 border=1 |
| '''Voltage'''
| '''Eurocard Pin'''
|-
| DGND
| A6
|-
| AGND
| A5
|-
| +5V
| A4
|-
| -5V
| A3
|-
| High voltage (DAC max out +10)
| A2
|}

=== Power Supply Sequencing ===
The control board is designed such that voltages may be supplied in any order so long as AGND and DGND are connected properly. However, for initial testing, the preferred order for powering up the board is as follows:

# Ensure AGND/DGND are connected/grounded
# +5V
# -5V
# High voltage

== FPGA ==
The control board uses a Xilinx XC3S50A VQ100 FPGA. It has a 100 pin footprint and is located in the center of the control board.

=== Power Details ===
The FPGA is powered by the 3.3V power plane, which is regulated by VR1. The FPGA also obtains 1.2V for its internal logic from a 1.2V power island, regulated by VR3.

=== Logic Standard ===
The Xilinx XC3S50A supports several different digital logic standards. The control board is hard wired such that the FPGA will use a '''3.3V CMOS''' logic standard.

=== Pinout Table ===
{| cellpadding=3 border=1 |
| '''Pin #''' || '''Net Name''' || '''Signal Name'''
| '''Description'''
|-
| P1 || FPGA/TMS || [JTAG]
| JTAG
|-
| P2 || FPGA/TDI || [JTAG]
| JTAG
|-
| P3 || AD7928/CS || SPI_A_iCS
| SPI chip select for ADC
|-
| P4 || SPI || SPI_SDO
| '''Erroneously wired SPI bus trace''' Now connects to SDO on temp. sensor and on ADC
|-
| P5 || CLK_5MHZ || SPI_SCLK
| 5 MHz clock output for SPI bus (ADC and temp. sensor)
|-
| P6 || No connection ||
|
|-
| P7 || No connection ||
|
|-
| P8 || DGND ||
|
|-
| P9 || No connection ||
|
|-
| P10 || No connection ||
|
|-
| P11 || +3.3V ||
|
|-
| P12 || No connection ||
|
|-
| P13 || No connection ||
|
|-
| P14 || DGND ||
|
|-
| P15 || No connection ||
|
|-
| P16 || No connection ||
|
|-
| P17 || +1.2V ||
|
|-
| P18 || DGND ||
|
|-
| P19 || dBinfo_Start ||
|
|-
| P20 || dBinfo_Stream ||
|
|-
| P21 || No connection ||
|
|-
| P22 || +3.3V ||
|
|-
| P23 || DGND || [M1: JTAG prog. config.]
|
|-
| P24 || DGND || [M2: JTAG prog. config.]
|
|-
| P25 || DGND || [M0: JTAG prog. config.]
|
|-
| P26 || +3.3V ||
|
|-
| P27 || FPGA/CLK_IN || fClk
| 20 MHz clock input from crystal oscillator
|-
| P28 || No connection ||
|
|-
| P29 || No connection || (db) state_Q(0)
|
|-
| P30 || No connection ||
|
|-
| P31 || No connection || (db) state_Q(1)
|
|-
| P32 || No connection ||
|
|-
| P33 || No connection || (db) state_Q(2)
|
|-
| P34 || No connection ||
|
|-
| P35 || CP2201/INT || Eth_iINT
| Ethernet controller interrupt
|-
| P36 || MASTER_RESET || Rst
| Connects to RESET jumper in upper left of board (active-low, externally pulled up)
|-
| P37 || (manually wired) || fClk_out
|
|-
| P38 || +1.2V ||
|
|-
| P39 || No connection ||
|
|-
| P40 || CP2201/CS || iCS
| Chip select for ethernet controller
|-
| P41 || CP2201/WR || iWR
| Write enable for ethernet controller
|-
| P42 || DGND ||
|
|-
| P43 || CP2201/RD || iRD
| Read enable for ethernet controller
|-
| P44 || CP2201/ALE || ALE
| Address line enable for ethernet controller
|-
| P45 || +3.3V ||
|
|-
| P46 || CP2201/RESET || Eth_iRst
| Reset pin for ethernet controller
|-
| P47 || DGND ||
|
|-
| P48 || FPGA/INIT_B || [JTAG]
| Used during FPGA configuration - see Xilinx documentation
|-
| P49 || CP2201/AD0 || AD(0)
| Ethernet controller address/data bus, bit 0
|-
| P50 || CP2201/AD1 || AD(1)
| Ethernet controller address/data bus, bit 1
|-
| P51 || FPGA/DIN || [JTAG]
| Serial data input from EEPROM for configuration
|-
| P52 || CP2201/AD2 || AD(2)
| Ethernet controller address/data bus, bit 2
|-
| P53 || FPGA/CCLK || [JTAG]
| Configuration clock (signal generated by FPGA at power on to clock the configuration process) See Xilinx documentation
|-
| P54 || FPGA/DONE || [JTAG]
| Gives configuration status - see Xilinx documentation
|-
| P55 || +3.3V ||
|
|-
| P56 || CP2201/AD3 || AD(3)
| Ethernet controller address/data bus, bit 3
|-
| P57 || CP2201/AD4 || AD(4)
| Ethernet controller address/data bus, bit 4
|-
| P58 || DGND ||
|
|-
| P59 || CP2201/AD5 || AD(5)
| Ethernet controller address/data bus, bit 5
|-
| P60 || CP2201/AD6 || AD(6)
| Ethernet controller address/date bus, bit 6
|-
| P61 || CP2201/AD7 || AD(7)
| Ethernet controller address/date bus, bit 7
|-
| P62 || No connection ||
|
|-
| P63 || DGND ||
|
|-
| P64 || No connection ||
|
|-
| P65 || No connection ||
|
|-
| P66 || +1.2V ||
|
|-
| P67 || +3.3V ||
|
|-
| P68 || +3.3V ||
|
|-
| P69 || DGND ||
|
|-
| P70 || ID3 || LocStamp(3)
| Backplane location identifier jumper, pins 3 & 4 Active-low, FPGA should pull high
|-
| P71 || ID2 || LocStamp(2)
| Backplane location identifier jumper, pins 5 & 6 Active-low, FPGA should pull high
|-
| P72 || ID1 || LocStamp(1)
| Backplane location identifier jumper, pins 7 & 8 Active-low, FPGA should pull high
|-
| P73 || ID0 || LocStamp(0)
| Backplane location identifier jumper, pins 9 & 10 Active-low, FPGA should pull high
|-
| P74 || DGND ||
|
|-
| P75 || FPGA/TDO || [JTAG]
| JTAG
|-
| P76 || FPGA/TCK || [JTAG]
| JTAG
|-
| P77 || ID4 || LocStamp(4)
| Backplane location identifier jumper, pins 1 & 2 Active-low, FPGA should pull high
|-
| P78 || No connection ||
|
|-
| P79 || +3.3V ||
|
|-
| P80 || DGND ||
|
|-
| P81 || +1.2V ||
|
|-
| P82 || No connection || (db) dbShort
| Shorts out the waiting timer in FPGA for Ethernet controller initialization (pulled low)
|-
| P83 || CLK_5MHZ_2 || DAC_Clk
| 5 MHz clock output for DAC
|-
| P84 || No connection ||
|
|-
| P85 || AD5535/DIN || DAC_serData
| DAC serial data input (FPGA out -> DAC in)
|-
| P86 || No connection ||
|
|-
| P87 || DGND ||
|
|-
| P88 || AD5535/SYNC || DAC_setISync
|
|-
| P89 || No connection ||
|
|-
| P90 || No connection ||
|
|-
| P91 || DGND ||
|
|-
| P92 || +3.3V ||
|
|-
| P93 || AD7314/CE || SPI_TCE
| Chip enable for temperature sensor
|-
| P94 || No connection ||
|
|-
| P95 || DGND ||
|
|-
| P96 || +3.3V ||
|
|-
| P97 || (former AD7928/DOUT) ||
| '''Erroneously wired ADC SPI bus connection''' Connects to DOUT on ADC
|-
| P98 || AD5535/RESET || DAC_iRst
|Reset pin for DAC
|-
| P99 || DGND ||
| PUDC_B pin - enables pullup resistors on user IO and input-only pins during FPGA config.
|-
| P100 || FPGA/PROG_B || [JTAG]
| Used during FPGA configuration - see Xilinx documentation
|}

== EEPROM ==
To facilitate power-on configuration of the FPGA, the control board includes a Xilinx XCF01S EEPROM. The EEPROM is located to the left of the FPGA, above the JTAG header, and has a 20 pin footprint. The EEPROM is labelled U5.

=== Power Details ===
The EEPROM uses +3.3V exclusively, which it receives from the +3.3V power plane, regulated by VR1.

=== Flashing/Burning/Writing ===
Whatever you call it, this refers to storing data in the EEPROM so that it can configure the FPGA at power-on. The EEPROM is programmed using a JTAG interface and the Xilinx Platform USB II cable. It is important to note that in digital board's JTAG chain, the EEPROM is the first device in the chain, unlike in the Xilinx documentation where it is shown as the second device. This should not affect the operation of the board, but should be reflected in the Xilinx software when writing the EEPROM via JTAG.

=== FPGA Configuration ===
The EEPROM and FPGA are hardwired to use a master serial protocol to transfer the program from the EEPROM to the FPGA. This is the protocol recommended in the Xilinx documentation because it minimizes the number of traces necessary to run between the EEPROM and FPGA. All configuration data is sent over a single trace, FPGA/DIN (pin 1 on EEPROM), controlled by the configuration clock signal (FPGA/CCLK) which is automatically generated by the FPGA at power-on. When configuration is complete, FPGA/DONE (pin 10) is pulled high by the FPGA, and the EEPROM and configuration clock are deactivated.

=== Pinout Table ===
{| cellpadding=3 border=1 |
| '''Pin #'''
| '''Net Name'''
| '''Description'''
|-
| 1
| FPGA/DIN
| Serial data line Carries data from the EEPROM to the FPGA
|-
| 2
| No connection
|
|-
| 3
| FPGA/CCLK
| Configuration clock Auto generated by FPGA at power-on, disabled at end of configuration
|-
| 4
| EEPROM/TDI
| This is the EEPROM's TDI This is the entry point for the onboard JTAG chain
|-
| 5
| FPGA/TMS
| JTAG TMS Connects to both FPGA and EEPROM
|-
| 6
| FPGA/TCK
| JTAG TCK Connects to both FPGA and EEPROM
|-
| 7
| FPGA/PROG_B
| Used during configuration See Xilinx documentation
|-
| 8
| FPGA/INIT_B
| Used during configuration - can be used to intiate reconfiguration of FPGA See Xilinx documentation
|-
| 9
| No connection
|
|-
| 10
| FPGA/DONE
| Indicates completion of FPGA configuration High when complete
|-
| 11
| DGND
|
|-
| 12-16
| No connection
|
|-
| 17
| FPGA/TDI
| This is the EEPROM's TDO/FPGA's TDI
|-
| 18-20
| +3.3V
|
|}

== JTAG Header ==
To write the FPGA's program to the EEPROM, the board employs a JTAG based programming system consistent with Xilinx's recommendations. The system is designed to operate with Xilnx's Platform USB II cable and the flying lead adapter.

===Header Location and Size===
The header consists of 14 pins, 100 mil pitch, just below the EEPROM (U5). The header is labelled P1. The pitch of the pins in the header was erroneously selected to be 100 mil, which is not compatible with Xilinx's JTAG ribbon cable. Therefore, the Xilinx flying lead adapter must be used.

===Power Details===
The JTAG interface is powered by the +3.3V power plane, not by the computer's USB port. Power is supplied through pin 2 of the JTAG header.

===Pinout Table===
Note that the header is positioned on the board rotated 180 degrees from the position in which it is shown in the Xilinx documentation. Care must be taken when connecting the flying leads to ensure they are connected to the right pins. Improper wiring will certainly cause undesired operation, and may cause damage as well. Damage is most likely to occur if one of the flying leads is improperly connected to an odd numbered pin, since it will short to the PCB's ground plane.

{| cellpadding=3 border=1 |
| '''Pin #'''
| '''Net Name'''
| '''Flying Lead'''
| '''Description'''
|-
| 1, 3, 5, 7, 9, 11, 13 (odd pins)
| DGND
| Black (connect to any odd numbered pin)
| Ground pins for signal integrity '''Never connect a flying lead other than the black lead to an odd numbered pin''' Doing so will short to ground and may cause permanent damage if the Platform USB II cable does not have protection against this.
|-
| 2
| +3.3V
| Red/VREF
| Power source for all JTAG logic
|-
| 4
| FPGA/TMS
| Green/TMS
| JTAG TMS - connects to EEPROM and FPGA
|-
| 6
| FPGA/TCK
| Yellow/TCK
| JTAG TCK - connects to EEPROM and FPGA
|-
| 8
| FPGA/TDO
| Purple/TDO
| JTAG boundary scan chain endpoint
|-
| 10
| EEPROM/TDI
| White/TDI
| JTAG boundary scan chain start point
|-
| 12
| No connection
|
| Pin is floating
|-
| 14
| No connection
|
| Pin is floating
|}
''The gray HALT flying lead is not connected.''

===JTAG Overview===
The JTAG interface is clocked by the TCK signal. TCK is generated by the Platform USB II cable, and connects directly from the JTAG header to both the EEPROM and FPGA.

The TMS signal is directly connected to both the EEPROM and FPGA, and is the data line over which JTAG test results (in this case programming results) are sent. TMS is used by only one component at a time.

The TDI/TDO lines form a chain that connects to each JTAG component in series. On the control board, the first point in the chain is the EEPROM's TDI. Next is the EEPROM's TDO, which is the same as the FPGA's TDI. The FPGA's TDO then returns to the JTAG header and the Platform USB II cable.

== DAC ==
The control board uses the Analog Devices AD5535, 32-channel, 200V max, digital to analog converter. This chip has a modified BC-124 BGA footprint and is located above the Eurocard connector at the bottom of the board. It is labelled U3.

=== Power Details ===
The DAC is primarily powered by the +5V power island, regulated by an off-board power supply and extensively decoupled in the area of the DAC. The DAC also requires -5V, and a high voltage as discussed in [[#Power Requirements | Power Requirements]]. Both of these voltages are supplied by an off-board supply and decoupled near the DAC. In addition to these voltage levels, the DAC requires a precise +2.5V reference, created by the shunt-type voltage reference VR4.

=== Setting the Output Range ===
The output range of the DAC is set by the 2.5V reference voltage supplied by VR4. The high voltage power supply must supply at a minimum 50 times this voltage, plus 10. Thus, the high voltage power supply should be at least 135V for DAC to operate properly, even though the SiPMs are expected to need only 40V. If it is convenient to use a lower high voltage, VR4 must be replaced to provide lower reference voltage. The high voltage may then be decreased appropriately. To summarize:

* Max output voltage = VREF*50
* Minimum high voltage supply = VREF*50 + 10
* Acceptable range for VREF
** Min: 1V
** Max: 3.75V (AD5535 datasheet specifies 4V max, but this would require AVCC of 5.25V for the DAC, which is not possible in the current board design)

If relevant, R13 is a 100K resistor.

=== Thermal Diode ===
The DAC has a built in thermal diode. The diode drop from anode to cathode is typically 0.65V at 25°C. It changes at a rate of -2.20mV/°C. The anode of this diode is connected to the +5V power island, and the cathode is connected to a 270K resistor to ground. The voltage between the cathode and the resistor is connected to VIN1 (pin 15) on the ADC.

=== Pinout Table ===
See documentation from Analog Devices.

=== Channel Mapping ===
Due to the layout of the balls on the footprint of the DAC, the DAC's internal channel numbers (which must be referenced by the FPGA) have no correlation to the channel numbers on the amplifier board. This table summarizes the mapping between various pins that belong to each channel.

{| cellpadding=3 border=1 |
| '''DAC Channel #'''
| '''DAC Pin #'''
| '''Digital Board Eurocard Pin #'''
| '''Amplifier Board Eurocard Pin #'''
| '''Amplifier Channel #'''
|-
| 0
| B1
| B3
| B6
| 6
|-
| 1
| A2
| C4
| B7
| 7
|-
| 2
| D1
| B2
| B4
| 4
|-
| 3
| C2
| C3
| B5
| 5
|-
| 4
| B3
| B4
| B8
| 8
|-
| 5
| E2
| C2
| B3
| 3
|-
| 6
| F3
| B1
| B2
| 2
|-
| 7
| A4
| B5
| B10
| 10
|-
| 8
| E4
| C5
| B9
| 9
|-
| 9
| B5
| C6
| B11
| 11
|-
| 10
| F5
| C1
| B1
| 1
|-
| 11
| A6
| C7
| B13
| 13
|-
| 12
| E6
| B6
| B12
| 12
|-
| 13
| B7
| B7
| B14
| 14
|-
| 14
| F7
| C10
| B19
| 19
|-
| 15
| E8
| C8
| B15
| 15
|-
| 16
| A8
| B8
| B16
| 16
|-
| 17
| B9
| C9
| B17
| 17
|-
| 18
| F9
| C16
| B31
| 31
|-
| 19
| E10
| B11
| B22
| 22
|-
| 20
| A10
| B9
| B18
| 18
|-
| 21
| B11
| B10
| B20
| 20
|-
| 22
| C12
| B12
| B24
| 24
|-
| 23
| D13
| B13
| B26
| 26
|-
| 24
| E12
| B14
| B28
| 28
|-
| 25
| A12
| C11
| B21
| 21
|-
| 26
| B13
| C12
| B23
| 23
|-
| 27
| H13
| B16
| B32
| 32
|-
| 28
| G14
| B15
| B30
| 30
|-
| 29
| C14
| C13
| B25
| 25
|-
| 30
| F13
| C15
| B29
| 29
|-
| 31
| E14
| C14
| B27
| 27 DACHEALTH See [[#Channel Descriptions | ADC Channel Descriptions]].
|}

==ADC==
The board includes an Analog Devices AD7928 analog to digital converter. The ADC is located just to the right and slightly below the FPGA. It is labelled U4.

===Power Details===
The ADC is powered by the +5V power island, which is regulated by an off-board power supply and decoupled near the ADC. It also requires a precise (±1%) 2.5V reference to which it compares voltages when converting from analog to digital. Since the +5V power source is not used for comparison, it is flexible and may vary by ±0.25V without affecting ADC precision.

===Setting the Measuring Range===
The measuring range is set programmatically by the FPGA over the SPI bus. The way the ADC is connected on the digital board requires that its measuring range be set to 5V, so the RANGE bit should be set to 1 by the FPGA (see Analog Devices documentation).

===Data Interfacing===
The ADC uses an SPI bus to communicate with the FPGA. This bus is shared with the temperature sensor. SPI related pins include SCLK, CS, DIN, and DOUT. See the Pinout Table below.

===Channel Descriptions===
This table shows what signals are monitored by the ADC.

{| cellpadding=3 border=1 |
| '''ADC Channel #'''
| '''ADC Pin #'''
| '''Net Name'''
| '''Description'''
|-
| VIN0
| 16
| AD7928/VHEALTH
| This net helps to monitor to overall health of power on the board, but is specifically intended to monitor -5V. It's voltage is the output of a resistor divider between the +5 and -5V power supplies, with resistor values of 33.2K, and 100K. Assuming +5V and -5V are both correct, the output of the divider will be +2.51V. A reading of other than 2.51V indicates a problem with one of the power supplies. Problems with the +5V power supply can be ruled out by reading VIN3. Based on the reading from VIN3, the voltage of the -5V supply can be calculated.
|-
| VIN1
| 15
| AD5535/CATHODE
| This is the thermal diode output from the DAC. Should read 4.35V (typical) at 25°C. Drops 2.20mV/°C.
|-
| VIN2
| 14
| +3.3V
| This is the +3.3V power plane. A reading of other than +3.3V indicates a problem with VR1.
|-
| VIN3
| 13
| +5V
| This is the +5V power island. A reading of other than +5V indicates a problem with the +5V power supply.
|-
| VIN4
| 12
| ADC_EXT1
| This trace routes to the backplane via Eurocard pin A7. It is intended to measure the output of thermistor on the amplifier board.
|-
| VIN5
| 11
| +1.2V
| This is the +1.2V power island. This island powers the internal logic of the FPGA. A reading of other than 1.2V indicates a problem with VR3.
|-
| VIN6
| 10
| ADC_EXT2
| This trace routes to the backplane via Eurocard pin A8. It is intended to measure one of the transistor base voltages on the amplifier board.
|-
| VIN7
| 9
| DACHEALTH
| This channel monitors the output of a resistor divider connected to channel 31 of the DAC. The divider consists of three resistors of 200K, 200K, and 10.2K (in order). The ADC reads out the voltage level between the second 200K and then 10.2K resistor. These resistors were selected so that at 200V, the readout voltage will be 4.973V. Since the divider should be linear, the expected voltage at 20V is 0.4973V. Three resistors were used rather than two to avoid exceeding the resistors' power ratings when the DAC is set to its maximum voltage. Note that since this divider will consume up to 484uA of current at 200V, this DAC channel should not be used for anything that might require more than ~200uA of current (the DAC can source 700uA max). The channel is routed to the backplane nonetheless.
|}

===Pinout Table===
{| cellpadding=3 border=1 |
| '''Pin #'''
| '''Net Name'''
| '''Description'''
|-
| 1
| CLK_5MHZ
| SPI clock (SCLK), from FPGA Shared with temperature sensor
|-
| 2
| DIN
| SPI data in, from FPGA Shared with temperature sensor ''Currently wired wrong''
|-
| 3
| CS
| SPI chip select
|-
| 4
| AGND
|
|-
| 5
| +5V
| Power pin
|-
| 6
| +5V
| Power pin
|-
| 7
| AD7928/REF_IN
| +2.5V reference, set by VR2
|-
| 8
| AGND
|
|-
| 9-16
| VIN[7:0]
| See [[#Channel Descriptions | ADC Channel Descriptions]]
|-
| 17
| AGND
|
|-
| 18
| DOUT
| SPI data out ''Currently wired incorrectly''
|-
| 19
| +3.3V
| VDRIVE, powers the SPI logic
|-
| 20
| AGND
|
|}

== Ethernet Controller ==
The board uses a Silicon Laboratories CP2201, 28-pin, ethernet controller. The CP2201 is located just above the FPGA, and is labelled U2.

=== Power Details ===
The CP2201 uses only +3.3V, which is supplied by the +3.3V power plane and regulated by VR1. Appropriate decoupling capacitors can be found near the CP2201.

=== Ethernet Jack ===
To the right of the CP2201 is a Pulse J0011D21NL ethernet jack, labelled J1. This jack has a built-in 1:1 inductive coupling. For best results, connect this jack to a nearby ethernet switch. The jack may also be connected directly to a computer using a crossover cable. Though auto-crossover is not supported by the CP2201, if the computer's NIC supports it, a crossover cable is not necessary to connect directly to a computer.

==== Ethernet Jack Pins ====
These are visible only on the back side of the board. Pin 1 is indicated by a square pad. Pin 8 is the farthest pin from pin 1. Pins are numbered such that the 4 pins closer to the plastic thru-hole connectors are odd (1, 3, 5, 7), and the four pins closer to the CP2201 are are even (2, 4, 6, 8).

* Pin 1: TX+
* Pin 2: AC coupled to DGND
* Pin 3: TX-
* Pin 4: RX+
* Pin 5: AC coupled to DGND
* Pin 6: RX-
* Pin 7: No connection
* Pin 8: DGND (direct)

The two large thru-hole pins (not numbered) connect to the metal shielding on the outside of the jack. These are directly connected to DGND to shield against electrical noise inside the jack.

The two plastic thru-hole pins are not conductive and have no electrical connection. They are present only for structural purposes, presumably to prevent stress on the solder points when an ethernet wire is inserted or removed from the jack.

=== Crystal Oscillator ===
The CP2201 is responsible for driving the 20MHz crystal oscillator. This oscillator clocks both the CP2201 and the FPGA. The crystal oscillator can be found above the right corner of the FPGA. It can be identified by its four surface mount pads and roughly .3" length. It is labelled Y1, though this label is not visible after the oscillator is soldered on. The CP2201 uses an inverting driver to excite the crystal. The output of the crystal is then sent to the CP2201 and the FPGA.

=== Bus Format and Multiplexing ===
The 28-pin CP2201 used on the board only supports multiplexed operation. This means that both address and data information are passed over the same set of 8 traces. Hence, these traces are referred to as the address/data (AD) bus. A separate address line enable (ALE) trace prevents collisions from occuring on these traces. The communication protocol used is the Intel format. See the CP2201's datasheet for more information about this.

=== Pinout Table ===
{| cellpadding=3 border=1 |
| '''Pin #'''
| '''Net Name'''
| '''Description'''
|-
| 1
| CP2201/LA
| Link/activity indicator Routed to backplane but not implemented See CP2201 data sheet for information on how to connect to an LED
|-
| 2
| DGND
| By the data sheet, this pin should be AGND We deliberately set it to DGND to avoid noise on AGND plane
|-
| 3
| +3.3V
| AV+ power pin
|-
| 4
| CP2201/RX-
| Connects to RX- on ethernet jack
|-
| 5
| CP2201/RX+
| Connects to RX+ on ethernet jack
|-
| 6
| CP2201/TX+
| Connects to TX+ on ethernet jack
|-
| 7
| CP2201/TX-
| Connects to TX- on ethernet jack
|-
| 8
| +3.3V
| "VDD" power pin
|-
| 9
| DGND
| "DGND1" per the data sheet
|-
| 10
| CP2201/RESET
| "RST" per the data sheet Connects to FPGA - should be programmatically triggered upon reset of FPGA by RESET jumper
|-
| 11-18
| CP2201/AD[0:7]
| Bits 0-7 of the address/data bus Connect to FPGA
|-
| 19
| +3.3V
| "VDD" power pin
|-
| 20
| DGND
| "DGND2" per the data sheet
|-
| 21
| CP2201/ALE
| Address line enable Connects to FPGA See CP2201 documentation
|-
| 22
| CP2201/RD
| Read strobe for AD bus Connects to FPGA See CP2201 documentation
|-
| 23
| CP2201/WR
| Write strobe for AD bus Connects to FPGA See CP2201 documentation
|-
| 24
| CP2201/CS
| Chip select Connects to FPGA
|-
| 25
| CP2201/INT
| Interrupt request Connects to FPGA
|-
| 26
| DGND
| "MOTEN" (Motorola enable) per the datasheet Tied low to disable Motorola bus format (enable Intel format)
|-
| 27
| CP2201/XTAL2
| Crystal oscillator driver The CP2201 inverts the 20MHz clock signal and feeds it back to the crystal oscillator to encourage larger oscillations
|-
| 28
| FPGA/CLK_IN
| "XTAL1" per the data sheet This is the 20MHz clock input Also connects to the FPGA's clock input
|-
| 29*
| DGND
| This is not a pin but rather the base of the CP2201 package. It is connected to the DGND plane for thermal relief
|}

== Eurocard Connector ==
At the bottom of the control board is the Eurocard connector, labelled P2. The Eurocard connector connects the board to the backplane and also connects the board to its power supplies. The Eurocard has 48 pins arranged in three rows of 16 pins each. Rows B and C are exclusively used to pass SiPM bias voltages to the backplane as described in [[#Channel Mapping | DAC Channel Mapping]]. Here is a table describing the purpose of pins in row A:

=== Row A Pinout Table ===
Note that when viewing the front side of the board with the Eurocard at the bottom, these pins go from right to left. If you look closely at the pins, you will see that pin A1 has a square pad, unlike the round pads of the others.

{| cellpadding=3 border=1 |
| '''Pin #'''
| '''Net Name'''
| '''Description'''
|-
| A1
| CP2201/LA
| Ethernet link/activity indicator routed to backplane
|-
| A2
| High voltage input (+210V max)
| High voltage input for DAC. See [[#DAC | DAC]] for information about what voltage to input here.
|-
| A3
| -5V
| For DAC
|-
| A4
| +5V
| Powers most things on the board
|-
| A5
| AGND
|
|-
| A6
| DGND
|
|-
| A7
| ADC_EXT1
| Connects to ADC to monitor voltages on amplifier board See [[#ADC | ADC]]
|-
| A8
| ADC_EXT2
| Connects to ADC to monitor voltages on amplifier board See [[#ADC | ADC]]
|-
| A9
| No connection
|
|-
| A10
| No connection
|
|-
| A11
| No conneciton
|
|-
| A12
| ID4
| Location identifier bit 4 Used to identify which backplane board is connected to See [[#FPGA | FPGA]]
|-
| A13
| ID3
| Location identifier bit 3 Used to identify which backplane board is connected to See [[#FPGA | FPGA]]
|-
| A14
| ID2
| Location identifier bit 2 Used to identify which backplane board is connected to See [[#FPGA | FPGA]]
|-
| A15
| ID1
| Location identifier bit 1 Used to identify which backplane board is connected to See [[#FPGA | FPGA]]
|-
| A16
| ID0
| Location identifier bit 0 Used to identify which backplane board is connected to See [[#FPGA | FPGA]]
|}

Digital control board documentation

2009-07-22T16:30:34Z

Underwood: /* Channel Mapping */ started adding amplifier channel mapping

This documentation covers the most important things to know while testing the digital control board, including component pinouts, nets, and other information.

== Power Requirements ==
=== Required Voltages ===
All components on the digital board '''except the DAC''' can be tested using only a +5V source. The DAC requires +5V, -5V, and a high voltage corresponding to 10V higher than the maximum desired DAC output voltage (see [[#Setting the Output Range | Setting the Output Range]]). Digital and analog grounds must be connected as well before any testing takes place.

=== Power Pins ===
Power shall be connected to the board as follows:
{| cellpadding=3 border=1 |
| '''Voltage'''
| '''Eurocard Pin'''
|-
| DGND
| A6
|-
| AGND
| A5
|-
| +5V
| A4
|-
| -5V
| A3
|-
| High voltage (DAC max out +10)
| A2
|}

=== Power Supply Sequencing ===
The control board is designed such that voltages may be supplied in any order so long as AGND and DGND are connected properly. However, for initial testing, the preferred order for powering up the board is as follows:

# Ensure AGND/DGND are connected/grounded
# +5V
# -5V
# High voltage

== FPGA ==
The control board uses a Xilinx XC3S50A VQ100 FPGA. It has a 100 pin footprint and is located in the center of the control board.

=== Power Details ===
The FPGA is powered by the 3.3V power plane, which is regulated by VR1. The FPGA also obtains 1.2V for its internal logic from a 1.2V power island, regulated by VR3.

=== Logic Standard ===
The Xilinx XC3S50A supports several different digital logic standards. The control board is hard wired such that the FPGA will use a '''3.3V CMOS''' logic standard.

=== Pinout Table ===
{| cellpadding=3 border=1 |
| '''Pin #''' || '''Net Name''' || '''Signal Name'''
| '''Description'''
|-
| P1 || FPGA/TMS || [JTAG]
| JTAG
|-
| P2 || FPGA/TDI || [JTAG]
| JTAG
|-
| P3 || AD7928/CS || SPI_A_iCS
| SPI chip select for ADC
|-
| P4 || SPI || SDO
| '''Erroneously wired SPI bus trace''' Connects to SDO on temp. sensor and DIN on ADC
|-
| P5 || CLK_5MHZ || SPI_SCLK
| 5 MHz clock output for SPI bus (ADC and temp. sensor)
|-
| P6 || No connection ||
|
|-
| P7 || No connection ||
|
|-
| P8 || DGND ||
|
|-
| P9 || No connection ||
|
|-
| P10 || No connection ||
|
|-
| P11 || +3.3V ||
|
|-
| P12 || No connection ||
|
|-
| P13 || No connection ||
|
|-
| P14 || DGND ||
|
|-
| P15 || No connection ||
|
|-
| P16 || No connection ||
|
|-
| P17 || +1.2V ||
|
|-
| P18 || DGND ||
|
|-
| P19 || No connection ||
|
|-
| P20 || No connection ||
|
|-
| P21 || No connection ||
|
|-
| P22 || +3.3V ||
|
|-
| P23 || DGND || [M1: JTAG prog. config.]
|
|-
| P24 || DGND || [M2: JTAG prog. config.]
|
|-
| P25 || DGND || [M0: JTAG prog. config.]
|
|-
| P26 || +3.3V ||
|
|-
| P27 || FPGA/CLK_IN || fClk
| 20 MHz clock input from crystal oscillator
|-
| P28 || No connection ||
|
|-
| P29 || No connection || (db) state_Q(0)
|
|-
| P30 || No connection ||
|
|-
| P31 || No connection || (db) state_Q(1)
|
|-
| P32 || No connection ||
|
|-
| P33 || No connection || (db) state_Q(2)
|
|-
| P34 || No connection ||
|
|-
| P35 || CP2201/INT || Eth_iINT
| Ethernet controller interrupt
|-
| P36 || MASTER_RESET || Rst
| Connects to RESET jumper in upper left of board (active-low, externally pulled up)
|-
| P37 || (manually wired) || fClk_out
|
|-
| P38 || +1.2V ||
|
|-
| P39 || No connection ||
|
|-
| P40 || CP2201/CS || iCS
| Chip select for ethernet controller
|-
| P41 || CP2201/WR || iWR
| Write enable for ethernet controller
|-
| P42 || DGND ||
|
|-
| P43 || CP2201/RD || iRD
| Read enable for ethernet controller
|-
| P44 || CP2201/ALE || ALE
| Address line enable for ethernet controller
|-
| P45 || +3.3V ||
|
|-
| P46 || CP2201/RESET || Eth_iRst
| Reset pin for ethernet controller
|-
| P47 || DGND ||
|
|-
| P48 || FPGA/INIT_B || [JTAG]
| Used during FPGA configuration - see Xilinx documentation
|-
| P49 || CP2201/AD0 || AD(0)
| Ethernet controller address/data bus, bit 0
|-
| P50 || CP2201/AD1 || AD(1)
| Ethernet controller address/data bus, bit 1
|-
| P51 || FPGA/DIN || [JTAG]
| Serial data input from EEPROM for configuration
|-
| P52 || CP2201/AD2 || AD(2)
| Ethernet controller address/data bus, bit 2
|-
| P53 || FPGA/CCLK || [JTAG]
| Configuration clock (signal generated by FPGA at power on to clock the configuration process) See Xilinx documentation
|-
| P54 || FPGA/DONE || [JTAG]
| Gives configuration status - see Xilinx documentation
|-
| P55 || +3.3V ||
|
|-
| P56 || CP2201/AD3 || AD(3)
| Ethernet controller address/data bus, bit 3
|-
| P57 || CP2201/AD4 || AD(4)
| Ethernet controller address/data bus, bit 4
|-
| P58 || DGND ||
|
|-
| P59 || CP2201/AD5 || AD(5)
| Ethernet controller address/data bus, bit 5
|-
| P60 || CP2201/AD6 || AD(6)
| Ethernet controller address/date bus, bit 6
|-
| P61 || CP2201/AD7 || AD(7)
| Ethernet controller address/date bus, bit 7
|-
| P62 || No connection ||
|
|-
| P63 || DGND ||
|
|-
| P64 || No connection ||
|
|-
| P65 || No connection ||
|
|-
| P66 || +1.2V ||
|
|-
| P67 || +3.3V ||
|
|-
| P68 || +3.3V ||
|
|-
| P69 || DGND ||
|
|-
| P70 || ID3 || LocStamp(3)
| Backplane location identifier jumper, pins 3 & 4 Active-low, FPGA should pull high
|-
| P71 || ID2 || LocStamp(2)
| Backplane location identifier jumper, pins 5 & 6 Active-low, FPGA should pull high
|-
| P72 || ID1 || LocStamp(1)
| Backplane location identifier jumper, pins 7 & 8 Active-low, FPGA should pull high
|-
| P73 || ID0 || LocStamp(0)
| Backplane location identifier jumper, pins 9 & 10 Active-low, FPGA should pull high
|-
| P74 || DGND ||
|
|-
| P75 || FPGA/TDO || [JTAG]
| JTAG
|-
| P76 || FPGA/TCK || [JTAG]
| JTAG
|-
| P77 || ID4 || LocStamp(4)
| Backplane location identifier jumper, pins 1 & 2 Active-low, FPGA should pull high
|-
| P78 || No connection ||
|
|-
| P79 || +3.3V ||
|
|-
| P80 || DGND ||
|
|-
| P81 || +1.2V ||
|
|-
| P82 || No connection || (db) dbShort
| Shorts out the waiting timer in FPGA for Ethernet controller initialization (pulled low)
|-
| P83 || CLK_5MHZ_2 || DAC_Clk
| 5 MHz clock output for DAC
|-
| P84 || No connection ||
|
|-
| P85 || AD5535/DIN || DAC_serData
| DAC serial data input (FPGA out -> DAC in)
|-
| P86 || No connection ||
|
|-
| P87 || DGND ||
|
|-
| P88 || AD5535/SYNC || DAC_setISync
|
|-
| P89 || No connection ||
|
|-
| P90 || No connection ||
|
|-
| P91 || DGND ||
|
|-
| P92 || +3.3V ||
|
|-
| P93 || AD7314/CE || SPI_TCE
| Chip enable for temperature sensor
|-
| P94 || (''needs manual connection?''') || SPI_iRst_out
|
|-
| P95 || DGND ||
|
|-
| P96 || +3.3V ||
|
|-
| P97 || (former AD7928/DOUT) ||
| '''Erroneously wired ADC SPI bus connection''' Connects to DOUT on ADC
|-
| P98 || AD5535/RESET || DAC_iRst
|Reset pin for DAC
|-
| P99 || DGND ||
| PUDC_B pin - enables pullup resistors on user IO and input-only pins during FPGA config.
|-
| P100 || FPGA/PROG_B || [JTAG]
| Used during FPGA configuration - see Xilinx documentation
|}

== EEPROM ==
To facilitate power-on configuration of the FPGA, the control board includes a Xilinx XCF01S EEPROM. The EEPROM is located to the left of the FPGA, above the JTAG header, and has a 20 pin footprint. The EEPROM is labelled U5.

=== Power Details ===
The EEPROM uses +3.3V exclusively, which it receives from the +3.3V power plane, regulated by VR1.

=== Flashing/Burning/Writing ===
Whatever you call it, this refers to storing data in the EEPROM so that it can configure the FPGA at power-on. The EEPROM is programmed using a JTAG interface and the Xilinx Platform USB II cable. It is important to note that in digital board's JTAG chain, the EEPROM is the first device in the chain, unlike in the Xilinx documentation where it is shown as the second device. This should not affect the operation of the board, but should be reflected in the Xilinx software when writing the EEPROM via JTAG.

=== FPGA Configuration ===
The EEPROM and FPGA are hardwired to use a master serial protocol to transfer the program from the EEPROM to the FPGA. This is the protocol recommended in the Xilinx documentation because it minimizes the number of traces necessary to run between the EEPROM and FPGA. All configuration data is sent over a single trace, FPGA/DIN (pin 1 on EEPROM), controlled by the configuration clock signal (FPGA/CCLK) which is automatically generated by the FPGA at power-on. When configuration is complete, FPGA/DONE (pin 10) is pulled high by the FPGA, and the EEPROM and configuration clock are deactivated.

=== Pinout Table ===
{| cellpadding=3 border=1 |
| '''Pin #'''
| '''Net Name'''
| '''Description'''
|-
| 1
| FPGA/DIN
| Serial data line Carries data from the EEPROM to the FPGA
|-
| 2
| No connection
|
|-
| 3
| FPGA/CCLK
| Configuration clock Auto generated by FPGA at power-on, disabled at end of configuration
|-
| 4
| EEPROM/TDI
| This is the EEPROM's TDI This is the entry point for the onboard JTAG chain
|-
| 5
| FPGA/TMS
| JTAG TMS Connects to both FPGA and EEPROM
|-
| 6
| FPGA/TCK
| JTAG TCK Connects to both FPGA and EEPROM
|-
| 7
| FPGA/PROG_B
| Used during configuration See Xilinx documentation
|-
| 8
| FPGA/INIT_B
| Used during configuration - can be used to intiate reconfiguration of FPGA See Xilinx documentation
|-
| 9
| No connection
|
|-
| 10
| FPGA/DONE
| Indicates completion of FPGA configuration High when complete
|-
| 11
| DGND
|
|-
| 12-16
| No connection
|
|-
| 17
| FPGA/TDI
| This is the EEPROM's TDO/FPGA's TDI
|-
| 18-20
| +3.3V
|
|}

== JTAG Header ==
To write the FPGA's program to the EEPROM, the board employs a JTAG based programming system consistent with Xilinx's recommendations. The system is designed to operate with Xilnx's Platform USB II cable and the flying lead adapter.

===Header Location and Size===
The header consists of 14 pins, 100 mil pitch, just below the EEPROM (U5). The header is labelled P1. The pitch of the pins in the header was erroneously selected to be 100 mil, which is not compatible with Xilinx's JTAG ribbon cable. Therefore, the Xilinx flying lead adapter must be used.

===Power Details===
The JTAG interface is powered by the +3.3V power plane, not by the computer's USB port. Power is supplied through pin 2 of the JTAG header.

===Pinout Table===
Note that the header is positioned on the board rotated 180 degrees from the position in which it is shown in the Xilinx documentation. Care must be taken when connecting the flying leads to ensure they are connected to the right pins. Improper wiring will certainly cause undesired operation, and may cause damage as well. Damage is most likely to occur if one of the flying leads is improperly connected to an odd numbered pin, since it will short to the PCB's ground plane.

{| cellpadding=3 border=1 |
| '''Pin #'''
| '''Net Name'''
| '''Flying Lead'''
| '''Description'''
|-
| 1, 3, 5, 7, 9, 11, 13 (odd pins)
| DGND
| Black (connect to any odd numbered pin)
| Ground pins for signal integrity '''Never connect a flying lead other than the black lead to an odd numbered pin''' Doing so will short to ground and may cause permanent damage if the Platform USB II cable does not have protection against this.
|-
| 2
| +3.3V
| Red/VREF
| Power source for all JTAG logic
|-
| 4
| FPGA/TMS
| Green/TMS
| JTAG TMS - connects to EEPROM and FPGA
|-
| 6
| FPGA/TCK
| Yellow/TCK
| JTAG TCK - connects to EEPROM and FPGA
|-
| 8
| FPGA/TDO
| Purple/TDO
| JTAG boundary scan chain endpoint
|-
| 10
| EEPROM/TDI
| White/TDI
| JTAG boundary scan chain start point
|-
| 12
| No connection
|
| Pin is floating
|-
| 14
| No connection
|
| Pin is floating
|}
''The gray HALT flying lead is not connected.''

===JTAG Overview===
The JTAG interface is clocked by the TCK signal. TCK is generated by the Platform USB II cable, and connects directly from the JTAG header to both the EEPROM and FPGA.

The TMS signal is directly connected to both the EEPROM and FPGA, and is the data line over which JTAG test results (in this case programming results) are sent. TMS is used by only one component at a time.

The TDI/TDO lines form a chain that connects to each JTAG component in series. On the control board, the first point in the chain is the EEPROM's TDI. Next is the EEPROM's TDO, which is the same as the FPGA's TDI. The FPGA's TDO then returns to the JTAG header and the Platform USB II cable.

== DAC ==
The control board uses the Analog Devices AD5535, 32-channel, 200V max, digital to analog converter. This chip has a modified BC-124 BGA footprint and is located above the Eurocard connector at the bottom of the board. It is labelled U3.

=== Power Details ===
The DAC is primarily powered by the +5V power island, regulated by an off-board power supply and extensively decoupled in the area of the DAC. The DAC also requires -5V, and a high voltage as discussed in [[#Power Requirements | Power Requirements]]. Both of these voltages are supplied by an off-board supply and decoupled near the DAC. In addition to these voltage levels, the DAC requires a precise +2.5V reference, created by the shunt-type voltage reference VR4.

=== Setting the Output Range ===
The output range of the DAC is set by the 2.5V reference voltage supplied by VR4. The high voltage power supply must supply at a minimum 50 times this voltage, plus 10. Thus, the high voltage power supply should be at least 135V for DAC to operate properly, even though the SiPMs are expected to need only 40V. If it is convenient to use a lower high voltage, VR4 must be replaced to provide lower reference voltage. The high voltage may then be decreased appropriately. To summarize:

* Max output voltage = VREF*50
* Minimum high voltage supply = VREF*50 + 10
* Acceptable range for VREF
** Min: 1V
** Max: 3.75V (AD5535 datasheet specifies 4V max, but this would require AVCC of 5.25V for the DAC, which is not possible in the current board design)

If relevant, R13 is a 100K resistor.

=== Thermal Diode ===
The DAC has a built in thermal diode. The diode drop from anode to cathode is typically 0.65V at 25°C. It changes at a rate of -2.20mV/°C. The anode of this diode is connected to the +5V power island, and the cathode is connected to a 270K resistor to ground. The voltage between the cathode and the resistor is connected to VIN1 (pin 15) on the ADC.

=== Pinout Table ===
See documentation from Analog Devices.

=== Channel Mapping ===
Due to the layout of the balls on the footprint of the DAC, the DAC's internal channel numbers (which must be referenced by the FPGA) have no correlation to the channel numbers on the amplifier board. This table summarizes the mapping between various pins that belong to each channel.

{| cellpadding=3 border=1 |
| '''DAC Channel #'''
| '''DAC Pin #'''
| '''Digital Board Eurocard Pin #'''
| '''Amplifier Board Eurocard Pin #'''
| '''Amplifier Channel #'''
|-
| 0
| B1
| B3
| B6
| 6
|-
| 1
| A2
| C4
| B7
| 7
|-
| 2
| D1
| B2
| B4
| 4
|-
| 3
| C2
| C3
| B5
| 5
|-
| 4
| B3
| B4
| B8
| 8
|-
| 5
| E2
| C2
| B3
| 3
|-
| 6
| F3
| B1
| B2
| 2
|-
| 7
| A4
| B5
| B10
| 10
|-
| 8
| E4
| C5
| B9
| 9
|-
| 9
| B5
| C6
| B11
| 11
|-
| 10
| F5
| C1
| B1
| 1
|-
| 11
| A6
| C7
| B13
| 13
|-
| 12
| E6
| B6
| B12
| 12
|-
| 13
| B7
| B7
| B14
| B14
|-
| 14
| F7
| C10
| B19
| 19
|-
| 15
| E8
| C8
| B15
| 15
|-
| 16
| A8
| B8
|
|
|-
| 17
| B9
| C9
|
|
|-
| 18
| F9
| C16
|
|
|-
| 19
| E10
| B11
|
|
|-
| 20
| A10
| B9
|
|
|-
| 21
| B11
| B10
|
|
|-
| 22
| C12
| B12
|
|
|-
| 23
| D13
| B13
|
|
|-
| 24
| E12
| B14
|
|
|-
| 25
| A12
| C11
|
|
|-
| 26
| B13
| C12
|
|
|-
| 27
| H13
| B16
|
|
|-
| 28
| G14
| B15
|
|
|-
| 29
| C14
| C13
|
|
|-
| 30
| F13
| C15
|
|
|-
| 31
| E14
| C14
|
| DACHEALTH See [[#Channel Descriptions | ADC Channel Descriptions]].
|}

==ADC==
The board includes an Analog Devices AD7928 analog to digital converter. The ADC is located just to the right and slightly below the FPGA. It is labelled U4.

===Power Details===
The ADC is powered by the +5V power island, which is regulated by an off-board power supply and decoupled near the ADC. It also requires a precise (±1%) 2.5V reference to which it compares voltages when converting from analog to digital. Since the +5V power source is not used for comparison, it is flexible and may vary by ±0.25V without affecting ADC precision.

===Setting the Measuring Range===
The measuring range is set programmatically by the FPGA over the SPI bus. The way the ADC is connected on the digital board requires that its measuring range be set to 5V, so the RANGE bit should be set to 1 by the FPGA (see Analog Devices documentation).

===Data Interfacing===
The ADC uses an SPI bus to communicate with the FPGA. This bus is shared with the temperature sensor. SPI related pins include SCLK, CS, DIN, and DOUT. See the Pinout Table below.

===Channel Descriptions===
This table shows what signals are monitored by the ADC.

{| cellpadding=3 border=1 |
| '''ADC Channel #'''
| '''ADC Pin #'''
| '''Net Name'''
| '''Description'''
|-
| VIN0
| 16
| AD7928/VHEALTH
| This net helps to monitor to overall health of power on the board, but is specifically intended to monitor -5V. It's voltage is the output of a resistor divider between the +5 and -5V power supplies, with resistor values of 33.2K, and 100K. Assuming +5V and -5V are both correct, the output of the divider will be +2.51V. A reading of other than 2.51V indicates a problem with one of the power supplies. Problems with the +5V power supply can be ruled out by reading VIN3. Based on the reading from VIN3, the voltage of the -5V supply can be calculated.
|-
| VIN1
| 15
| AD5535/CATHODE
| This is the thermal diode output from the DAC. Should read 4.35V (typical) at 25°C. Drops 2.20mV/°C.
|-
| VIN2
| 14
| +3.3V
| This is the +3.3V power plane. A reading of other than +3.3V indicates a problem with VR1.
|-
| VIN3
| 13
| +5V
| This is the +5V power island. A reading of other than +5V indicates a problem with the +5V power supply.
|-
| VIN4
| 12
| ADC_EXT1
| This trace routes to the backplane via Eurocard pin A7. It is intended to measure the output of thermistor on the amplifier board.
|-
| VIN5
| 11
| +1.2V
| This is the +1.2V power island. This island powers the internal logic of the FPGA. A reading of other than 1.2V indicates a problem with VR3.
|-
| VIN6
| 10
| ADC_EXT2
| This trace routes to the backplane via Eurocard pin A8. It is intended to measure one of the transistor base voltages on the amplifier board.
|-
| VIN7
| 9
| DACHEALTH
| This channel monitors the output of a resistor divider connected to channel 31 of the DAC. The divider consists of three resistors of 200K, 200K, and 10.2K (in order). The ADC reads out the voltage level between the second 200K and then 10.2K resistor. These resistors were selected so that at 200V, the readout voltage will be 4.973V. Since the divider should be linear, the expected voltage at 20V is 0.4973V. Three resistors were used rather than two to avoid exceeding the resistors' power ratings when the DAC is set to its maximum voltage. Note that since this divider will consume up to 484uA of current at 200V, this DAC channel should not be used for anything that might require more than ~200uA of current (the DAC can source 700uA max). The channel is routed to the backplane nonetheless.
|}

===Pinout Table===
{| cellpadding=3 border=1 |
| '''Pin #'''
| '''Net Name'''
| '''Description'''
|-
| 1
| CLK_5MHZ
| SPI clock (SCLK), from FPGA Shared with temperature sensor
|-
| 2
| DIN
| SPI data in, from FPGA Shared with temperature sensor ''Currently wired wrong''
|-
| 3
| CS
| SPI chip select
|-
| 4
| AGND
|
|-
| 5
| +5V
| Power pin
|-
| 6
| +5V
| Power pin
|-
| 7
| AD7928/REF_IN
| +2.5V reference, set by VR2
|-
| 8
| AGND
|
|-
| 9-16
| VIN[7:0]
| See [[#Channel Descriptions | ADC Channel Descriptions]]
|-
| 17
| AGND
|
|-
| 18
| DOUT
| SPI data out ''Currently wired incorrectly''
|-
| 19
| +3.3V
| VDRIVE, powers the SPI logic
|-
| 20
| AGND
|
|}

== Ethernet Controller ==
The board uses a Silicon Laboratories CP2201, 28-pin, ethernet controller. The CP2201 is located just above the FPGA, and is labelled U2.

=== Power Details ===
The CP2201 uses only +3.3V, which is supplied by the +3.3V power plane and regulated by VR1. Appropriate decoupling capacitors can be found near the CP2201.

=== Ethernet Jack ===
To the right of the CP2201 is a Pulse J0011D21NL ethernet jack, labelled J1. This jack has a built-in 1:1 inductive coupling. For best results, connect this jack to a nearby ethernet switch. The jack may also be connected directly to a computer using a crossover cable. Though auto-crossover is not supported by the CP2201, if the computer's NIC supports it, a crossover cable is not necessary to connect directly to a computer.

==== Ethernet Jack Pins ====
These are visible only on the back side of the board. Pin 1 is indicated by a square pad. Pin 8 is the farthest pin from pin 1. Pins are numbered such that the 4 pins closer to the plastic thru-hole connectors are odd (1, 3, 5, 7), and the four pins closer to the CP2201 are are even (2, 4, 6, 8).

* Pin 1: TX+
* Pin 2: AC coupled to DGND
* Pin 3: TX-
* Pin 4: RX+
* Pin 5: AC coupled to DGND
* Pin 6: RX-
* Pin 7: No connection
* Pin 8: DGND (direct)

The two large thru-hole pins (not numbered) connect to the metal shielding on the outside of the jack. These are directly connected to DGND to shield against electrical noise inside the jack.

The two plastic thru-hole pins are not conductive and have no electrical connection. They are present only for structural purposes, presumably to prevent stress on the solder points when an ethernet wire is inserted or removed from the jack.

=== Crystal Oscillator ===
The CP2201 is responsible for driving the 20MHz crystal oscillator. This oscillator clocks both the CP2201 and the FPGA. The crystal oscillator can be found above the right corner of the FPGA. It can be identified by its four surface mount pads and roughly .3" length. It is labelled Y1, though this label is not visible after the oscillator is soldered on. The CP2201 uses an inverting driver to excite the crystal. The output of the crystal is then sent to the CP2201 and the FPGA.

=== Bus Format and Multiplexing ===
The 28-pin CP2201 used on the board only supports multiplexed operation. This means that both address and data information are passed over the same set of 8 traces. Hence, these traces are referred to as the address/data (AD) bus. A separate address line enable (ALE) trace prevents collisions from occuring on these traces. The communication protocol used is the Intel format. See the CP2201's datasheet for more information about this.

=== Pinout Table ===
{| cellpadding=3 border=1 |
| '''Pin #'''
| '''Net Name'''
| '''Description'''
|-
| 1
| CP2201/LA
| Link/activity indicator Routed to backplane but not implemented See CP2201 data sheet for information on how to connect to an LED
|-
| 2
| DGND
| By the data sheet, this pin should be AGND We deliberately set it to DGND to avoid noise on AGND plane
|-
| 3
| +3.3V
| AV+ power pin
|-
| 4
| CP2201/RX-
| Connects to RX- on ethernet jack
|-
| 5
| CP2201/RX+
| Connects to RX+ on ethernet jack
|-
| 6
| CP2201/TX+
| Connects to TX+ on ethernet jack
|-
| 7
| CP2201/TX-
| Connects to TX- on ethernet jack
|-
| 8
| +3.3V
| "VDD" power pin
|-
| 9
| DGND
| "DGND1" per the data sheet
|-
| 10
| CP2201/RESET
| "RST" per the data sheet Connects to FPGA - should be programmatically triggered upon reset of FPGA by RESET jumper
|-
| 11-18
| CP2201/AD[0:7]
| Bits 0-7 of the address/data bus Connect to FPGA
|-
| 19
| +3.3V
| "VDD" power pin
|-
| 20
| DGND
| "DGND2" per the data sheet
|-
| 21
| CP2201/ALE
| Address line enable Connects to FPGA See CP2201 documentation
|-
| 22
| CP2201/RD
| Read strobe for AD bus Connects to FPGA See CP2201 documentation
|-
| 23
| CP2201/WR
| Write strobe for AD bus Connects to FPGA See CP2201 documentation
|-
| 24
| CP2201/CS
| Chip select Connects to FPGA
|-
| 25
| CP2201/INT
| Interrupt request Connects to FPGA
|-
| 26
| DGND
| "MOTEN" (Motorola enable) per the datasheet Tied low to disable Motorola bus format (enable Intel format)
|-
| 27
| CP2201/XTAL2
| Crystal oscillator driver The CP2201 inverts the 20MHz clock signal and feeds it back to the crystal oscillator to encourage larger oscillations
|-
| 28
| FPGA/CLK_IN
| "XTAL1" per the data sheet This is the 20MHz clock input Also connects to the FPGA's clock input
|-
| 29*
| DGND
| This is not a pin but rather the base of the CP2201 package. It is connected to the DGND plane for thermal relief
|}

== Eurocard Connector ==
At the bottom of the control board is the Eurocard connector, labelled P2. The Eurocard connector connects the board to the backplane and also connects the board to its power supplies. The Eurocard has 48 pins arranged in three rows of 16 pins each. Rows B and C are exclusively used to pass SiPM bias voltages to the backplane as described in [[#Channel Mapping | DAC Channel Mapping]]. Here is a table describing the purpose of pins in row A:

=== Row A Pinout Table ===
Note that when viewing the front side of the board with the Eurocard at the bottom, these pins go from right to left. If you look closely at the pins, you will see that pin A1 has a square pad, unlike the round pads of the others.

{| cellpadding=3 border=1 |
| '''Pin #'''
| '''Net Name'''
| '''Description'''
|-
| A1
| CP2201/LA
| Ethernet link/activity indicator routed to backplane
|-
| A2
| High voltage input (+210V max)
| High voltage input for DAC. See [[#DAC | DAC]] for information about what voltage to input here.
|-
| A3
| -5V
| For DAC
|-
| A4
| +5V
| Powers most things on the board
|-
| A5
| AGND
|
|-
| A6
| DGND
|
|-
| A7
| ADC_EXT1
| Connects to ADC to monitor voltages on amplifier board See [[#ADC | ADC]]
|-
| A8
| ADC_EXT2
| Connects to ADC to monitor voltages on amplifier board See [[#ADC | ADC]]
|-
| A9
| No connection
|
|-
| A10
| No connection
|
|-
| A11
| No conneciton
|
|-
| A12
| ID4
| Location identifier bit 4 Used to identify which backplane board is connected to See [[#FPGA | FPGA]]
|-
| A13
| ID3
| Location identifier bit 3 Used to identify which backplane board is connected to See [[#FPGA | FPGA]]
|-
| A14
| ID2
| Location identifier bit 2 Used to identify which backplane board is connected to See [[#FPGA | FPGA]]
|-
| A15
| ID1
| Location identifier bit 1 Used to identify which backplane board is connected to See [[#FPGA | FPGA]]
|-
| A16
| ID0
| Location identifier bit 0 Used to identify which backplane board is connected to See [[#FPGA | FPGA]]
|}

Digital control board debugging notes

2009-06-22T16:10:11Z

Underwood:

This page contains a list of all currently known problems with the digital control board.

== No Power on +1.2V Power Island ==
=== Description ===
The +1.2V island was found to be at 0.0V rather than +1.2V.

=== Cause ===
The +5V input (pin 2) on the +1.2V voltage regulator, VR3 (Analog Devices ADP1715), was not connected.

=== Solution ===
A dab of solder was used to short pins 1 and 2 on VR3. Pin 1 is an active high chip enable pin, which is permanently tied to +5V.

=== Other Details and Current Status ===
This problem was due to an unconnected pin in the original schematics. The schematics have '''not yet been updated''' to reflect the solution.

* June 22, 2009: One board has been modified to correct this problem.

== SPI Bus Miswired ==
=== Description ===
The SPI bus to the temperature sensor and the ADC is not wired correctly.

=== Cause ===
FPGA pin 5 (labelled SPI) is connected to DIN on the ADC, and DOUT of the temperature sensor. FPGA pin 96 (labelled AD7928/DOUT) is connected to DOUT on the ADC. SPI designates that all slave device DOUT traces be connected together. Chip select and HiZ logic are used to prevent devices from fighting over the signal line.

=== Solution ===
DOUT on the temperature sensor should be connected to DOUT on the ADC and pin 96 on the FPGA. This can be accomplished by cutting the existing DOUT trace near the temperature sensor and soldering a wire to DOUT on the ADC. DIN on the ADC can then be connected with a wire to pin 5 on the FPGA, or if possible, simply left connected using the original trace. In this configuration, pin 5 on the FPGA will become the SPI MOSI (master out, slave in) line, and pin 96 on the FPGA will become the SPI MISO (master in, slave out) line. DIN on the temperature sensor is left tied to ground, since it is not needed.

=== Other Details and Current Status ===
This problem was due to errors int he original schematics. The schematics have '''not yet been updated''' to reflect the solution.

* June 22, 2009: This modification has not yet been implemented.

Design and prototyping of SiPM electronics

2009-06-22T15:47:52Z

Underwood: /* Current Progress */ added link to debugging notes

[[Image:TaggerBoards.png|thumb|445px|Basic Tagger Microscope control/wiring scheme]]

The pages listed here describe the work in electronics undertaken to support Silicon Photomultiplier (SiPM) based readout of the Tagger Microscope for JLab Hall-D and the GlueX experiment in particular. The working design concept for the Tagger's readout involves an array of PCB boards with SiPMs and their amplifiers, summing circuits etc. suspended in a light-tight box out of the plane of incoming electrons. Each of these "amplifier" or "analog" boards are connected across a light-sealing bus board to a "control" or "digital" board. The latter set of boards principally contain bias voltage control circuitry and an architecture that allows Ethernet-based communication with a controlling PC. An added advantage of this two-tier design is the ease with which the tagger can be wired without introducing light leaks: the SiPM signals are passed into a chamber more tolerant of ambient light. (The coaxial cables can then take the SiPM signals off digital boards.) The adjacent diagram outlines this scheme.

== Amplifier Boards ==

=== Analog Amplifier ===

The suitability of commercially-available SiPMs have been evaluated with "AMP_0604" amplifier by [http://www.photonique.ch/ Photonique].

The following pages provide analysis of this circuit:
* [[SiPM Amplifier]] - analog amplifier circuit supplied by for use with the SiPMs.
** [[MATLAB amplifier in detail]] - more information regarding the implementation of the MATLAB-based simulation of the amplifier circuit.

A similar amplifier circuit is necessary replicated for each SiPM in the tagger microscope. However, microscope readout calls for somewhat different design requirements and operating condition constraints. The following is a brief outline the demands on the amplifier design:
* adjustable gain, ranging from readout of hundreds of pixels to calibration with single-photon counting
* less than 15% gain variability on transistor <math>\beta</math> (<math>h_{FE}</math>) parameter
* summing circuit to pool SiPM signals in groups of 5
* minimized pulse duration
* minimized power consumption

A full discussion of these along with steps taken to meet the new design goals are outlined in:
* [[SiPM Amplifier Optimization]]
** [[SiPM Amplifier Signal Analysis]]
** [[SiPM Amplifier Components]]

== Digital Control Boards ==

=== Current Progress ===
The PCB layout of the digital control board is complete. Three prototype identical prototype boards are currently being tested. Documentation for these boards can be found here: [[Digital control board documentation]]

For debugging notes, including all currently known problems, see [[Digital control board debugging notes]].

=== Design Tree ===

* [[SiPM digital control board]] - design of the digital PCB for controlling the SiPMs.
** Programming the FPGA
*** [[Programming the Ethernet controller]] - discussion of the design for the core of the FPGA which handles the complex needs of the FPGA - Ethernet controller chip interface.
**** [[Reset and Initialization]] - discussion of the design for the reset and initialization part of the core
**** [[Ethernet packets]] - a detail of the packets we intend to use on our network.
*** [[Programming the DAC]] - discussion of the design for the DAC.
*** [[Programming the SPI]] - discussion of the hybrid module that controls both the ADC and the temperature sensor over a single SPI bus. This design incorporates the (now obsolete) predecessor modules:
**** [[Programming the temperature sensor]] - discussion of the design for the temperature sensor.
**** [[Programming the ADC]] - discussion of the design for the ADC.

== Resources ==

* Presentation on FPGA programming [http://zeus.phys.uconn.edu/~senderovich/GlueX/Tagger/Reports/FPGAtalk-4-17-2008/FPGAdesign.ppt PPT] [http://zeus.phys.uconn.edu/~senderovich/GlueX/Tagger/Reports/FPGAtalk-4-17-2008/FPGAdesign.pdf PDF]
* [http://www.vhdl-online.de/tutorial/ VHDL Tutorial]
* [http://tams-www.informatik.uni-hamburg.de/research/vlsi/vhdl/index.php?content=03-documentation The Hamburg VHDL Archive]

=== VHDL Overview ===

* [[VHDL tutorial]] - a brief guide to VHDL design with a design example; the introduction and core of the tutorial.
** [[VHDL: Where to start]] - section one of the tutorial, focusing on preparing your design for coding.
** [[VHDL: Enter the code monkey]] - section two of the tutorial, focusing on outlining the framework of your code.
** [[VHDL: The real code]] - section three of the tutorial, focusing on coding the body of your design.
** [[VHDL: Xilinx ISE]] - section four of the tutorial, focusing on using the development environment.

== To-do list ==

* Upload [[Programming the ADC|ADC module]] block diagrams
* <s>Combine [[Programming the ADC|ADC]] & [[Programming the temperature sensor|temperature sensor]] into single "SPI" module</s>
[[Programming_the_Ethernet_controller#.28000.29_Reset_Cycle|Ethernet module]]
* <s>Complete [[Programming the Ethernet controller|Ethernet controller module]]</s>
** <s>Registers</s>
** <s>Idler</s>
** <s>Reader</s>
** <s>Querier</s>
** <s>Programmer</s>
** <s>Transmitter</s>
** <s>Transceiver</s>, extra debugging quasi-emulators in progress
** <s>[[Reset and Initialization|Reset module]]</s>
*** <s>Check all modules for proper async reset support</s>
*** <s>Execute on startup</s>
*** <s>Execute on command</s>
*** <s>Soft reset - load and report MAC and location addresses.</s>

* <s>Integrate all modules and simulate the device as a whole</s>
* <s>Determine size of FPGA</s>
* Design or purchase connector to bus board
* Purchase all components (including EEPROM, RJ-45 female jack, etc)
* Obtain footprints of all chips, connectors, jacks, etc
* PCB layout [in progress]
* Prototype PCB
* Design bus board
* Design [[SiPM Amplifier|analog board]]

==Schematics and PCB Designs==

[[Woody Underwood|Electronics board design project by Woody Underwood]]

Digital control board documentation

2009-06-16T20:42:24Z

Underwood: /* Pinout Table */

This documentation covers the most important things to know while testing the digital control board, including component pinouts, nets, and other information.

== Power Requirements ==
=== Required Voltages ===
All components on the digital board '''except the DAC''' can be tested using only a +5V source. The DAC requires +5V, -5V, and a high voltage corresponding to 10V higher than the maximum desired DAC output voltage (see [[#Setting the Output Range | Setting the Output Range]]). Digital and analog grounds must be connected as well before any testing takes place.

=== Power Pins ===
Power shall be connected to the board as follows:
{| cellpadding=3 border=1 |
| '''Voltage'''
| '''Eurocard Pin'''
|-
| DGND
| A6
|-
| AGND
| A5
|-
| +5V
| A4
|-
| -5V
| A3
|-
| High voltage (DAC max out +10)
| A2
|}

=== Power Supply Sequencing ===
The control board is designed such that voltages may be supplied in any order so long as AGND and DGND are connected properly. However, for initial testing, the preferred order for powering up the board is as follows:

# Ensure AGND/DGND are connected/grounded
# +5V
# -5V
# High voltage

== FPGA ==
The control board uses a Xilinx XC3S50A VQ100 FPGA. It has a 100 pin footprint and is located in the center of the control board.

=== Power Details ===
The FPGA is powered by the 3.3V power plane, which is regulated by VR1. The FPGA also obtains 1.2V for its internal logic from a 1.2V power island, regulated by VR3.

=== Logic Standard ===
The Xilinx XC3S50A supports several different digital logic standards. The control board is hard wired such that the FPGA will use a '''3.3V CMOS''' logic standard.

=== Pinout Table ===
{| cellpadding=3 border=1 |
| '''Pin #'''
| '''Net Name'''
| '''Description'''
|-
| P1
| FPGA/TMS
| JTAG
|-
| P2
| FPGA/TDI
| JTAG
|-
| P3
| AD7928/CS
| SPI chip select for ADC
|-
| P4
| SPI
| '''Erroneously wired SPI bus trace''' Connects to SDO on temp. sensor and DIN on ADC
|-
| P5
| CLK_5MHZ
| 5 MHz clock output for SPI bus (ADC and temp. sensor)
|-
| P6
| No connection
|
|-
| P7
| No connection
|
|-
| P8
| DGND
|
|-
| P9
| No connection
|
|-
| P10
| No connection
|
|-
| P11
| +3.3V
|
|-
| P12
| No connection
|
|-
| P13
| No connection
|
|-
| P14
| DGND
|
|-
| P15
| No connection
|
|-
| P16
| No connection
|
|-
| P17
| +1.2V
|
|-
| P18
| DGND
|
|-
| P19
| No connection
|
|-
| P20
| No connection
|
|-
| P21
| No connection
|
|-
| P22
| +3.3V
|
|-
| P23
| DGND
|
|-
| P24
| DGND
|
|-
| P25
| DGND
|
|-
| P26
| +3.3V
|
|-
| P27
| FPGA/CLK_IN
| 20 MHz clock input from crystal oscillator
|-
| P28
| No connection
|
|-
| P29
| No connection
|
|-
| P30
| No connection
|
|-
| P31
| No connection
|
|-
| P32
| No connection
|
|-
| P33
| No connection
|
|-
| P34
| No connection
|
|-
| P35
| CP2201/INT
| Ethernet controller interrupt
|-
| P36
| MASTER_RESET
| Connects to RESET jumper in upper left of board (active-low, externally pulled up)
|-
| P37
| No connection
|
|-
| P38
| +1.2V
|
|-
| P39
| No connection
|
|-
| P40
| CP2201/CS
| Chip select for ethernet controller
|-
| P41
| CP2201/WR
| Write enable for ethernet controller
|-
| P42
| DGND
|
|-
| P43
| CP2201/RD
| Read enable for ethernet controller
|-
| P44
| CP2201/ALE
| Address line enable for ethernet controller
|-
| P45
| +3.3V
|
|-
| P46
| CP2201/RESET
| Reset pin for ethernet controller
|-
| P47
| DGND
|
|-
| P48
| FPGA/INIT_B
| Used during FPGA configuration - see Xilinx documentation
|-
| P49
| CP2201/AD0
| Ethernet controller address/data bus, bit 0
|-
| P50
| CP2201/AD1
| Ethernet controller address/data bus, bit 1
|-
| P51
| FPGA/DIN
| Serial data input from EEPROM for configuration
|-
| P52
| CP2201/AD2
| Ethernet controller address/data bus, bit 2
|-
| P53
| FPGA/CCLK
| Configuration clock (signal generated by FPGA at power on to clock the configuration process) See Xilinx documentation
|-
| P54
| FPGA/DONE
| Gives configuration status - see Xilinx documentation
|-
| P55
| +3.3V
|
|-
| P56
| CP2201/AD3
| Ethernet controller address/data bus, bit 3
|-
| P57
| CP2201/AD4
| Ethernet controller address/data bus, bit 4
|-
| P58
| DGND
|
|-
| P59
| CP2201/AD5
| Ethernet controller address/data bus, bit 5
|-
| P60
| CP2201/AD6
| Ethernet controller address/date bus, bit 6
|-
| P61
| CP2201/AD7
| Ethernet controller address/date bus, bit 7
|-
| P62
| No connection
|
|-
| P63
| DGND
|
|-
| P64
| No connection
|
|-
| P65
| No connection
|
|-
| P66
| +1.2V
|
|-
| P67
| +3.3V
|
|-
| P68
| +3.3V
|
|-
| P69
| DGND
|
|-
| P70
| ID3
| Backplane location identifier jumper, pins 3 & 4 Active-low, FPGA should pull high
|-
| P71
| ID2
| Backplane location identifier jumper, pins 5 & 6 Active-low, FPGA should pull high
|-
| P72
| ID1
| Backplane location identifier jumper, pins 7 & 8 Active-low, FPGA should pull high
|-
| P73
| ID0
| Backplane location identifier jumper, pins 9 & 10 Active-low, FPGA should pull high
|-
| P74
| DGND
|
|-
| P75
| FPGA/TDO
| JTAG
|-
| P76
| FPGA/TCK
| JTAG
|-
| P77
| ID4
| Backplane location identifier jumper, pins 1 & 2 Active-low, FPGA should pull high
|-
| P78
| No connection
|
|-
| P79
| +3.3V
|
|-
| P80
| DGND
|
|-
| P81
| +1.2V
|
|-
| P82
| No connection
|
|-
| P83
| CLK_5MHZ_2
| 5 MHz clock output for DAC
|-
| P84
| No connection
|
|-
| P85
| AD5535/DIN
| DAC serial data input (FPGA out -> DAC in)
|-
| P86
| No connection
|
|-
| P87
| DGND
|
|-
| P89
| No connection
|
|-
| P90
| No connection
|
|-
| P91
| DGND
|
|-
| P92
| +3.3V
|
|-
| P93
| AD7314/CE
| Chip enable for temperature sensor
|-
| P94
| No connection
|
|-
| P95
| DGND
|
|-
| P96
| +3.3V
|
|-
| P97
| AD7928/DOUT
| '''Erroneously wired ADC SPI bus connection''' Connects to DOUT on ADC
|-
| P98
| AD5535/RESET
| Reset pin for DAC
|-
| P99
| DGND
|
|-
| P100
| FPGA/PROG_B
| Used during FPGA configuration - see Xilinx documentation
|}

== EEPROM ==
To facilitate power-on configuration of the FPGA, the control board includes a Xilinx XCF01S EEPROM. The EEPROM is located to the left of the FPGA, above the JTAG header, and has a 20 pin footprint. The EEPROM is labelled U5.

=== Power Details ===
The EEPROM uses +3.3V exclusively, which it receives from the +3.3V power plane, regulated by VR1.

=== Flashing/Burning/Writing ===
Whatever you call it, this refers to storing data in the EEPROM so that it can configure the FPGA at power-on. The EEPROM is programmed using a JTAG interface and the Xilinx Platform USB II cable. It is important to note that in digital board's JTAG chain, the EEPROM is the first device in the chain, unlike in the Xilinx documentation where it is shown as the second device. This should not affect the operation of the board, but should be reflected in the Xilinx software when writing the EEPROM via JTAG.

=== FPGA Configuration ===
The EEPROM and FPGA are hardwired to use a master serial protocol to transfer the program from the EEPROM to the FPGA. This is the protocol recommended in the Xilinx documentation because it minimizes the number of traces necessary to run between the EEPROM and FPGA. All configuration data is sent over a single trace, FPGA/DIN (pin 1 on EEPROM), controlled by the configuration clock signal (FPGA/CCLK) which is automatically generated by the FPGA at power-on. When configuration is complete, FPGA/DONE (pin 10) is pulled high by the FPGA, and the EEPROM and configuration clock are deactivated.

=== Pinout Table ===
{| cellpadding=3 border=1 |
| '''Pin #'''
| '''Net Name'''
| '''Description'''
|-
| 1
| FPGA/DIN
| Serial data line Carries data from the EEPROM to the FPGA
|-
| 2
| No connection
|
|-
| 3
| FPGA/CCLK
| Configuration clock Auto generated by FPGA at power-on, disabled at end of configuration
|-
| 4
| EEPROM/TDI
| This is the EEPROM's TDI This is the entry point for the onboard JTAG chain
|-
| 5
| FPGA/TMS
| JTAG TMS Connects to both FPGA and EEPROM
|-
| 6
| FPGA/TCK
| JTAG TCK Connects to both FPGA and EEPROM
|-
| 7
| FPGA/PROG_B
| Used during configuration See Xilinx documentation
|-
| 8
| FPGA/INIT_B
| Used during configuration - can be used to intiate reconfiguration of FPGA See Xilinx documentation
|-
| 9
| No connection
|
|-
| 10
| FPGA/DONE
| Indicates completion of FPGA configuration High when complete
|-
| 11
| DGND
|
|-
| 12-16
| No connection
|
|-
| 17
| FPGA/TDI
| This is the EEPROM's TDO/FPGA's TDI
|-
| 18-20
| +3.3V
|
|}

== JTAG Header ==
To write the FPGA's program to the EEPROM, the board employs a JTAG based programming system consistent with Xilinx's recommendations. The system is designed to operate with Xilnx's Platform USB II cable and the flying lead adapter.

===Header Location and Size===
The header consists of 14 pins, 100 mil pitch, just below the EEPROM (U5). The header is labelled P1. The pitch of the pins in the header was erroneously selected to be 100 mil, which is not compatible with Xilinx's JTAG ribbon cable. Therefore, the Xilinx flying lead adapter must be used.

===Power Details===
The JTAG interface is powered by the +3.3V power plane, not by the computer's USB port. Power is supplied through pin 2 of the JTAG header.

===Pinout Table===
Note that the header is positioned on the board rotated 180 degrees from the position in which it is shown in the Xilinx documentation. Care must be taken when connecting the flying leads to ensure they are connected to the right pins. Improper wiring will certainly cause undesired operation, and may cause damage as well. Damage is most likely to occur if one of the flying leads is improperly connected to an odd numbered pin, since it will short to the PCB's ground plane.

{| cellpadding=3 border=1 |
| '''Pin #'''
| '''Net Name'''
| '''Flying Lead'''
| '''Description'''
|-
| 1, 3, 5, 7, 9, 11, 13 (odd pins)
| DGND
| Black (connect to any odd numbered pin)
| Ground pins for signal integrity '''Never connect a flying lead other than the black lead to an odd numbered pin''' Doing so will short to ground and may cause permanent damage if the Platform USB II cable does not have protection against this.
|-
| 2
| +3.3V
| Red/VREF
| Power source for all JTAG logic
|-
| 4
| FPGA/TMS
| Green/TMS
| JTAG TMS - connects to EEPROM and FPGA
|-
| 6
| FPGA/TCK
| Yellow/TCK
| JTAG TCK - connects to EEPROM and FPGA
|-
| 8
| FPGA/TDO
| Purple/TDO
| JTAG boundary scan chain endpoint
|-
| 10
| EEPROM/TDI
| White/TDI
| JTAG boundary scan chain start point
|-
| 12
| No connection
|
| Pin is floating
|-
| 14
| No connection
|
| Pin is floating
|}
''The gray HALT flying lead is not connected.''

===JTAG Overview===
The JTAG interface is clocked by the TCK signal. TCK is generated by the Platform USB II cable, and connects directly from the JTAG header to both the EEPROM and FPGA.

The TMS signal is directly connected to both the EEPROM and FPGA, and is the data line over which JTAG test results (in this case programming results) are sent. TMS is used by only one component at a time.

The TDI/TDO lines form a chain that connects to each JTAG component in series. On the control board, the first point in the chain is the EEPROM's TDI. Next is the EEPROM's TDO, which is the same as the FPGA's TDI. The FPGA's TDO then returns to the JTAG header and the Platform USB II cable.

== DAC ==
The control board uses the Analog Devices AD5535, 32-channel, 200V max, digital to analog converter. This chip has a modified BC-124 BGA footprint and is located above the Eurocard connector at the bottom of the board. It is labelled U3.

=== Power Details ===
The DAC is primarily powered by the +5V power island, regulated by an off-board power supply and extensively decoupled in the area of the DAC. The DAC also requires -5V, and a high voltage as discussed in [[#Power Requirements | Power Requirements]]. Both of these voltages are supplied by an off-board supply and decoupled near the DAC. In addition to these voltage levels, the DAC requires a precise +2.5V reference, created by the shunt-type voltage reference VR4.

=== Setting the Output Range ===
The output range of the DAC is set by the 2.5V reference voltage supplied by VR4. The high voltage power supply must supply at a minimum 50 times this voltage, plus 10. Thus, the high voltage power supply should be at least 135V for DAC to operate properly, even though the SiPMs are expected to need only 40V. If it is convenient to use a lower high voltage, VR4 must be replaced to provide lower reference voltage. The high voltage may then be decreased appropriately. To summarize:

* Max output voltage = VREF*50
* Minimum high voltage supply = VREF*50 + 10
* Acceptable range for VREF
** Min: 1V
** Max: 3.75V (AD5535 datasheet specifies 4V max, but this would require AVCC of 5.25V for the DAC, which is not possible in the current board design)

If relevant, R13 is a 100K resistor.

=== Thermal Diode ===
The DAC has a built in thermal diode. The diode drop from anode to cathode is typically 0.65V at 25°C. It changes at a rate of -2.20mV/°C. The anode of this diode is connected to the +5V power island, and the cathode is connected to a 270K resistor to ground. The voltage between the cathode and the resistor is connected to VIN1 (pin 15) on the ADC.

=== Pinout Table ===
See documentation from Analog Devices.

=== Channel Mapping ===
Due to the layout of the balls on the footprint of the DAC, the DAC's internal channel numbers (which must be referenced by the FPGA) have no correlation to the channel numbers on the amplifier board. This table summarizes the mapping between various pins that belong to each channel.

{| cellpadding=3 border=1 |
| '''DAC Channel #'''
| '''DAC Pin #'''
| '''Digital Board Eurocard Pin #'''
| '''Amplifier Board Eurocard Pin #'''
| '''Amplifier Channel #'''
|-
| 0
| B1
| B3
|
|
|-
| 1
| A2
| C4
|
|
|-
| 2
| D1
| B2
|
|
|-
| 3
| C2
| C3
|
|
|-
| 4
| B3
| B4
|
|
|-
| 5
| E2
| C2
|
|
|-
| 6
| F3
| B1
|
|
|-
| 7
| A4
| B5
|
|
|-
| 8
| E4
| C5
|
|
|-
| 9
| B5
| C6
|
|
|-
| 10
| F5
| C1
|
|
|-
| 11
| A6
| C7
|
|
|-
| 12
| E6
| B6
|
|
|-
| 13
| B7
| B7
|
|
|-
| 14
| F7
| C10
|
|
|-
| 15
| E8
| C8
|
|
|-
| 16
| A8
| B8
|
|
|-
| 17
| B9
| C9
|
|
|-
| 18
| F9
| C16
|
|
|-
| 19
| E10
| B11
|
|
|-
| 20
| A10
| B9
|
|
|-
| 21
| B11
| B10
|
|
|-
| 22
| C12
| B12
|
|
|-
| 23
| D13
| B13
|
|
|-
| 24
| E12
| B14
|
|
|-
| 25
| A12
| C11
|
|
|-
| 26
| B13
| C12
|
|
|-
| 27
| H13
| B16
|
|
|-
| 28
| G14
| B15
|
|
|-
| 29
| C14
| C13
|
|
|-
| 30
| F13
| C15
|
|
|-
| 31
| E14
| C14
|
| DACHEALTH See [[#Channel Descriptions | ADC Channel Descriptions]].
|}

==ADC==
The board includes an Analog Devices AD7928 analog to digital converter. The ADC is located just to the right and slightly below the FPGA. It is labelled U4.

===Power Details===
The ADC is powered by the +5V power island, which is regulated by an off-board power supply and decoupled near the ADC. It also requires a precise (±1%) 2.5V reference to which it compares voltages when converting from analog to digital. Since the +5V power source is not used for comparison, it is flexible and may vary by ±0.25V without affecting ADC precision.

===Setting the Measuring Range===
The measuring range is set programmatically by the FPGA over the SPI bus. The way the ADC is connected on the digital board requires that its measuring range be set to 5V, so the RANGE bit should be set to 1 by the FPGA (see Analog Devices documentation).

===Data Interfacing===
The ADC uses an SPI bus to communicate with the FPGA. This bus is shared with the temperature sensor. SPI related pins include SCLK, CS, DIN, and DOUT. See the Pinout Table below.

===Channel Descriptions===
This table shows what signals are monitored by the ADC.

{| cellpadding=3 border=1 |
| '''ADC Channel #'''
| '''ADC Pin #'''
| '''Net Name'''
| '''Description'''
|-
| VIN0
| 16
| AD7928/VHEALTH
| This net helps to monitor to overall health of power on the board, but is specifically intended to monitor -5V. It's voltage is the output of a resistor divider between the +5 and -5V power supplies, with resistor values of 33.2K, and 100K. Assuming +5V and -5V are both correct, the output of the divider will be +2.51V. A reading of other than 2.51V indicates a problem with one of the power supplies. Problems with the +5V power supply can be ruled out by reading VIN3. Based on the reading from VIN3, the voltage of the -5V supply can be calculated.
|-
| VIN1
| 15
| AD5535/CATHODE
| This is the thermal diode output from the DAC. Should read 4.35V (typical) at 25°C. Drops 2.20mV/°C.
|-
| VIN2
| 14
| +3.3V
| This is the +3.3V power plane. A reading of other than +3.3V indicates a problem with VR1.
|-
| VIN3
| 13
| +5V
| This is the +5V power island. A reading of other than +5V indicates a problem with the +5V power supply.
|-
| VIN4
| 12
| ADC_EXT1
| This trace routes to the backplane via Eurocard pin A7. It is intended to measure the output of thermistor on the amplifier board.
|-
| VIN5
| 11
| +1.2V
| This is the +1.2V power island. This island powers the internal logic of the FPGA. A reading of other than 1.2V indicates a problem with VR3.
|-
| VIN6
| 10
| ADC_EXT2
| This trace routes to the backplane via Eurocard pin A8. It is intended to measure one of the transistor base voltages on the amplifier board.
|-
| VIN7
| 9
| DACHEALTH
| This channel monitors the output of a resistor divider connected to channel 31 of the DAC. The divider consists of three resistors of 200K, 200K, and 10.2K (in order). The ADC reads out the voltage level between the second 200K and then 10.2K resistor. These resistors were selected so that at 200V, the readout voltage will be 4.973V. Since the divider should be linear, the expected voltage at 20V is 0.4973V. Three resistors were used rather than two to avoid exceeding the resistors' power ratings when the DAC is set to its maximum voltage. Note that since this divider will consume up to 484uA of current at 200V, this DAC channel should not be used for anything that might require more than ~200uA of current (the DAC can source 700uA max). The channel is routed to the backplane nonetheless.
|}

===Pinout Table===
{| cellpadding=3 border=1 |
| '''Pin #'''
| '''Net Name'''
| '''Description'''
|-
| 1
| CLK_5MHZ
| SPI clock (SCLK), from FPGA Shared with temperature sensor
|-
| 2
| DIN
| SPI data in, from FPGA Shared with temperature sensor ''Currently wired wrong''
|-
| 3
| CS
| SPI chip select
|-
| 4
| AGND
|
|-
| 5
| +5V
| Power pin
|-
| 6
| +5V
| Power pin
|-
| 7
| AD7928/REF_IN
| +2.5V reference, set by VR2
|-
| 8
| AGND
|
|-
| 9-16
| VIN[7:0]
| See [[#Channel Descriptions | ADC Channel Descriptions]]
|-
| 17
| AGND
|
|-
| 18
| DOUT
| SPI data out ''Currently wired incorrectly''
|-
| 19
| +3.3V
| VDRIVE, powers the SPI logic
|-
| 20
| AGND
|
|}

== Ethernet Controller ==
The board uses a Silicon Laboratories CP2201, 28-pin, ethernet controller. The CP2201 is located just above the FPGA, and is labelled U2.

=== Power Details ===
The CP2201 uses only +3.3V, which is supplied by the +3.3V power plane and regulated by VR1. Appropriate decoupling capacitors can be found near the CP2201.

=== Ethernet Jack ===
To the right of the CP2201 is a Pulse J0011D21NL ethernet jack, labelled J1. This jack has a built-in 1:1 inductive coupling. For best results, connect this jack to a nearby ethernet switch. The jack may also be connected directly to a computer using a crossover cable. Though auto-crossover is not supported by the CP2201, if the computer's NIC supports it, a crossover cable is not necessary to connect directly to a computer.

==== Ethernet Jack Pins ====
These are visible only on the back side of the board. Pin 1 is indicated by a square pad. Pin 8 is the farthest pin from pin 1. Pins are numbered such that the 4 pins closer to the plastic thru-hole connectors are odd (1, 3, 5, 7), and the four pins closer to the CP2201 are are even (2, 4, 6, 8).

* Pin 1: TX+
* Pin 2: AC coupled to DGND
* Pin 3: TX-
* Pin 4: RX+
* Pin 5: AC coupled to DGND
* Pin 6: RX-
* Pin 7: No connection
* Pin 8: DGND (direct)

The two large thru-hole pins (not numbered) connect to the metal shielding on the outside of the jack. These are directly connected to DGND to shield against electrical noise inside the jack.

The two plastic thru-hole pins are not conductive and have no electrical connection. They are present only for structural purposes, presumably to prevent stress on the solder points when an ethernet wire is inserted or removed from the jack.

=== Crystal Oscillator ===
The CP2201 is responsible for driving the 20MHz crystal oscillator. This oscillator clocks both the CP2201 and the FPGA. The crystal oscillator can be found above the right corner of the FPGA. It can be identified by its four surface mount pads and roughly .3" length. It is labelled Y1, though this label is not visible after the oscillator is soldered on. The CP2201 uses an inverting driver to excite the crystal. The output of the crystal is then sent to the CP2201 and the FPGA.

=== Bus Format and Multiplexing ===
The 28-pin CP2201 used on the board only supports multiplexed operation. This means that both address and data information are passed over the same set of 8 traces. Hence, these traces are referred to as the address/data (AD) bus. A separate address line enable (ALE) trace prevents collisions from occuring on these traces. The communication protocol used is the Intel format. See the CP2201's datasheet for more information about this.

=== Pinout Table ===
{| cellpadding=3 border=1 |
| '''Pin #'''
| '''Net Name'''
| '''Description'''
|-
| 1
| CP2201/LA
| Link/activity indicator Routed to backplane but not implemented See CP2201 data sheet for information on how to connect to an LED
|-
| 2
| DGND
| By the data sheet, this pin should be AGND We deliberately set it to DGND to avoid noise on AGND plane
|-
| 3
| +3.3V
| AV+ power pin
|-
| 4
| CP2201/RX-
| Connects to RX- on ethernet jack
|-
| 5
| CP2201/RX+
| Connects to RX+ on ethernet jack
|-
| 6
| CP2201/TX+
| Connects to TX+ on ethernet jack
|-
| 7
| CP2201/TX-
| Connects to TX- on ethernet jack
|-
| 8
| +3.3V
| "VDD" power pin
|-
| 9
| DGND
| "DGND1" per the data sheet
|-
| 10
| CP2201/RESET
| "RST" per the data sheet Connects to FPGA - should be programmatically triggered upon reset of FPGA by RESET jumper
|-
| 11-18
| CP2201/AD[0:7]
| Bits 0-7 of the address/data bus Connect to FPGA
|-
| 19
| +3.3V
| "VDD" power pin
|-
| 20
| DGND
| "DGND2" per the data sheet
|-
| 21
| CP2201/ALE
| Address line enable Connects to FPGA See CP2201 documentation
|-
| 22
| CP2201/RD
| Read strobe for AD bus Connects to FPGA See CP2201 documentation
|-
| 23
| CP2201/WR
| Write strobe for AD bus Connects to FPGA See CP2201 documentation
|-
| 24
| CP2201/CS
| Chip select Connects to FPGA
|-
| 25
| CP2201/INT
| Interrupt request Connects to FPGA
|-
| 26
| DGND
| "MOTEN" (Motorola enable) per the datasheet Tied low to disable Motorola bus format (enable Intel format)
|-
| 27
| CP2201/XTAL2
| Crystal oscillator driver The CP2201 inverts the 20MHz clock signal and feeds it back to the crystal oscillator to encourage larger oscillations
|-
| 28
| FPGA/CLK_IN
| "XTAL1" per the data sheet This is the 20MHz clock input Also connects to the FPGA's clock input
|-
| 29*
| DGND
| This is not a pin but rather the base of the CP2201 package. It is connected to the DGND plane for thermal relief
|}

== Eurocard Connector ==
At the bottom of the control board is the Eurocard connector, labelled P2. The Eurocard connector connects the board to the backplane and also connects the board to its power supplies. The Eurocard has 48 pins arranged in three rows of 16 pins each. Rows B and C are exclusively used to pass SiPM bias voltages to the backplane as described in [[#Channel Mapping | DAC Channel Mapping]]. Here is a table describing the purpose of pins in row A:

=== Row A Pinout Table ===
Note that when viewing the front side of the board with the Eurocard at the bottom, these pins go from right to left. If you look closely at the pins, you will see that pin A1 has a square pad, unlike the round pads of the others.

{| cellpadding=3 border=1 |
| '''Pin #'''
| '''Net Name'''
| '''Description'''
|-
| A1
| CP2201/LA
| Ethernet link/activity indicator routed to backplane
|-
| A2
| High voltage input (+210V max)
| High voltage input for DAC. See [[#DAC | DAC]] for information about what voltage to input here.
|-
| A3
| -5V
| For DAC
|-
| A4
| +5V
| Powers most things on the board
|-
| A5
| AGND
|
|-
| A6
| DGND
|
|-
| A7
| ADC_EXT1
| Connects to ADC to monitor voltages on amplifier board See [[#ADC | ADC]]
|-
| A8
| ADC_EXT2
| Connects to ADC to monitor voltages on amplifier board See [[#ADC | ADC]]
|-
| A9
| No connection
|
|-
| A10
| No connection
|
|-
| A11
| No conneciton
|
|-
| A12
| ID4
| Location identifier bit 4 Used to identify which backplane board is connected to See [[#FPGA | FPGA]]
|-
| A13
| ID3
| Location identifier bit 3 Used to identify which backplane board is connected to See [[#FPGA | FPGA]]
|-
| A14
| ID2
| Location identifier bit 2 Used to identify which backplane board is connected to See [[#FPGA | FPGA]]
|-
| A15
| ID1
| Location identifier bit 1 Used to identify which backplane board is connected to See [[#FPGA | FPGA]]
|-
| A16
| ID0
| Location identifier bit 0 Used to identify which backplane board is connected to See [[#FPGA | FPGA]]
|}

Digital control board documentation

2009-06-16T19:35:15Z

Underwood: /* Pinout Table */ changed pin warning

This documentation covers the most important things to know while testing the digital control board, including component pinouts, nets, and other information.

== Power Requirements ==
=== Required Voltages ===
All components on the digital board '''except the DAC''' can be tested using only a +5V source. The DAC requires +5V, -5V, and a high voltage corresponding to 10V higher than the maximum desired DAC output voltage (see [[#Setting the Output Range | Setting the Output Range]]). Digital and analog grounds must be connected as well before any testing takes place.

=== Power Pins ===
Power shall be connected to the board as follows:
{| cellpadding=3 border=1 |
| '''Voltage'''
| '''Eurocard Pin'''
|-
| DGND
| A6
|-
| AGND
| A5
|-
| +5V
| A4
|-
| -5V
| A3
|-
| High voltage (DAC max out +10)
| A2
|}

=== Power Supply Sequencing ===
The control board is designed such that voltages may be supplied in any order so long as AGND and DGND are connected properly. However, for initial testing, the preferred order for powering up the board is as follows:

# Ensure AGND/DGND are connected/grounded
# +5V
# -5V
# High voltage

== FPGA ==
The control board uses a Xilinx XC3S50A VQ100 FPGA. It has a 100 pin footprint and is located in the center of the control board.

=== Power Details ===
The FPGA is powered by the 3.3V power plane, which is regulated by VR1. The FPGA also obtains 1.2V for its internal logic from a 1.2V power island, regulated by VR3.

=== Logic Standard ===
The Xilinx XC3S50A supports several different digital logic standards. The control board is hard wired such that the FPGA will use a '''3.3V CMOS''' logic standard.

=== Pinout Table ===
{| cellpadding=3 border=1 |
| '''Pin #'''
| '''Net Name'''
| '''Description'''
|-
| P1
| FPGA/TMS
| JTAG
|-
| P2
| FPGA/TDI
| JTAG
|-
| P3
| AD7928/CS
| SPI chip select for ADC
|-
| P4
| SPI
| '''Erroneously wired SPI bus trace''' Connects to SDO on temp. sensor and DIN on ADC
|-
| P5
| CLK_5MHZ
| 5 MHz clock output for SPI bus (ADC and temp. sensor)
|-
| P6
| No connection
|
|-
| P7
| No connection
|
|-
| P8
| DGND
|
|-
| P9
| No connection
|
|-
| P10
| No connection
|
|-
| P11
| +3.3V
|
|-
| P12
| No connection
|
|-
| P13
| No connection
|
|-
| P14
| DGND
|
|-
| P15
| No connection
|
|-
| P16
| No connection
|
|-
| P17
| +1.2V
|
|-
| P18
| DGND
|
|-
| P19
| No connection
|
|-
| P20
| No connection
|
|-
| P21
| No connection
|
|-
| P22
| +3.3V
|
|-
| P23
| DGND
|
|-
| P24
| DGND
|
|-
| P25
| DGND
|
|-
| P26
| +3.3V
|
|-
| P27
| FPGA/CLK_IN
| 20 MHz clock input from crystal oscillator
|-
| P28
| No connection
|
|-
| P29
| No connection
|
|-
| P30
| No connection
|
|-
| P31
| No connection
|
|-
| P32
| No connection
|
|-
| P33
| No connection
|
|-
| P34
| No connection
|
|-
| P35
| CP2201/INT
| Ethernet controller interrupt
|-
| P36
| MASTER_RESET
| Connects to RESET jumper in upper left of board (active-low, externally pulled up)
|-
| P37
| No connection
|
|-
| P38
| +1.2V
|
|-
| P39
| No connection
|
|-
| P40
| CP2201/CS
| Chip select for ethernet controller
|-
| P41
| CP2201/WR
| Write enable for ethernet controller
|-
| P42
| DGND
|
|-
| P43
| CP2201/RD
| Read enable for ethernet controller
|-
| P44
| CP2201/ALE
| Address line enable for ethernet controller
|-
| P45
| +3.3V
|
|-
| P46
| CP2201/RESET
| Reset pin for ethernet controller
|-
| P47
| DGND
|
|-
| P48
| FPGA/INIT_B
| Used during FPGA configuration - see Xilinx documentation
|-
| P49
| CP2201/AD0
| Ethernet controller address/data bus, bit 0
|-
| P50
| CP2201/AD1
| Ethernet controller address/data bus, bit 1
|-
| P51
| FPGA/DIN
| Serial data input from EEPROM for configuration
|-
| P52
| CP2201/AD2
| Ethernet controller address/data bus, bit 2
|-
| P53
| FPGA/CCLK
| Configuration clock (signal generated by FPGA at power on to clock the configuration process) See Xilinx documentation
|-
| P54
| FPGA/DONE
| Gives configuration status - see Xilinx documentation
|-
| P55
| +3.3V
|
|-
| P56
| CP2201/AD3
| Ethernet controller address/data bus, bit 3
|-
| P57
| CP2201/AD4
| Ethernet controller address/data bus, bit 4
|-
| P58
| DGND
|
|-
| P59
| CP2201/AD5
| Ethernet controller address/data bus, bit 5
|-
| P60
| CP2201/AD6
| Ethernet controller address/date bus, bit 6
|-
| P61
| CP2201/AD7
| Ethernet controller address/date bus, bit 7
|-
| P62
| No connection
|
|-
| P63
| DGND
|
|-
| P64
| No connection
|
|-
| P65
| No connection
|
|-
| P66
| +1.2V
|
|-
| P67
| +3.3V
|
|-
| P68
| +3.3V
|
|-
| P69
| DGND
|
|-
| P70
| ID3
| Backplane location identifier jumper, pins 3 & 4 Active-low, FPGA should pull high
|-
| P71
| ID2
| Backplane location identifier jumper, pins 5 & 6 Active-low, FPGA should pull high
|-
| P72
| ID1
| Backplane location identifier jumper, pins 7 & 8 Active-low, FPGA should pull high
|-
| P73
| ID0
| Backplane location identifier jumper, pins 9 & 10 Active-low, FPGA should pull high
|-
| P74
| DGND
|
|-
| P75
| FPGA/TDO
| JTAG
|-
| P76
| FPGA/TCK
| JTAG
|-
| P77
| ID4
| Backplane location identifier jumper, pins 1 & 2 Active-low, FPGA should pull high
|-
| P78
| No connection
|
|-
| P79
| +3.3V
|
|-
| P80
| DGND
|
|-
| P81
| +1.2V
|
|-
| P82
| No connection
|
|-
| P83
| CLK_5MHZ_2
| 5 MHz clock output for DAC
|-
| P84
| No connection
|
|-
| P85
| AD5535/DIN
| DAC serial data input (FPGA out -> DAC in)
|-
| P86
| No connection
|
|-
| P87
| DGND
|
|-
| P89
| No connection
|
|-
| P90
| No connection
|
|-
| P91
| DGND
|
|-
| P92
| +3.3V
|
|-
| P93
| AD7314/CE
| Chip enable for temperature sensor
|-
| P94
| No connection
|
|-
| P95
| DGND
|
|-
| P96
| +3.3V
|
|-
| P97
| AD7928/DOUT
| '''Erroneously wired ADC SPI bus connection''' Connects to DOUT on ADC
|-
| P98
| AD5535/RESET
| Reset pin for DAC
|-
| P99
| DGND
|
|-
| P100
| FPGA/PROG_B
| Used during FPGA configuration - see Xilinx documentation
|}

== EEPROM ==
To facilitate power-on configuration of the FPGA, the control board includes a Xilinx XCF01S EEPROM. The EEPROM is located to the left of the FPGA, above the JTAG header, and has a 20 pin footprint. The EEPROM is labelled U5.

=== Power Details ===
The EEPROM uses +3.3V exclusively, which it receives from the +3.3V power plane, regulated by VR1.

=== Flashing/Burning/Writing ===
Whatever you call it, this refers to storing data in the EEPROM so that it can configure the FPGA at power-on. The EEPROM is programmed using a JTAG interface and the Xilinx Platform USB II cable. It is important to note that in digital board's JTAG chain, the EEPROM is the first device in the chain, unlike in the Xilinx documentation where it is shown as the second device. This should not affect the operation of the board, but should be reflected in the Xilinx software when writing the EEPROM via JTAG.

=== FPGA Configuration ===
The EEPROM and FPGA are hardwired to use a master serial protocol to transfer the program from the EEPROM to the FPGA. This is the protocol recommended in the Xilinx documentation because it minimizes the number of traces necessary to run between the EEPROM and FPGA. All configuration data is sent over a single trace, FPGA/DIN (pin 1 on EEPROM), controlled by the configuration clock signal (FPGA/CCLK) which is automatically generated by the FPGA at power-on. When configuration is complete, FPGA/DONE (pin 10) is pulled high by the FPGA, and the EEPROM and configuration clock are deactivated.

=== Pinout Table ===
{| cellpadding=3 border=1 |
| '''Pin #'''
| '''Net Name'''
| '''Description'''
|-
| 1
| FPGA/DIN
| Serial data line Carries data from the EEPROM to the FPGA
|-
| 2
| No connection
|
|-
| 3
| FPGA/CCLK
| Configuration clock Auto generated by FPGA at power-on, disabled at end of configuration
|-
| 4
| EEPROM/TDI
| This is the EEPROM's TDI This is the entry point for the onboard JTAG chain
|-
| 5
| FPGA/TMS
| JTAG TMS Connects to both FPGA and EEPROM
|-
| 6
| FPGA/TCK
| JTAG TCK Connects to both FPGA and EEPROM
|-
| 7
| FPGA/PROG_B
| Used during configuration See Xilinx documentation
|-
| 8
| FPGA/INIT_B
| Used during configuration - can be used to intiate reconfiguration of FPGA See Xilinx documentation
|-
| 9
| No connection
|
|-
| 10
| FPGA/DONE
| Indicates completion of FPGA configuration High when complete
|-
| 11
| DGND
|
|-
| 12-16
| No connection
|
|-
| 17
| FPGA/TDI
| This is the EEPROM's TDO/FPGA's TDI
|-
| 18-20
| +3.3V
|
|}

== JTAG Header ==
To write the FPGA's program to the EEPROM, the board employs a JTAG based programming system consistent with Xilinx's recommendations. The system is designed to operate with Xilnx's Platform USB II cable and the flying lead adapter.

===Header Location and Size===
The header consists of 14 pins, 100 mil pitch, just below the EEPROM (U5). The header is labelled P1. The pitch of the pins in the header was erroneously selected to be 100 mil, which is not compatible with Xilinx's JTAG ribbon cable. Therefore, the Xilinx flying lead adapter must be used.

===Power Details===
The JTAG interface is powered by the +3.3V power plane, not by the computer's USB port. Power is supplied through pin 2 of the JTAG header.

===Pinout Table===
Note that the header is positioned on the board rotated 180 degrees from the position in which it is shown in the Xilinx documentation. Care must be taken when connecting the flying leads to ensure they are connected to the right pins. Improper wiring will certainly cause undesired operation, and may cause damage as well. Damage is most likely to occur if one of the flying leads is connected to an odd numbered pin, since it will short to the PCB's ground plane. '''Note from the pinout table below that no flying lead connections should ever be made to the odd numbered pins on the JTAG header.'''

{| cellpadding=3 border=1 |
| '''Pin #'''
| '''Net Name'''
| '''Description'''
|-
| 1, 3, 5, 7, 9, 11, 13 (odd pins)
| DGND
| Ground pins for signal integrity '''Never connect a flying lead to these pins''' Doing so will short to ground and may cause permanent damage if the Platform USB II cable does not have protection against this.
|-
| 2
| +3.3V
| Power source for all JTAG logic
|-
| 4
| FPGA/TMS
| JTAG TMS - connects to EEPROM and FPGA
|-
| 6
| FPGA/TCK
| JTAG TCK - connects to EEPROM and FPGA
|-
| 8
| FPGA/TDO
| JTAG boundary scan chain endpoint
|-
| 10
| EEPROM/TDI
| JTAG boundary scan chain start point
|-
| 12
| No connection
| Pin is floating
|-
| 14
| No connection
| Pin is floating
|}

===JTAG Overview===
The JTAG interface is clocked by the TCK signal. TCK is generated by the Platform USB II cable, and connects directly from the JTAG header to both the EEPROM and FPGA.

The TMS signal is directly connected to both the EEPROM and FPGA, and is the data line over which JTAG test results (in this case programming results) are sent. TMS is used by only one component at a time.

The TDI/TDO lines form a chain that connects to each JTAG component in series. On the control board, the first point in the chain is the EEPROM's TDI. Next is the EEPROM's TDO, which is the same as the FPGA's TDI. The FPGA's TDO then returns to the JTAG header and the Platform USB II cable.

== DAC ==
The control board uses the Analog Devices AD5535, 32-channel, 200V max, digital to analog converter. This chip has a modified BC-124 BGA footprint and is located above the Eurocard connector at the bottom of the board. It is labelled U3.

=== Power Details ===
The DAC is primarily powered by the +5V power island, regulated by an off-board power supply and extensively decoupled in the area of the DAC. The DAC also requires -5V, and a high voltage as discussed in [[#Power Requirements | Power Requirements]]. Both of these voltages are supplied by an off-board supply and decoupled near the DAC. In addition to these voltage levels, the DAC requires a precise +2.5V reference, created by the shunt-type voltage reference VR4.

=== Setting the Output Range ===
The output range of the DAC is set by the 2.5V reference voltage supplied by VR4. The high voltage power supply must supply at a minimum 50 times this voltage, plus 10. Thus, the high voltage power supply should be at least 135V for DAC to operate properly, even though the SiPMs are expected to need only 40V. If it is convenient to use a lower high voltage, VR4 must be replaced to provide lower reference voltage. The high voltage may then be decreased appropriately. To summarize:

* Max output voltage = VREF*50
* Minimum high voltage supply = VREF*50 + 10
* Acceptable range for VREF
** Min: 1V
** Max: 3.75V (AD5535 datasheet specifies 4V max, but this would require AVCC of 5.25V for the DAC, which is not possible in the current board design)

If relevant, R13 is a 100K resistor.

=== Thermal Diode ===
The DAC has a built in thermal diode. The diode drop from anode to cathode is typically 0.65V at 25°C. It changes at a rate of -2.20mV/°C. The anode of this diode is connected to the +5V power island, and the cathode is connected to a 270K resistor to ground. The voltage between the cathode and the resistor is connected to VIN1 (pin 15) on the ADC.

=== Pinout Table ===
See documentation from Analog Devices.

=== Channel Mapping ===
Due to the layout of the balls on the footprint of the DAC, the DAC's internal channel numbers (which must be referenced by the FPGA) have no correlation to the channel numbers on the amplifier board. This table summarizes the mapping between various pins that belong to each channel.

{| cellpadding=3 border=1 |
| '''DAC Channel #'''
| '''DAC Pin #'''
| '''Digital Board Eurocard Pin #'''
| '''Amplifier Board Eurocard Pin #'''
| '''Amplifier Channel #'''
|-
| 0
| B1
| B3
|
|
|-
| 1
| A2
| C4
|
|
|-
| 2
| D1
| B2
|
|
|-
| 3
| C2
| C3
|
|
|-
| 4
| B3
| B4
|
|
|-
| 5
| E2
| C2
|
|
|-
| 6
| F3
| B1
|
|
|-
| 7
| A4
| B5
|
|
|-
| 8
| E4
| C5
|
|
|-
| 9
| B5
| C6
|
|
|-
| 10
| F5
| C1
|
|
|-
| 11
| A6
| C7
|
|
|-
| 12
| E6
| B6
|
|
|-
| 13
| B7
| B7
|
|
|-
| 14
| F7
| C10
|
|
|-
| 15
| E8
| C8
|
|
|-
| 16
| A8
| B8
|
|
|-
| 17
| B9
| C9
|
|
|-
| 18
| F9
| C16
|
|
|-
| 19
| E10
| B11
|
|
|-
| 20
| A10
| B9
|
|
|-
| 21
| B11
| B10
|
|
|-
| 22
| C12
| B12
|
|
|-
| 23
| D13
| B13
|
|
|-
| 24
| E12
| B14
|
|
|-
| 25
| A12
| C11
|
|
|-
| 26
| B13
| C12
|
|
|-
| 27
| H13
| B16
|
|
|-
| 28
| G14
| B15
|
|
|-
| 29
| C14
| C13
|
|
|-
| 30
| F13
| C15
|
|
|-
| 31
| E14
| C14
|
| DACHEALTH See [[#Channel Descriptions | ADC Channel Descriptions]].
|}

==ADC==
The board includes an Analog Devices AD7928 analog to digital converter. The ADC is located just to the right and slightly below the FPGA. It is labelled U4.

===Power Details===
The ADC is powered by the +5V power island, which is regulated by an off-board power supply and decoupled near the ADC. It also requires a precise (±1%) 2.5V reference to which it compares voltages when converting from analog to digital. Since the +5V power source is not used for comparison, it is flexible and may vary by ±0.25V without affecting ADC precision.

===Setting the Measuring Range===
The measuring range is set programmatically by the FPGA over the SPI bus. The way the ADC is connected on the digital board requires that its measuring range be set to 5V, so the RANGE bit should be set to 1 by the FPGA (see Analog Devices documentation).

===Data Interfacing===
The ADC uses an SPI bus to communicate with the FPGA. This bus is shared with the temperature sensor. SPI related pins include SCLK, CS, DIN, and DOUT. See the Pinout Table below.

===Channel Descriptions===
This table shows what signals are monitored by the ADC.

{| cellpadding=3 border=1 |
| '''ADC Channel #'''
| '''ADC Pin #'''
| '''Net Name'''
| '''Description'''
|-
| VIN0
| 16
| AD7928/VHEALTH
| This net helps to monitor to overall health of power on the board, but is specifically intended to monitor -5V. It's voltage is the output of a resistor divider between the +5 and -5V power supplies, with resistor values of 33.2K, and 100K. Assuming +5V and -5V are both correct, the output of the divider will be +2.51V. A reading of other than 2.51V indicates a problem with one of the power supplies. Problems with the +5V power supply can be ruled out by reading VIN3. Based on the reading from VIN3, the voltage of the -5V supply can be calculated.
|-
| VIN1
| 15
| AD5535/CATHODE
| This is the thermal diode output from the DAC. Should read 4.35V (typical) at 25°C. Drops 2.20mV/°C.
|-
| VIN2
| 14
| +3.3V
| This is the +3.3V power plane. A reading of other than +3.3V indicates a problem with VR1.
|-
| VIN3
| 13
| +5V
| This is the +5V power island. A reading of other than +5V indicates a problem with the +5V power supply.
|-
| VIN4
| 12
| ADC_EXT1
| This trace routes to the backplane via Eurocard pin A7. It is intended to measure the output of thermistor on the amplifier board.
|-
| VIN5
| 11
| +1.2V
| This is the +1.2V power island. This island powers the internal logic of the FPGA. A reading of other than 1.2V indicates a problem with VR3.
|-
| VIN6
| 10
| ADC_EXT2
| This trace routes to the backplane via Eurocard pin A8. It is intended to measure one of the transistor base voltages on the amplifier board.
|-
| VIN7
| 9
| DACHEALTH
| This channel monitors the output of a resistor divider connected to channel 31 of the DAC. The divider consists of three resistors of 200K, 200K, and 10.2K (in order). The ADC reads out the voltage level between the second 200K and then 10.2K resistor. These resistors were selected so that at 200V, the readout voltage will be 4.973V. Since the divider should be linear, the expected voltage at 20V is 0.4973V. Three resistors were used rather than two to avoid exceeding the resistors' power ratings when the DAC is set to its maximum voltage. Note that since this divider will consume up to 484uA of current at 200V, this DAC channel should not be used for anything that might require more than ~200uA of current (the DAC can source 700uA max). The channel is routed to the backplane nonetheless.
|}

===Pinout Table===
{| cellpadding=3 border=1 |
| '''Pin #'''
| '''Net Name'''
| '''Description'''
|-
| 1
| CLK_5MHZ
| SPI clock (SCLK), from FPGA Shared with temperature sensor
|-
| 2
| DIN
| SPI data in, from FPGA Shared with temperature sensor ''Currently wired wrong''
|-
| 3
| CS
| SPI chip select
|-
| 4
| AGND
|
|-
| 5
| +5V
| Power pin
|-
| 6
| +5V
| Power pin
|-
| 7
| AD7928/REF_IN
| +2.5V reference, set by VR2
|-
| 8
| AGND
|
|-
| 9-16
| VIN[7:0]
| See [[#Channel Descriptions | ADC Channel Descriptions]]
|-
| 17
| AGND
|
|-
| 18
| DOUT
| SPI data out ''Currently wired incorrectly''
|-
| 19
| +3.3V
| VDRIVE, powers the SPI logic
|-
| 20
| AGND
|
|}

== Ethernet Controller ==
The board uses a Silicon Laboratories CP2201, 28-pin, ethernet controller. The CP2201 is located just above the FPGA, and is labelled U2.

=== Power Details ===
The CP2201 uses only +3.3V, which is supplied by the +3.3V power plane and regulated by VR1. Appropriate decoupling capacitors can be found near the CP2201.

=== Ethernet Jack ===
To the right of the CP2201 is a Pulse J0011D21NL ethernet jack, labelled J1. This jack has a built-in 1:1 inductive coupling. For best results, connect this jack to a nearby ethernet switch. The jack may also be connected directly to a computer using a crossover cable. Though auto-crossover is not supported by the CP2201, if the computer's NIC supports it, a crossover cable is not necessary to connect directly to a computer.

==== Ethernet Jack Pins ====
These are visible only on the back side of the board. Pin 1 is indicated by a square pad. Pin 8 is the farthest pin from pin 1. Pins are numbered such that the 4 pins closer to the plastic thru-hole connectors are odd (1, 3, 5, 7), and the four pins closer to the CP2201 are are even (2, 4, 6, 8).

* Pin 1: TX+
* Pin 2: AC coupled to DGND
* Pin 3: TX-
* Pin 4: RX+
* Pin 5: AC coupled to DGND
* Pin 6: RX-
* Pin 7: No connection
* Pin 8: DGND (direct)

The two large thru-hole pins (not numbered) connect to the metal shielding on the outside of the jack. These are directly connected to DGND to shield against electrical noise inside the jack.

The two plastic thru-hole pins are not conductive and have no electrical connection. They are present only for structural purposes, presumably to prevent stress on the solder points when an ethernet wire is inserted or removed from the jack.

=== Crystal Oscillator ===
The CP2201 is responsible for driving the 20MHz crystal oscillator. This oscillator clocks both the CP2201 and the FPGA. The crystal oscillator can be found above the right corner of the FPGA. It can be identified by its four surface mount pads and roughly .3" length. It is labelled Y1, though this label is not visible after the oscillator is soldered on. The CP2201 uses an inverting driver to excite the crystal. The output of the crystal is then sent to the CP2201 and the FPGA.

=== Bus Format and Multiplexing ===
The 28-pin CP2201 used on the board only supports multiplexed operation. This means that both address and data information are passed over the same set of 8 traces. Hence, these traces are referred to as the address/data (AD) bus. A separate address line enable (ALE) trace prevents collisions from occuring on these traces. The communication protocol used is the Intel format. See the CP2201's datasheet for more information about this.

=== Pinout Table ===
{| cellpadding=3 border=1 |
| '''Pin #'''
| '''Net Name'''
| '''Description'''
|-
| 1
| CP2201/LA
| Link/activity indicator Routed to backplane but not implemented See CP2201 data sheet for information on how to connect to an LED
|-
| 2
| DGND
| By the data sheet, this pin should be AGND We deliberately set it to DGND to avoid noise on AGND plane
|-
| 3
| +3.3V
| AV+ power pin
|-
| 4
| CP2201/RX-
| Connects to RX- on ethernet jack
|-
| 5
| CP2201/RX+
| Connects to RX+ on ethernet jack
|-
| 6
| CP2201/TX+
| Connects to TX+ on ethernet jack
|-
| 7
| CP2201/TX-
| Connects to TX- on ethernet jack
|-
| 8
| +3.3V
| "VDD" power pin
|-
| 9
| DGND
| "DGND1" per the data sheet
|-
| 10
| CP2201/RESET
| "RST" per the data sheet Connects to FPGA - should be programmatically triggered upon reset of FPGA by RESET jumper
|-
| 11-18
| CP2201/AD[0:7]
| Bits 0-7 of the address/data bus Connect to FPGA
|-
| 19
| +3.3V
| "VDD" power pin
|-
| 20
| DGND
| "DGND2" per the data sheet
|-
| 21
| CP2201/ALE
| Address line enable Connects to FPGA See CP2201 documentation
|-
| 22
| CP2201/RD
| Read strobe for AD bus Connects to FPGA See CP2201 documentation
|-
| 23
| CP2201/WR
| Write strobe for AD bus Connects to FPGA See CP2201 documentation
|-
| 24
| CP2201/CS
| Chip select Connects to FPGA
|-
| 25
| CP2201/INT
| Interrupt request Connects to FPGA
|-
| 26
| DGND
| "MOTEN" (Motorola enable) per the datasheet Tied low to disable Motorola bus format (enable Intel format)
|-
| 27
| CP2201/XTAL2
| Crystal oscillator driver The CP2201 inverts the 20MHz clock signal and feeds it back to the crystal oscillator to encourage larger oscillations
|-
| 28
| FPGA/CLK_IN
| "XTAL1" per the data sheet This is the 20MHz clock input Also connects to the FPGA's clock input
|-
| 29*
| DGND
| This is not a pin but rather the base of the CP2201 package. It is connected to the DGND plane for thermal relief
|}

== Eurocard Connector ==
At the bottom of the control board is the Eurocard connector, labelled P2. The Eurocard connector connects the board to the backplane and also connects the board to its power supplies. The Eurocard has 48 pins arranged in three rows of 16 pins each. Rows B and C are exclusively used to pass SiPM bias voltages to the backplane as described in [[#Channel Mapping | DAC Channel Mapping]]. Here is a table describing the purpose of pins in row A:

=== Row A Pinout Table ===
Note that when viewing the front side of the board with the Eurocard at the bottom, these pins go from right to left. If you look closely at the pins, you will see that pin A1 has a square pad, unlike the round pads of the others.

{| cellpadding=3 border=1 |
| '''Pin #'''
| '''Net Name'''
| '''Description'''
|-
| A1
| CP2201/LA
| Ethernet link/activity indicator routed to backplane
|-
| A2
| High voltage input (+210V max)
| High voltage input for DAC. See [[#DAC | DAC]] for information about what voltage to input here.
|-
| A3
| -5V
| For DAC
|-
| A4
| +5V
| Powers most things on the board
|-
| A5
| AGND
|
|-
| A6
| DGND
|
|-
| A7
| ADC_EXT1
| Connects to ADC to monitor voltages on amplifier board See [[#ADC | ADC]]
|-
| A8
| ADC_EXT2
| Connects to ADC to monitor voltages on amplifier board See [[#ADC | ADC]]
|-
| A9
| No connection
|
|-
| A10
| No connection
|
|-
| A11
| No conneciton
|
|-
| A12
| ID4
| Location identifier bit 4 Used to identify which backplane board is connected to See [[#FPGA | FPGA]]
|-
| A13
| ID3
| Location identifier bit 3 Used to identify which backplane board is connected to See [[#FPGA | FPGA]]
|-
| A14
| ID2
| Location identifier bit 2 Used to identify which backplane board is connected to See [[#FPGA | FPGA]]
|-
| A15
| ID1
| Location identifier bit 1 Used to identify which backplane board is connected to See [[#FPGA | FPGA]]
|-
| A16
| ID0
| Location identifier bit 0 Used to identify which backplane board is connected to See [[#FPGA | FPGA]]
|}

Digital control board documentation

2009-06-16T19:28:36Z

Underwood: /* Eurocard Connector */

This documentation covers the most important things to know while testing the digital control board, including component pinouts, nets, and other information.

== Power Requirements ==
=== Required Voltages ===
All components on the digital board '''except the DAC''' can be tested using only a +5V source. The DAC requires +5V, -5V, and a high voltage corresponding to 10V higher than the maximum desired DAC output voltage (see [[#Setting the Output Range | Setting the Output Range]]). Digital and analog grounds must be connected as well before any testing takes place.

=== Power Pins ===
Power shall be connected to the board as follows:
{| cellpadding=3 border=1 |
| '''Voltage'''
| '''Eurocard Pin'''
|-
| DGND
| A6
|-
| AGND
| A5
|-
| +5V
| A4
|-
| -5V
| A3
|-
| High voltage (DAC max out +10)
| A2
|}

=== Power Supply Sequencing ===
The control board is designed such that voltages may be supplied in any order so long as AGND and DGND are connected properly. However, for initial testing, the preferred order for powering up the board is as follows:

# Ensure AGND/DGND are connected/grounded
# +5V
# -5V
# High voltage

== FPGA ==
The control board uses a Xilinx XC3S50A VQ100 FPGA. It has a 100 pin footprint and is located in the center of the control board.

=== Power Details ===
The FPGA is powered by the 3.3V power plane, which is regulated by VR1. The FPGA also obtains 1.2V for its internal logic from a 1.2V power island, regulated by VR3.

=== Logic Standard ===
The Xilinx XC3S50A supports several different digital logic standards. The control board is hard wired such that the FPGA will use a '''3.3V CMOS''' logic standard.

=== Pinout Table ===
{| cellpadding=3 border=1 |
| '''Pin #'''
| '''Net Name'''
| '''Description'''
|-
| P1
| FPGA/TMS
| JTAG
|-
| P2
| FPGA/TDI
| JTAG
|-
| P3
| AD7928/CS
| SPI chip select for ADC
|-
| P4
| SPI
| '''Erroneously wired SPI bus trace''' Connects to SDO on temp. sensor and DIN on ADC
|-
| P5
| CLK_5MHZ
| 5 MHz clock output for SPI bus (ADC and temp. sensor)
|-
| P6
| No connection
|
|-
| P7
| No connection
|
|-
| P8
| DGND
|
|-
| P9
| No connection
|
|-
| P10
| No connection
|
|-
| P11
| +3.3V
|
|-
| P12
| No connection
|
|-
| P13
| No connection
|
|-
| P14
| DGND
|
|-
| P15
| No connection
|
|-
| P16
| No connection
|
|-
| P17
| +1.2V
|
|-
| P18
| DGND
|
|-
| P19
| No connection
|
|-
| P20
| No connection
|
|-
| P21
| No connection
|
|-
| P22
| +3.3V
|
|-
| P23
| DGND
|
|-
| P24
| DGND
|
|-
| P25
| DGND
|
|-
| P26
| +3.3V
|
|-
| P27
| FPGA/CLK_IN
| 20 MHz clock input from crystal oscillator
|-
| P28
| No connection
|
|-
| P29
| No connection
|
|-
| P30
| No connection
|
|-
| P31
| No connection
|
|-
| P32
| No connection
|
|-
| P33
| No connection
|
|-
| P34
| No connection
|
|-
| P35
| CP2201/INT
| Ethernet controller interrupt
|-
| P36
| MASTER_RESET
| Connects to RESET jumper in upper left of board (active-low, externally pulled up)
|-
| P37
| No connection
|
|-
| P38
| +1.2V
|
|-
| P39
| No connection
|
|-
| P40
| CP2201/CS
| Chip select for ethernet controller
|-
| P41
| CP2201/WR
| Write enable for ethernet controller
|-
| P42
| DGND
|
|-
| P43
| CP2201/RD
| Read enable for ethernet controller
|-
| P44
| CP2201/ALE
| Address line enable for ethernet controller
|-
| P45
| +3.3V
|
|-
| P46
| CP2201/RESET
| Reset pin for ethernet controller
|-
| P47
| DGND
|
|-
| P48
| FPGA/INIT_B
| Used during FPGA configuration - see Xilinx documentation
|-
| P49
| CP2201/AD0
| Ethernet controller address/data bus, bit 0
|-
| P50
| CP2201/AD1
| Ethernet controller address/data bus, bit 1
|-
| P51
| FPGA/DIN
| Serial data input from EEPROM for configuration
|-
| P52
| CP2201/AD2
| Ethernet controller address/data bus, bit 2
|-
| P53
| FPGA/CCLK
| Configuration clock (signal generated by FPGA at power on to clock the configuration process) See Xilinx documentation
|-
| P54
| FPGA/DONE
| Gives configuration status - see Xilinx documentation
|-
| P55
| +3.3V
|
|-
| P56
| CP2201/AD3
| Ethernet controller address/data bus, bit 3
|-
| P57
| CP2201/AD4
| Ethernet controller address/data bus, bit 4
|-
| P58
| DGND
|
|-
| P59
| CP2201/AD5
| Ethernet controller address/data bus, bit 5
|-
| P60
| CP2201/AD6
| Ethernet controller address/date bus, bit 6
|-
| P61
| CP2201/AD7
| Ethernet controller address/date bus, bit 7
|-
| P62
| No connection
|
|-
| P63
| DGND
|
|-
| P64
| No connection
|
|-
| P65
| No connection
|
|-
| P66
| +1.2V
|
|-
| P67
| +3.3V
|
|-
| P68
| +3.3V
|
|-
| P69
| DGND
|
|-
| P70
| ID3
| Backplane location identifier jumper, pins 3 & 4 Active-low, FPGA should pull high
|-
| P71
| ID2
| Backplane location identifier jumper, pins 5 & 6 Active-low, FPGA should pull high
|-
| P72
| ID1
| Backplane location identifier jumper, pins 7 & 8 Active-low, FPGA should pull high
|-
| P73
| ID0
| Backplane location identifier jumper, pins 9 & 10 Active-low, FPGA should pull high
|-
| P74
| DGND
|
|-
| P75
| FPGA/TDO
| JTAG
|-
| P76
| FPGA/TCK
| JTAG
|-
| P77
| ID4
| Backplane location identifier jumper, pins 1 & 2 Active-low, FPGA should pull high
|-
| P78
| No connection
|
|-
| P79
| +3.3V
|
|-
| P80
| DGND
|
|-
| P81
| +1.2V
|
|-
| P82
| No connection
|
|-
| P83
| CLK_5MHZ_2
| 5 MHz clock output for DAC
|-
| P84
| No connection
|
|-
| P85
| AD5535/DIN
| DAC serial data input (FPGA out -> DAC in)
|-
| P86
| No connection
|
|-
| P87
| DGND
|
|-
| P89
| No connection
|
|-
| P90
| No connection
|
|-
| P91
| DGND
|
|-
| P92
| +3.3V
|
|-
| P93
| AD7314/CE
| Chip enable for temperature sensor
|-
| P94
| No connection
|
|-
| P95
| DGND
|
|-
| P96
| +3.3V
|
|-
| P97
| AD7928/DOUT
| '''Erroneously wired ADC SPI bus connection''' Connects to DOUT on ADC
|-
| P98
| AD5535/RESET
| Reset pin for DAC
|-
| P99
| DGND
|
|-
| P100
| FPGA/PROG_B
| Used during FPGA configuration - see Xilinx documentation
|}

== EEPROM ==
To facilitate power-on configuration of the FPGA, the control board includes a Xilinx XCF01S EEPROM. The EEPROM is located to the left of the FPGA, above the JTAG header, and has a 20 pin footprint. The EEPROM is labelled U5.

=== Power Details ===
The EEPROM uses +3.3V exclusively, which it receives from the +3.3V power plane, regulated by VR1.

=== Flashing/Burning/Writing ===
Whatever you call it, this refers to storing data in the EEPROM so that it can configure the FPGA at power-on. The EEPROM is programmed using a JTAG interface and the Xilinx Platform USB II cable. It is important to note that in digital board's JTAG chain, the EEPROM is the first device in the chain, unlike in the Xilinx documentation where it is shown as the second device. This should not affect the operation of the board, but should be reflected in the Xilinx software when writing the EEPROM via JTAG.

=== FPGA Configuration ===
The EEPROM and FPGA are hardwired to use a master serial protocol to transfer the program from the EEPROM to the FPGA. This is the protocol recommended in the Xilinx documentation because it minimizes the number of traces necessary to run between the EEPROM and FPGA. All configuration data is sent over a single trace, FPGA/DIN (pin 1 on EEPROM), controlled by the configuration clock signal (FPGA/CCLK) which is automatically generated by the FPGA at power-on. When configuration is complete, FPGA/DONE (pin 10) is pulled high by the FPGA, and the EEPROM and configuration clock are deactivated.

=== Pinout Table ===
{| cellpadding=3 border=1 |
| '''Pin #'''
| '''Net Name'''
| '''Description'''
|-
| 1
| FPGA/DIN
| Serial data line Carries data from the EEPROM to the FPGA
|-
| 2
| No connection
|
|-
| 3
| FPGA/CCLK
| Configuration clock Auto generated by FPGA at power-on, disabled at end of configuration
|-
| 4
| EEPROM/TDI
| This is the EEPROM's TDI This is the entry point for the onboard JTAG chain
|-
| 5
| FPGA/TMS
| JTAG TMS Connects to both FPGA and EEPROM
|-
| 6
| FPGA/TCK
| JTAG TCK Connects to both FPGA and EEPROM
|-
| 7
| FPGA/PROG_B
| Used during configuration See Xilinx documentation
|-
| 8
| FPGA/INIT_B
| Used during configuration - can be used to intiate reconfiguration of FPGA See Xilinx documentation
|-
| 9
| No connection
|
|-
| 10
| FPGA/DONE
| Indicates completion of FPGA configuration High when complete
|-
| 11
| DGND
|
|-
| 12-16
| No connection
|
|-
| 17
| FPGA/TDI
| This is the EEPROM's TDO/FPGA's TDI
|-
| 18-20
| +3.3V
|
|}

== JTAG Header ==
To write the FPGA's program to the EEPROM, the board employs a JTAG based programming system consistent with Xilinx's recommendations. The system is designed to operate with Xilnx's Platform USB II cable and the flying lead adapter.

===Header Location and Size===
The header consists of 14 pins, 100 mil pitch, just below the EEPROM (U5). The header is labelled P1. The pitch of the pins in the header was erroneously selected to be 100 mil, which is not compatible with Xilinx's JTAG ribbon cable. Therefore, the Xilinx flying lead adapter must be used.

===Power Details===
The JTAG interface is powered by the +3.3V power plane, not by the computer's USB port. Power is supplied through pin 2 of the JTAG header.

===Pinout Table===
Note that the header is positioned on the board rotated 180 degrees from the position in which it is shown in the Xilinx documentation. Care must be taken when connecting the flying leads to ensure they are connected to the right pins. Connecting the flying leads to the wrong side of the header will cause all of the leads to short on the digital board's ground plane. This will certainly cause undesired operation, and may or may not cause damage. Improper wiring is most likely to cause damage if one of the flying leads is connected to an odd numbered pin. '''Note from the pinout table below that no flying lead connections should ever be made to the odd numbered pins on the JTAG header.'''

{| cellpadding=3 border=1 |
| '''Pin #'''
| '''Net Name'''
| '''Description'''
|-
| 1, 3, 5, 7, 9, 11, 13 (odd pins)
| DGND
| Ground pins for signal integrity '''Never connect a flying lead to these pins''' Doing so will short to ground and may cause permanent damage if the Platform USB II cable does not have protection against this.
|-
| 2
| +3.3V
| Power source for all JTAG logic
|-
| 4
| FPGA/TMS
| JTAG TMS - connects to EEPROM and FPGA
|-
| 6
| FPGA/TCK
| JTAG TCK - connects to EEPROM and FPGA
|-
| 8
| FPGA/TDO
| JTAG boundary scan chain endpoint
|-
| 10
| EEPROM/TDI
| JTAG boundary scan chain start point
|-
| 12
| No connection
| Pin is floating
|-
| 14
| No connection
| Pin is floating
|}

===JTAG Overview===
The JTAG interface is clocked by the TCK signal. TCK is generated by the Platform USB II cable, and connects directly from the JTAG header to both the EEPROM and FPGA.

The TMS signal is directly connected to both the EEPROM and FPGA, and is the data line over which JTAG test results (in this case programming results) are sent. TMS is used by only one component at a time.

The TDI/TDO lines form a chain that connects to each JTAG component in series. On the control board, the first point in the chain is the EEPROM's TDI. Next is the EEPROM's TDO, which is the same as the FPGA's TDI. The FPGA's TDO then returns to the JTAG header and the Platform USB II cable.

== DAC ==
The control board uses the Analog Devices AD5535, 32-channel, 200V max, digital to analog converter. This chip has a modified BC-124 BGA footprint and is located above the Eurocard connector at the bottom of the board. It is labelled U3.

=== Power Details ===
The DAC is primarily powered by the +5V power island, regulated by an off-board power supply and extensively decoupled in the area of the DAC. The DAC also requires -5V, and a high voltage as discussed in [[#Power Requirements | Power Requirements]]. Both of these voltages are supplied by an off-board supply and decoupled near the DAC. In addition to these voltage levels, the DAC requires a precise +2.5V reference, created by the shunt-type voltage reference VR4.

=== Setting the Output Range ===
The output range of the DAC is set by the 2.5V reference voltage supplied by VR4. The high voltage power supply must supply at a minimum 50 times this voltage, plus 10. Thus, the high voltage power supply should be at least 135V for DAC to operate properly, even though the SiPMs are expected to need only 40V. If it is convenient to use a lower high voltage, VR4 must be replaced to provide lower reference voltage. The high voltage may then be decreased appropriately. To summarize:

* Max output voltage = VREF*50
* Minimum high voltage supply = VREF*50 + 10
* Acceptable range for VREF
** Min: 1V
** Max: 3.75V (AD5535 datasheet specifies 4V max, but this would require AVCC of 5.25V for the DAC, which is not possible in the current board design)

If relevant, R13 is a 100K resistor.

=== Thermal Diode ===
The DAC has a built in thermal diode. The diode drop from anode to cathode is typically 0.65V at 25°C. It changes at a rate of -2.20mV/°C. The anode of this diode is connected to the +5V power island, and the cathode is connected to a 270K resistor to ground. The voltage between the cathode and the resistor is connected to VIN1 (pin 15) on the ADC.

=== Pinout Table ===
See documentation from Analog Devices.

=== Channel Mapping ===
Due to the layout of the balls on the footprint of the DAC, the DAC's internal channel numbers (which must be referenced by the FPGA) have no correlation to the channel numbers on the amplifier board. This table summarizes the mapping between various pins that belong to each channel.

{| cellpadding=3 border=1 |
| '''DAC Channel #'''
| '''DAC Pin #'''
| '''Digital Board Eurocard Pin #'''
| '''Amplifier Board Eurocard Pin #'''
| '''Amplifier Channel #'''
|-
| 0
| B1
| B3
|
|
|-
| 1
| A2
| C4
|
|
|-
| 2
| D1
| B2
|
|
|-
| 3
| C2
| C3
|
|
|-
| 4
| B3
| B4
|
|
|-
| 5
| E2
| C2
|
|
|-
| 6
| F3
| B1
|
|
|-
| 7
| A4
| B5
|
|
|-
| 8
| E4
| C5
|
|
|-
| 9
| B5
| C6
|
|
|-
| 10
| F5
| C1
|
|
|-
| 11
| A6
| C7
|
|
|-
| 12
| E6
| B6
|
|
|-
| 13
| B7
| B7
|
|
|-
| 14
| F7
| C10
|
|
|-
| 15
| E8
| C8
|
|
|-
| 16
| A8
| B8
|
|
|-
| 17
| B9
| C9
|
|
|-
| 18
| F9
| C16
|
|
|-
| 19
| E10
| B11
|
|
|-
| 20
| A10
| B9
|
|
|-
| 21
| B11
| B10
|
|
|-
| 22
| C12
| B12
|
|
|-
| 23
| D13
| B13
|
|
|-
| 24
| E12
| B14
|
|
|-
| 25
| A12
| C11
|
|
|-
| 26
| B13
| C12
|
|
|-
| 27
| H13
| B16
|
|
|-
| 28
| G14
| B15
|
|
|-
| 29
| C14
| C13
|
|
|-
| 30
| F13
| C15
|
|
|-
| 31
| E14
| C14
|
| DACHEALTH See [[#Channel Descriptions | ADC Channel Descriptions]].
|}

==ADC==
The board includes an Analog Devices AD7928 analog to digital converter. The ADC is located just to the right and slightly below the FPGA. It is labelled U4.

===Power Details===
The ADC is powered by the +5V power island, which is regulated by an off-board power supply and decoupled near the ADC. It also requires a precise (±1%) 2.5V reference to which it compares voltages when converting from analog to digital. Since the +5V power source is not used for comparison, it is flexible and may vary by ±0.25V without affecting ADC precision.

===Setting the Measuring Range===
The measuring range is set programmatically by the FPGA over the SPI bus. The way the ADC is connected on the digital board requires that its measuring range be set to 5V, so the RANGE bit should be set to 1 by the FPGA (see Analog Devices documentation).

===Data Interfacing===
The ADC uses an SPI bus to communicate with the FPGA. This bus is shared with the temperature sensor. SPI related pins include SCLK, CS, DIN, and DOUT. See the Pinout Table below.

===Channel Descriptions===
This table shows what signals are monitored by the ADC.

{| cellpadding=3 border=1 |
| '''ADC Channel #'''
| '''ADC Pin #'''
| '''Net Name'''
| '''Description'''
|-
| VIN0
| 16
| AD7928/VHEALTH
| This net helps to monitor to overall health of power on the board, but is specifically intended to monitor -5V. It's voltage is the output of a resistor divider between the +5 and -5V power supplies, with resistor values of 33.2K, and 100K. Assuming +5V and -5V are both correct, the output of the divider will be +2.51V. A reading of other than 2.51V indicates a problem with one of the power supplies. Problems with the +5V power supply can be ruled out by reading VIN3. Based on the reading from VIN3, the voltage of the -5V supply can be calculated.
|-
| VIN1
| 15
| AD5535/CATHODE
| This is the thermal diode output from the DAC. Should read 4.35V (typical) at 25°C. Drops 2.20mV/°C.
|-
| VIN2
| 14
| +3.3V
| This is the +3.3V power plane. A reading of other than +3.3V indicates a problem with VR1.
|-
| VIN3
| 13
| +5V
| This is the +5V power island. A reading of other than +5V indicates a problem with the +5V power supply.
|-
| VIN4
| 12
| ADC_EXT1
| This trace routes to the backplane via Eurocard pin A7. It is intended to measure the output of thermistor on the amplifier board.
|-
| VIN5
| 11
| +1.2V
| This is the +1.2V power island. This island powers the internal logic of the FPGA. A reading of other than 1.2V indicates a problem with VR3.
|-
| VIN6
| 10
| ADC_EXT2
| This trace routes to the backplane via Eurocard pin A8. It is intended to measure one of the transistor base voltages on the amplifier board.
|-
| VIN7
| 9
| DACHEALTH
| This channel monitors the output of a resistor divider connected to channel 31 of the DAC. The divider consists of three resistors of 200K, 200K, and 10.2K (in order). The ADC reads out the voltage level between the second 200K and then 10.2K resistor. These resistors were selected so that at 200V, the readout voltage will be 4.973V. Since the divider should be linear, the expected voltage at 20V is 0.4973V. Three resistors were used rather than two to avoid exceeding the resistors' power ratings when the DAC is set to its maximum voltage. Note that since this divider will consume up to 484uA of current at 200V, this DAC channel should not be used for anything that might require more than ~200uA of current (the DAC can source 700uA max). The channel is routed to the backplane nonetheless.
|}

===Pinout Table===
{| cellpadding=3 border=1 |
| '''Pin #'''
| '''Net Name'''
| '''Description'''
|-
| 1
| CLK_5MHZ
| SPI clock (SCLK), from FPGA Shared with temperature sensor
|-
| 2
| DIN
| SPI data in, from FPGA Shared with temperature sensor ''Currently wired wrong''
|-
| 3
| CS
| SPI chip select
|-
| 4
| AGND
|
|-
| 5
| +5V
| Power pin
|-
| 6
| +5V
| Power pin
|-
| 7
| AD7928/REF_IN
| +2.5V reference, set by VR2
|-
| 8
| AGND
|
|-
| 9-16
| VIN[7:0]
| See [[#Channel Descriptions | ADC Channel Descriptions]]
|-
| 17
| AGND
|
|-
| 18
| DOUT
| SPI data out ''Currently wired incorrectly''
|-
| 19
| +3.3V
| VDRIVE, powers the SPI logic
|-
| 20
| AGND
|
|}

== Ethernet Controller ==
The board uses a Silicon Laboratories CP2201, 28-pin, ethernet controller. The CP2201 is located just above the FPGA, and is labelled U2.

=== Power Details ===
The CP2201 uses only +3.3V, which is supplied by the +3.3V power plane and regulated by VR1. Appropriate decoupling capacitors can be found near the CP2201.

=== Ethernet Jack ===
To the right of the CP2201 is a Pulse J0011D21NL ethernet jack, labelled J1. This jack has a built-in 1:1 inductive coupling. For best results, connect this jack to a nearby ethernet switch. The jack may also be connected directly to a computer using a crossover cable. Though auto-crossover is not supported by the CP2201, if the computer's NIC supports it, a crossover cable is not necessary to connect directly to a computer.

==== Ethernet Jack Pins ====
These are visible only on the back side of the board. Pin 1 is indicated by a square pad. Pin 8 is the farthest pin from pin 1. Pins are numbered such that the 4 pins closer to the plastic thru-hole connectors are odd (1, 3, 5, 7), and the four pins closer to the CP2201 are are even (2, 4, 6, 8).

* Pin 1: TX+
* Pin 2: AC coupled to DGND
* Pin 3: TX-
* Pin 4: RX+
* Pin 5: AC coupled to DGND
* Pin 6: RX-
* Pin 7: No connection
* Pin 8: DGND (direct)

The two large thru-hole pins (not numbered) connect to the metal shielding on the outside of the jack. These are directly connected to DGND to shield against electrical noise inside the jack.

The two plastic thru-hole pins are not conductive and have no electrical connection. They are present only for structural purposes, presumably to prevent stress on the solder points when an ethernet wire is inserted or removed from the jack.

=== Crystal Oscillator ===
The CP2201 is responsible for driving the 20MHz crystal oscillator. This oscillator clocks both the CP2201 and the FPGA. The crystal oscillator can be found above the right corner of the FPGA. It can be identified by its four surface mount pads and roughly .3" length. It is labelled Y1, though this label is not visible after the oscillator is soldered on. The CP2201 uses an inverting driver to excite the crystal. The output of the crystal is then sent to the CP2201 and the FPGA.

=== Bus Format and Multiplexing ===
The 28-pin CP2201 used on the board only supports multiplexed operation. This means that both address and data information are passed over the same set of 8 traces. Hence, these traces are referred to as the address/data (AD) bus. A separate address line enable (ALE) trace prevents collisions from occuring on these traces. The communication protocol used is the Intel format. See the CP2201's datasheet for more information about this.

=== Pinout Table ===
{| cellpadding=3 border=1 |
| '''Pin #'''
| '''Net Name'''
| '''Description'''
|-
| 1
| CP2201/LA
| Link/activity indicator Routed to backplane but not implemented See CP2201 data sheet for information on how to connect to an LED
|-
| 2
| DGND
| By the data sheet, this pin should be AGND We deliberately set it to DGND to avoid noise on AGND plane
|-
| 3
| +3.3V
| AV+ power pin
|-
| 4
| CP2201/RX-
| Connects to RX- on ethernet jack
|-
| 5
| CP2201/RX+
| Connects to RX+ on ethernet jack
|-
| 6
| CP2201/TX+
| Connects to TX+ on ethernet jack
|-
| 7
| CP2201/TX-
| Connects to TX- on ethernet jack
|-
| 8
| +3.3V
| "VDD" power pin
|-
| 9
| DGND
| "DGND1" per the data sheet
|-
| 10
| CP2201/RESET
| "RST" per the data sheet Connects to FPGA - should be programmatically triggered upon reset of FPGA by RESET jumper
|-
| 11-18
| CP2201/AD[0:7]
| Bits 0-7 of the address/data bus Connect to FPGA
|-
| 19
| +3.3V
| "VDD" power pin
|-
| 20
| DGND
| "DGND2" per the data sheet
|-
| 21
| CP2201/ALE
| Address line enable Connects to FPGA See CP2201 documentation
|-
| 22
| CP2201/RD
| Read strobe for AD bus Connects to FPGA See CP2201 documentation
|-
| 23
| CP2201/WR
| Write strobe for AD bus Connects to FPGA See CP2201 documentation
|-
| 24
| CP2201/CS
| Chip select Connects to FPGA
|-
| 25
| CP2201/INT
| Interrupt request Connects to FPGA
|-
| 26
| DGND
| "MOTEN" (Motorola enable) per the datasheet Tied low to disable Motorola bus format (enable Intel format)
|-
| 27
| CP2201/XTAL2
| Crystal oscillator driver The CP2201 inverts the 20MHz clock signal and feeds it back to the crystal oscillator to encourage larger oscillations
|-
| 28
| FPGA/CLK_IN
| "XTAL1" per the data sheet This is the 20MHz clock input Also connects to the FPGA's clock input
|-
| 29*
| DGND
| This is not a pin but rather the base of the CP2201 package. It is connected to the DGND plane for thermal relief
|}

== Eurocard Connector ==
At the bottom of the control board is the Eurocard connector, labelled P2. The Eurocard connector connects the board to the backplane and also connects the board to its power supplies. The Eurocard has 48 pins arranged in three rows of 16 pins each. Rows B and C are exclusively used to pass SiPM bias voltages to the backplane as described in [[#Channel Mapping | DAC Channel Mapping]]. Here is a table describing the purpose of pins in row A:

=== Row A Pinout Table ===
Note that when viewing the front side of the board with the Eurocard at the bottom, these pins go from right to left. If you look closely at the pins, you will see that pin A1 has a square pad, unlike the round pads of the others.

{| cellpadding=3 border=1 |
| '''Pin #'''
| '''Net Name'''
| '''Description'''
|-
| A1
| CP2201/LA
| Ethernet link/activity indicator routed to backplane
|-
| A2
| High voltage input (+210V max)
| High voltage input for DAC. See [[#DAC | DAC]] for information about what voltage to input here.
|-
| A3
| -5V
| For DAC
|-
| A4
| +5V
| Powers most things on the board
|-
| A5
| AGND
|
|-
| A6
| DGND
|
|-
| A7
| ADC_EXT1
| Connects to ADC to monitor voltages on amplifier board See [[#ADC | ADC]]
|-
| A8
| ADC_EXT2
| Connects to ADC to monitor voltages on amplifier board See [[#ADC | ADC]]
|-
| A9
| No connection
|
|-
| A10
| No connection
|
|-
| A11
| No conneciton
|
|-
| A12
| ID4
| Location identifier bit 4 Used to identify which backplane board is connected to See [[#FPGA | FPGA]]
|-
| A13
| ID3
| Location identifier bit 3 Used to identify which backplane board is connected to See [[#FPGA | FPGA]]
|-
| A14
| ID2
| Location identifier bit 2 Used to identify which backplane board is connected to See [[#FPGA | FPGA]]
|-
| A15
| ID1
| Location identifier bit 1 Used to identify which backplane board is connected to See [[#FPGA | FPGA]]
|-
| A16
| ID0
| Location identifier bit 0 Used to identify which backplane board is connected to See [[#FPGA | FPGA]]
|}

Digital control board documentation

2009-06-16T19:26:56Z

Underwood: /* Channel Mapping */

This documentation covers the most important things to know while testing the digital control board, including component pinouts, nets, and other information.

== Power Requirements ==
=== Required Voltages ===
All components on the digital board '''except the DAC''' can be tested using only a +5V source. The DAC requires +5V, -5V, and a high voltage corresponding to 10V higher than the maximum desired DAC output voltage (see [[#Setting the Output Range | Setting the Output Range]]). Digital and analog grounds must be connected as well before any testing takes place.

=== Power Pins ===
Power shall be connected to the board as follows:
{| cellpadding=3 border=1 |
| '''Voltage'''
| '''Eurocard Pin'''
|-
| DGND
| A6
|-
| AGND
| A5
|-
| +5V
| A4
|-
| -5V
| A3
|-
| High voltage (DAC max out +10)
| A2
|}

=== Power Supply Sequencing ===
The control board is designed such that voltages may be supplied in any order so long as AGND and DGND are connected properly. However, for initial testing, the preferred order for powering up the board is as follows:

# Ensure AGND/DGND are connected/grounded
# +5V
# -5V
# High voltage

== FPGA ==
The control board uses a Xilinx XC3S50A VQ100 FPGA. It has a 100 pin footprint and is located in the center of the control board.

=== Power Details ===
The FPGA is powered by the 3.3V power plane, which is regulated by VR1. The FPGA also obtains 1.2V for its internal logic from a 1.2V power island, regulated by VR3.

=== Logic Standard ===
The Xilinx XC3S50A supports several different digital logic standards. The control board is hard wired such that the FPGA will use a '''3.3V CMOS''' logic standard.

=== Pinout Table ===
{| cellpadding=3 border=1 |
| '''Pin #'''
| '''Net Name'''
| '''Description'''
|-
| P1
| FPGA/TMS
| JTAG
|-
| P2
| FPGA/TDI
| JTAG
|-
| P3
| AD7928/CS
| SPI chip select for ADC
|-
| P4
| SPI
| '''Erroneously wired SPI bus trace''' Connects to SDO on temp. sensor and DIN on ADC
|-
| P5
| CLK_5MHZ
| 5 MHz clock output for SPI bus (ADC and temp. sensor)
|-
| P6
| No connection
|
|-
| P7
| No connection
|
|-
| P8
| DGND
|
|-
| P9
| No connection
|
|-
| P10
| No connection
|
|-
| P11
| +3.3V
|
|-
| P12
| No connection
|
|-
| P13
| No connection
|
|-
| P14
| DGND
|
|-
| P15
| No connection
|
|-
| P16
| No connection
|
|-
| P17
| +1.2V
|
|-
| P18
| DGND
|
|-
| P19
| No connection
|
|-
| P20
| No connection
|
|-
| P21
| No connection
|
|-
| P22
| +3.3V
|
|-
| P23
| DGND
|
|-
| P24
| DGND
|
|-
| P25
| DGND
|
|-
| P26
| +3.3V
|
|-
| P27
| FPGA/CLK_IN
| 20 MHz clock input from crystal oscillator
|-
| P28
| No connection
|
|-
| P29
| No connection
|
|-
| P30
| No connection
|
|-
| P31
| No connection
|
|-
| P32
| No connection
|
|-
| P33
| No connection
|
|-
| P34
| No connection
|
|-
| P35
| CP2201/INT
| Ethernet controller interrupt
|-
| P36
| MASTER_RESET
| Connects to RESET jumper in upper left of board (active-low, externally pulled up)
|-
| P37
| No connection
|
|-
| P38
| +1.2V
|
|-
| P39
| No connection
|
|-
| P40
| CP2201/CS
| Chip select for ethernet controller
|-
| P41
| CP2201/WR
| Write enable for ethernet controller
|-
| P42
| DGND
|
|-
| P43
| CP2201/RD
| Read enable for ethernet controller
|-
| P44
| CP2201/ALE
| Address line enable for ethernet controller
|-
| P45
| +3.3V
|
|-
| P46
| CP2201/RESET
| Reset pin for ethernet controller
|-
| P47
| DGND
|
|-
| P48
| FPGA/INIT_B
| Used during FPGA configuration - see Xilinx documentation
|-
| P49
| CP2201/AD0
| Ethernet controller address/data bus, bit 0
|-
| P50
| CP2201/AD1
| Ethernet controller address/data bus, bit 1
|-
| P51
| FPGA/DIN
| Serial data input from EEPROM for configuration
|-
| P52
| CP2201/AD2
| Ethernet controller address/data bus, bit 2
|-
| P53
| FPGA/CCLK
| Configuration clock (signal generated by FPGA at power on to clock the configuration process) See Xilinx documentation
|-
| P54
| FPGA/DONE
| Gives configuration status - see Xilinx documentation
|-
| P55
| +3.3V
|
|-
| P56
| CP2201/AD3
| Ethernet controller address/data bus, bit 3
|-
| P57
| CP2201/AD4
| Ethernet controller address/data bus, bit 4
|-
| P58
| DGND
|
|-
| P59
| CP2201/AD5
| Ethernet controller address/data bus, bit 5
|-
| P60
| CP2201/AD6
| Ethernet controller address/date bus, bit 6
|-
| P61
| CP2201/AD7
| Ethernet controller address/date bus, bit 7
|-
| P62
| No connection
|
|-
| P63
| DGND
|
|-
| P64
| No connection
|
|-
| P65
| No connection
|
|-
| P66
| +1.2V
|
|-
| P67
| +3.3V
|
|-
| P68
| +3.3V
|
|-
| P69
| DGND
|
|-
| P70
| ID3
| Backplane location identifier jumper, pins 3 & 4 Active-low, FPGA should pull high
|-
| P71
| ID2
| Backplane location identifier jumper, pins 5 & 6 Active-low, FPGA should pull high
|-
| P72
| ID1
| Backplane location identifier jumper, pins 7 & 8 Active-low, FPGA should pull high
|-
| P73
| ID0
| Backplane location identifier jumper, pins 9 & 10 Active-low, FPGA should pull high
|-
| P74
| DGND
|
|-
| P75
| FPGA/TDO
| JTAG
|-
| P76
| FPGA/TCK
| JTAG
|-
| P77
| ID4
| Backplane location identifier jumper, pins 1 & 2 Active-low, FPGA should pull high
|-
| P78
| No connection
|
|-
| P79
| +3.3V
|
|-
| P80
| DGND
|
|-
| P81
| +1.2V
|
|-
| P82
| No connection
|
|-
| P83
| CLK_5MHZ_2
| 5 MHz clock output for DAC
|-
| P84
| No connection
|
|-
| P85
| AD5535/DIN
| DAC serial data input (FPGA out -> DAC in)
|-
| P86
| No connection
|
|-
| P87
| DGND
|
|-
| P89
| No connection
|
|-
| P90
| No connection
|
|-
| P91
| DGND
|
|-
| P92
| +3.3V
|
|-
| P93
| AD7314/CE
| Chip enable for temperature sensor
|-
| P94
| No connection
|
|-
| P95
| DGND
|
|-
| P96
| +3.3V
|
|-
| P97
| AD7928/DOUT
| '''Erroneously wired ADC SPI bus connection''' Connects to DOUT on ADC
|-
| P98
| AD5535/RESET
| Reset pin for DAC
|-
| P99
| DGND
|
|-
| P100
| FPGA/PROG_B
| Used during FPGA configuration - see Xilinx documentation
|}

== EEPROM ==
To facilitate power-on configuration of the FPGA, the control board includes a Xilinx XCF01S EEPROM. The EEPROM is located to the left of the FPGA, above the JTAG header, and has a 20 pin footprint. The EEPROM is labelled U5.

=== Power Details ===
The EEPROM uses +3.3V exclusively, which it receives from the +3.3V power plane, regulated by VR1.

=== Flashing/Burning/Writing ===
Whatever you call it, this refers to storing data in the EEPROM so that it can configure the FPGA at power-on. The EEPROM is programmed using a JTAG interface and the Xilinx Platform USB II cable. It is important to note that in digital board's JTAG chain, the EEPROM is the first device in the chain, unlike in the Xilinx documentation where it is shown as the second device. This should not affect the operation of the board, but should be reflected in the Xilinx software when writing the EEPROM via JTAG.

=== FPGA Configuration ===
The EEPROM and FPGA are hardwired to use a master serial protocol to transfer the program from the EEPROM to the FPGA. This is the protocol recommended in the Xilinx documentation because it minimizes the number of traces necessary to run between the EEPROM and FPGA. All configuration data is sent over a single trace, FPGA/DIN (pin 1 on EEPROM), controlled by the configuration clock signal (FPGA/CCLK) which is automatically generated by the FPGA at power-on. When configuration is complete, FPGA/DONE (pin 10) is pulled high by the FPGA, and the EEPROM and configuration clock are deactivated.

=== Pinout Table ===
{| cellpadding=3 border=1 |
| '''Pin #'''
| '''Net Name'''
| '''Description'''
|-
| 1
| FPGA/DIN
| Serial data line Carries data from the EEPROM to the FPGA
|-
| 2
| No connection
|
|-
| 3
| FPGA/CCLK
| Configuration clock Auto generated by FPGA at power-on, disabled at end of configuration
|-
| 4
| EEPROM/TDI
| This is the EEPROM's TDI This is the entry point for the onboard JTAG chain
|-
| 5
| FPGA/TMS
| JTAG TMS Connects to both FPGA and EEPROM
|-
| 6
| FPGA/TCK
| JTAG TCK Connects to both FPGA and EEPROM
|-
| 7
| FPGA/PROG_B
| Used during configuration See Xilinx documentation
|-
| 8
| FPGA/INIT_B
| Used during configuration - can be used to intiate reconfiguration of FPGA See Xilinx documentation
|-
| 9
| No connection
|
|-
| 10
| FPGA/DONE
| Indicates completion of FPGA configuration High when complete
|-
| 11
| DGND
|
|-
| 12-16
| No connection
|
|-
| 17
| FPGA/TDI
| This is the EEPROM's TDO/FPGA's TDI
|-
| 18-20
| +3.3V
|
|}

== JTAG Header ==
To write the FPGA's program to the EEPROM, the board employs a JTAG based programming system consistent with Xilinx's recommendations. The system is designed to operate with Xilnx's Platform USB II cable and the flying lead adapter.

===Header Location and Size===
The header consists of 14 pins, 100 mil pitch, just below the EEPROM (U5). The header is labelled P1. The pitch of the pins in the header was erroneously selected to be 100 mil, which is not compatible with Xilinx's JTAG ribbon cable. Therefore, the Xilinx flying lead adapter must be used.

===Power Details===
The JTAG interface is powered by the +3.3V power plane, not by the computer's USB port. Power is supplied through pin 2 of the JTAG header.

===Pinout Table===
Note that the header is positioned on the board rotated 180 degrees from the position in which it is shown in the Xilinx documentation. Care must be taken when connecting the flying leads to ensure they are connected to the right pins. Connecting the flying leads to the wrong side of the header will cause all of the leads to short on the digital board's ground plane. This will certainly cause undesired operation, and may or may not cause damage. Improper wiring is most likely to cause damage if one of the flying leads is connected to an odd numbered pin. '''Note from the pinout table below that no flying lead connections should ever be made to the odd numbered pins on the JTAG header.'''

{| cellpadding=3 border=1 |
| '''Pin #'''
| '''Net Name'''
| '''Description'''
|-
| 1, 3, 5, 7, 9, 11, 13 (odd pins)
| DGND
| Ground pins for signal integrity '''Never connect a flying lead to these pins''' Doing so will short to ground and may cause permanent damage if the Platform USB II cable does not have protection against this.
|-
| 2
| +3.3V
| Power source for all JTAG logic
|-
| 4
| FPGA/TMS
| JTAG TMS - connects to EEPROM and FPGA
|-
| 6
| FPGA/TCK
| JTAG TCK - connects to EEPROM and FPGA
|-
| 8
| FPGA/TDO
| JTAG boundary scan chain endpoint
|-
| 10
| EEPROM/TDI
| JTAG boundary scan chain start point
|-
| 12
| No connection
| Pin is floating
|-
| 14
| No connection
| Pin is floating
|}

===JTAG Overview===
The JTAG interface is clocked by the TCK signal. TCK is generated by the Platform USB II cable, and connects directly from the JTAG header to both the EEPROM and FPGA.

The TMS signal is directly connected to both the EEPROM and FPGA, and is the data line over which JTAG test results (in this case programming results) are sent. TMS is used by only one component at a time.

The TDI/TDO lines form a chain that connects to each JTAG component in series. On the control board, the first point in the chain is the EEPROM's TDI. Next is the EEPROM's TDO, which is the same as the FPGA's TDI. The FPGA's TDO then returns to the JTAG header and the Platform USB II cable.

== DAC ==
The control board uses the Analog Devices AD5535, 32-channel, 200V max, digital to analog converter. This chip has a modified BC-124 BGA footprint and is located above the Eurocard connector at the bottom of the board. It is labelled U3.

=== Power Details ===
The DAC is primarily powered by the +5V power island, regulated by an off-board power supply and extensively decoupled in the area of the DAC. The DAC also requires -5V, and a high voltage as discussed in [[#Power Requirements | Power Requirements]]. Both of these voltages are supplied by an off-board supply and decoupled near the DAC. In addition to these voltage levels, the DAC requires a precise +2.5V reference, created by the shunt-type voltage reference VR4.

=== Setting the Output Range ===
The output range of the DAC is set by the 2.5V reference voltage supplied by VR4. The high voltage power supply must supply at a minimum 50 times this voltage, plus 10. Thus, the high voltage power supply should be at least 135V for DAC to operate properly, even though the SiPMs are expected to need only 40V. If it is convenient to use a lower high voltage, VR4 must be replaced to provide lower reference voltage. The high voltage may then be decreased appropriately. To summarize:

* Max output voltage = VREF*50
* Minimum high voltage supply = VREF*50 + 10
* Acceptable range for VREF
** Min: 1V
** Max: 3.75V (AD5535 datasheet specifies 4V max, but this would require AVCC of 5.25V for the DAC, which is not possible in the current board design)

If relevant, R13 is a 100K resistor.

=== Thermal Diode ===
The DAC has a built in thermal diode. The diode drop from anode to cathode is typically 0.65V at 25°C. It changes at a rate of -2.20mV/°C. The anode of this diode is connected to the +5V power island, and the cathode is connected to a 270K resistor to ground. The voltage between the cathode and the resistor is connected to VIN1 (pin 15) on the ADC.

=== Pinout Table ===
See documentation from Analog Devices.

=== Channel Mapping ===
Due to the layout of the balls on the footprint of the DAC, the DAC's internal channel numbers (which must be referenced by the FPGA) have no correlation to the channel numbers on the amplifier board. This table summarizes the mapping between various pins that belong to each channel.

{| cellpadding=3 border=1 |
| '''DAC Channel #'''
| '''DAC Pin #'''
| '''Digital Board Eurocard Pin #'''
| '''Amplifier Board Eurocard Pin #'''
| '''Amplifier Channel #'''
|-
| 0
| B1
| B3
|
|
|-
| 1
| A2
| C4
|
|
|-
| 2
| D1
| B2
|
|
|-
| 3
| C2
| C3
|
|
|-
| 4
| B3
| B4
|
|
|-
| 5
| E2
| C2
|
|
|-
| 6
| F3
| B1
|
|
|-
| 7
| A4
| B5
|
|
|-
| 8
| E4
| C5
|
|
|-
| 9
| B5
| C6
|
|
|-
| 10
| F5
| C1
|
|
|-
| 11
| A6
| C7
|
|
|-
| 12
| E6
| B6
|
|
|-
| 13
| B7
| B7
|
|
|-
| 14
| F7
| C10
|
|
|-
| 15
| E8
| C8
|
|
|-
| 16
| A8
| B8
|
|
|-
| 17
| B9
| C9
|
|
|-
| 18
| F9
| C16
|
|
|-
| 19
| E10
| B11
|
|
|-
| 20
| A10
| B9
|
|
|-
| 21
| B11
| B10
|
|
|-
| 22
| C12
| B12
|
|
|-
| 23
| D13
| B13
|
|
|-
| 24
| E12
| B14
|
|
|-
| 25
| A12
| C11
|
|
|-
| 26
| B13
| C12
|
|
|-
| 27
| H13
| B16
|
|
|-
| 28
| G14
| B15
|
|
|-
| 29
| C14
| C13
|
|
|-
| 30
| F13
| C15
|
|
|-
| 31
| E14
| C14
|
| DACHEALTH See [[#Channel Descriptions | ADC Channel Descriptions]].
|}

==ADC==
The board includes an Analog Devices AD7928 analog to digital converter. The ADC is located just to the right and slightly below the FPGA. It is labelled U4.

===Power Details===
The ADC is powered by the +5V power island, which is regulated by an off-board power supply and decoupled near the ADC. It also requires a precise (±1%) 2.5V reference to which it compares voltages when converting from analog to digital. Since the +5V power source is not used for comparison, it is flexible and may vary by ±0.25V without affecting ADC precision.

===Setting the Measuring Range===
The measuring range is set programmatically by the FPGA over the SPI bus. The way the ADC is connected on the digital board requires that its measuring range be set to 5V, so the RANGE bit should be set to 1 by the FPGA (see Analog Devices documentation).

===Data Interfacing===
The ADC uses an SPI bus to communicate with the FPGA. This bus is shared with the temperature sensor. SPI related pins include SCLK, CS, DIN, and DOUT. See the Pinout Table below.

===Channel Descriptions===
This table shows what signals are monitored by the ADC.

{| cellpadding=3 border=1 |
| '''ADC Channel #'''
| '''ADC Pin #'''
| '''Net Name'''
| '''Description'''
|-
| VIN0
| 16
| AD7928/VHEALTH
| This net helps to monitor to overall health of power on the board, but is specifically intended to monitor -5V. It's voltage is the output of a resistor divider between the +5 and -5V power supplies, with resistor values of 33.2K, and 100K. Assuming +5V and -5V are both correct, the output of the divider will be +2.51V. A reading of other than 2.51V indicates a problem with one of the power supplies. Problems with the +5V power supply can be ruled out by reading VIN3. Based on the reading from VIN3, the voltage of the -5V supply can be calculated.
|-
| VIN1
| 15
| AD5535/CATHODE
| This is the thermal diode output from the DAC. Should read 4.35V (typical) at 25°C. Drops 2.20mV/°C.
|-
| VIN2
| 14
| +3.3V
| This is the +3.3V power plane. A reading of other than +3.3V indicates a problem with VR1.
|-
| VIN3
| 13
| +5V
| This is the +5V power island. A reading of other than +5V indicates a problem with the +5V power supply.
|-
| VIN4
| 12
| ADC_EXT1
| This trace routes to the backplane via Eurocard pin A7. It is intended to measure the output of thermistor on the amplifier board.
|-
| VIN5
| 11
| +1.2V
| This is the +1.2V power island. This island powers the internal logic of the FPGA. A reading of other than 1.2V indicates a problem with VR3.
|-
| VIN6
| 10
| ADC_EXT2
| This trace routes to the backplane via Eurocard pin A8. It is intended to measure one of the transistor base voltages on the amplifier board.
|-
| VIN7
| 9
| DACHEALTH
| This channel monitors the output of a resistor divider connected to channel 31 of the DAC. The divider consists of three resistors of 200K, 200K, and 10.2K (in order). The ADC reads out the voltage level between the second 200K and then 10.2K resistor. These resistors were selected so that at 200V, the readout voltage will be 4.973V. Since the divider should be linear, the expected voltage at 20V is 0.4973V. Three resistors were used rather than two to avoid exceeding the resistors' power ratings when the DAC is set to its maximum voltage. Note that since this divider will consume up to 484uA of current at 200V, this DAC channel should not be used for anything that might require more than ~200uA of current (the DAC can source 700uA max). The channel is routed to the backplane nonetheless.
|}

===Pinout Table===
{| cellpadding=3 border=1 |
| '''Pin #'''
| '''Net Name'''
| '''Description'''
|-
| 1
| CLK_5MHZ
| SPI clock (SCLK), from FPGA Shared with temperature sensor
|-
| 2
| DIN
| SPI data in, from FPGA Shared with temperature sensor ''Currently wired wrong''
|-
| 3
| CS
| SPI chip select
|-
| 4
| AGND
|
|-
| 5
| +5V
| Power pin
|-
| 6
| +5V
| Power pin
|-
| 7
| AD7928/REF_IN
| +2.5V reference, set by VR2
|-
| 8
| AGND
|
|-
| 9-16
| VIN[7:0]
| See [[#Channel Descriptions | ADC Channel Descriptions]]
|-
| 17
| AGND
|
|-
| 18
| DOUT
| SPI data out ''Currently wired incorrectly''
|-
| 19
| +3.3V
| VDRIVE, powers the SPI logic
|-
| 20
| AGND
|
|}

== Ethernet Controller ==
The board uses a Silicon Laboratories CP2201, 28-pin, ethernet controller. The CP2201 is located just above the FPGA, and is labelled U2.

=== Power Details ===
The CP2201 uses only +3.3V, which is supplied by the +3.3V power plane and regulated by VR1. Appropriate decoupling capacitors can be found near the CP2201.

=== Ethernet Jack ===
To the right of the CP2201 is a Pulse J0011D21NL ethernet jack, labelled J1. This jack has a built-in 1:1 inductive coupling. For best results, connect this jack to a nearby ethernet switch. The jack may also be connected directly to a computer using a crossover cable. Though auto-crossover is not supported by the CP2201, if the computer's NIC supports it, a crossover cable is not necessary to connect directly to a computer.

==== Ethernet Jack Pins ====
These are visible only on the back side of the board. Pin 1 is indicated by a square pad. Pin 8 is the farthest pin from pin 1. Pins are numbered such that the 4 pins closer to the plastic thru-hole connectors are odd (1, 3, 5, 7), and the four pins closer to the CP2201 are are even (2, 4, 6, 8).

* Pin 1: TX+
* Pin 2: AC coupled to DGND
* Pin 3: TX-
* Pin 4: RX+
* Pin 5: AC coupled to DGND
* Pin 6: RX-
* Pin 7: No connection
* Pin 8: DGND (direct)

The two large thru-hole pins (not numbered) connect to the metal shielding on the outside of the jack. These are directly connected to DGND to shield against electrical noise inside the jack.

The two plastic thru-hole pins are not conductive and have no electrical connection. They are present only for structural purposes, presumably to prevent stress on the solder points when an ethernet wire is inserted or removed from the jack.

=== Crystal Oscillator ===
The CP2201 is responsible for driving the 20MHz crystal oscillator. This oscillator clocks both the CP2201 and the FPGA. The crystal oscillator can be found above the right corner of the FPGA. It can be identified by its four surface mount pads and roughly .3" length. It is labelled Y1, though this label is not visible after the oscillator is soldered on. The CP2201 uses an inverting driver to excite the crystal. The output of the crystal is then sent to the CP2201 and the FPGA.

=== Bus Format and Multiplexing ===
The 28-pin CP2201 used on the board only supports multiplexed operation. This means that both address and data information are passed over the same set of 8 traces. Hence, these traces are referred to as the address/data (AD) bus. A separate address line enable (ALE) trace prevents collisions from occuring on these traces. The communication protocol used is the Intel format. See the CP2201's datasheet for more information about this.

=== Pinout Table ===
{| cellpadding=3 border=1 |
| '''Pin #'''
| '''Net Name'''
| '''Description'''
|-
| 1
| CP2201/LA
| Link/activity indicator Routed to backplane but not implemented See CP2201 data sheet for information on how to connect to an LED
|-
| 2
| DGND
| By the data sheet, this pin should be AGND We deliberately set it to DGND to avoid noise on AGND plane
|-
| 3
| +3.3V
| AV+ power pin
|-
| 4
| CP2201/RX-
| Connects to RX- on ethernet jack
|-
| 5
| CP2201/RX+
| Connects to RX+ on ethernet jack
|-
| 6
| CP2201/TX+
| Connects to TX+ on ethernet jack
|-
| 7
| CP2201/TX-
| Connects to TX- on ethernet jack
|-
| 8
| +3.3V
| "VDD" power pin
|-
| 9
| DGND
| "DGND1" per the data sheet
|-
| 10
| CP2201/RESET
| "RST" per the data sheet Connects to FPGA - should be programmatically triggered upon reset of FPGA by RESET jumper
|-
| 11-18
| CP2201/AD[0:7]
| Bits 0-7 of the address/data bus Connect to FPGA
|-
| 19
| +3.3V
| "VDD" power pin
|-
| 20
| DGND
| "DGND2" per the data sheet
|-
| 21
| CP2201/ALE
| Address line enable Connects to FPGA See CP2201 documentation
|-
| 22
| CP2201/RD
| Read strobe for AD bus Connects to FPGA See CP2201 documentation
|-
| 23
| CP2201/WR
| Write strobe for AD bus Connects to FPGA See CP2201 documentation
|-
| 24
| CP2201/CS
| Chip select Connects to FPGA
|-
| 25
| CP2201/INT
| Interrupt request Connects to FPGA
|-
| 26
| DGND
| "MOTEN" (Motorola enable) per the datasheet Tied low to disable Motorola bus format (enable Intel format)
|-
| 27
| CP2201/XTAL2
| Crystal oscillator driver The CP2201 inverts the 20MHz clock signal and feeds it back to the crystal oscillator to encourage larger oscillations
|-
| 28
| FPGA/CLK_IN
| "XTAL1" per the data sheet This is the 20MHz clock input Also connects to the FPGA's clock input
|-
| 29*
| DGND
| This is not a pin but rather the base of the CP2201 package. It is connected to the DGND plane for thermal relief
|}

== Eurocard Connector ==
At the bottom of the control board is the Eurocard connector. The Eurocard connector connects the board to the backplane and also connects the board to its power supplies. The Eurocard has 48 pins arranged in three rows of 16 pins each. Rows B and C are exclusively used to pass SiPM bias voltages to the backplane as described in [[#Channel Mapping | DAC Channel Mapping]]. Here is a table describing the purpose of pins in row A:

=== Row A Pinout Table ===
Note that when viewing the front side of the board with the Eurocard at the bottom, these pins go from right to left. If you look closely at the pins, you will see that pin A1 has a square pad, unlike the round pads of the others.

{| cellpadding=3 border=1 |
| '''Pin #'''
| '''Net Name'''
| '''Description'''
|-
| A1
| CP2201/LA
| Ethernet link/activity indicator routed to backplane
|-
| A2
| High voltage input (+210V max)
| High voltage input for DAC. See [[#DAC | DAC]] for information about what voltage to input here.
|-
| A3
| -5V
| For DAC
|-
| A4
| +5V
| Powers most things on the board
|-
| A5
| AGND
|
|-
| A6
| DGND
|
|-
| A7
| ADC_EXT1
| Connects to ADC to monitor voltages on amplifier board See [[#ADC | ADC]]
|-
| A8
| ADC_EXT2
| Connects to ADC to monitor voltages on amplifier board See [[#ADC | ADC]]
|-
| A9
| No connection
|
|-
| A10
| No connection
|
|-
| A11
| No conneciton
|
|-
| A12
| ID4
| Location identifier bit 4 Used to identify which backplane board is connected to See [[#FPGA | FPGA]]
|-
| A13
| ID3
| Location identifier bit 3 Used to identify which backplane board is connected to See [[#FPGA | FPGA]]
|-
| A14
| ID2
| Location identifier bit 2 Used to identify which backplane board is connected to See [[#FPGA | FPGA]]
|-
| A15
| ID1
| Location identifier bit 1 Used to identify which backplane board is connected to See [[#FPGA | FPGA]]
|-
| A16
| ID0
| Location identifier bit 0 Used to identify which backplane board is connected to See [[#FPGA | FPGA]]
|}

Digital control board documentation

2009-06-16T19:22:43Z

Underwood: /* Ethernet Jack Pins */

This documentation covers the most important things to know while testing the digital control board, including component pinouts, nets, and other information.

== Power Requirements ==
=== Required Voltages ===
All components on the digital board '''except the DAC''' can be tested using only a +5V source. The DAC requires +5V, -5V, and a high voltage corresponding to 10V higher than the maximum desired DAC output voltage (see [[#Setting the Output Range | Setting the Output Range]]). Digital and analog grounds must be connected as well before any testing takes place.

=== Power Pins ===
Power shall be connected to the board as follows:
{| cellpadding=3 border=1 |
| '''Voltage'''
| '''Eurocard Pin'''
|-
| DGND
| A6
|-
| AGND
| A5
|-
| +5V
| A4
|-
| -5V
| A3
|-
| High voltage (DAC max out +10)
| A2
|}

=== Power Supply Sequencing ===
The control board is designed such that voltages may be supplied in any order so long as AGND and DGND are connected properly. However, for initial testing, the preferred order for powering up the board is as follows:

# Ensure AGND/DGND are connected/grounded
# +5V
# -5V
# High voltage

== FPGA ==
The control board uses a Xilinx XC3S50A VQ100 FPGA. It has a 100 pin footprint and is located in the center of the control board.

=== Power Details ===
The FPGA is powered by the 3.3V power plane, which is regulated by VR1. The FPGA also obtains 1.2V for its internal logic from a 1.2V power island, regulated by VR3.

=== Logic Standard ===
The Xilinx XC3S50A supports several different digital logic standards. The control board is hard wired such that the FPGA will use a '''3.3V CMOS''' logic standard.

=== Pinout Table ===
{| cellpadding=3 border=1 |
| '''Pin #'''
| '''Net Name'''
| '''Description'''
|-
| P1
| FPGA/TMS
| JTAG
|-
| P2
| FPGA/TDI
| JTAG
|-
| P3
| AD7928/CS
| SPI chip select for ADC
|-
| P4
| SPI
| '''Erroneously wired SPI bus trace''' Connects to SDO on temp. sensor and DIN on ADC
|-
| P5
| CLK_5MHZ
| 5 MHz clock output for SPI bus (ADC and temp. sensor)
|-
| P6
| No connection
|
|-
| P7
| No connection
|
|-
| P8
| DGND
|
|-
| P9
| No connection
|
|-
| P10
| No connection
|
|-
| P11
| +3.3V
|
|-
| P12
| No connection
|
|-
| P13
| No connection
|
|-
| P14
| DGND
|
|-
| P15
| No connection
|
|-
| P16
| No connection
|
|-
| P17
| +1.2V
|
|-
| P18
| DGND
|
|-
| P19
| No connection
|
|-
| P20
| No connection
|
|-
| P21
| No connection
|
|-
| P22
| +3.3V
|
|-
| P23
| DGND
|
|-
| P24
| DGND
|
|-
| P25
| DGND
|
|-
| P26
| +3.3V
|
|-
| P27
| FPGA/CLK_IN
| 20 MHz clock input from crystal oscillator
|-
| P28
| No connection
|
|-
| P29
| No connection
|
|-
| P30
| No connection
|
|-
| P31
| No connection
|
|-
| P32
| No connection
|
|-
| P33
| No connection
|
|-
| P34
| No connection
|
|-
| P35
| CP2201/INT
| Ethernet controller interrupt
|-
| P36
| MASTER_RESET
| Connects to RESET jumper in upper left of board (active-low, externally pulled up)
|-
| P37
| No connection
|
|-
| P38
| +1.2V
|
|-
| P39
| No connection
|
|-
| P40
| CP2201/CS
| Chip select for ethernet controller
|-
| P41
| CP2201/WR
| Write enable for ethernet controller
|-
| P42
| DGND
|
|-
| P43
| CP2201/RD
| Read enable for ethernet controller
|-
| P44
| CP2201/ALE
| Address line enable for ethernet controller
|-
| P45
| +3.3V
|
|-
| P46
| CP2201/RESET
| Reset pin for ethernet controller
|-
| P47
| DGND
|
|-
| P48
| FPGA/INIT_B
| Used during FPGA configuration - see Xilinx documentation
|-
| P49
| CP2201/AD0
| Ethernet controller address/data bus, bit 0
|-
| P50
| CP2201/AD1
| Ethernet controller address/data bus, bit 1
|-
| P51
| FPGA/DIN
| Serial data input from EEPROM for configuration
|-
| P52
| CP2201/AD2
| Ethernet controller address/data bus, bit 2
|-
| P53
| FPGA/CCLK
| Configuration clock (signal generated by FPGA at power on to clock the configuration process) See Xilinx documentation
|-
| P54
| FPGA/DONE
| Gives configuration status - see Xilinx documentation
|-
| P55
| +3.3V
|
|-
| P56
| CP2201/AD3
| Ethernet controller address/data bus, bit 3
|-
| P57
| CP2201/AD4
| Ethernet controller address/data bus, bit 4
|-
| P58
| DGND
|
|-
| P59
| CP2201/AD5
| Ethernet controller address/data bus, bit 5
|-
| P60
| CP2201/AD6
| Ethernet controller address/date bus, bit 6
|-
| P61
| CP2201/AD7
| Ethernet controller address/date bus, bit 7
|-
| P62
| No connection
|
|-
| P63
| DGND
|
|-
| P64
| No connection
|
|-
| P65
| No connection
|
|-
| P66
| +1.2V
|
|-
| P67
| +3.3V
|
|-
| P68
| +3.3V
|
|-
| P69
| DGND
|
|-
| P70
| ID3
| Backplane location identifier jumper, pins 3 & 4 Active-low, FPGA should pull high
|-
| P71
| ID2
| Backplane location identifier jumper, pins 5 & 6 Active-low, FPGA should pull high
|-
| P72
| ID1
| Backplane location identifier jumper, pins 7 & 8 Active-low, FPGA should pull high
|-
| P73
| ID0
| Backplane location identifier jumper, pins 9 & 10 Active-low, FPGA should pull high
|-
| P74
| DGND
|
|-
| P75
| FPGA/TDO
| JTAG
|-
| P76
| FPGA/TCK
| JTAG
|-
| P77
| ID4
| Backplane location identifier jumper, pins 1 & 2 Active-low, FPGA should pull high
|-
| P78
| No connection
|
|-
| P79
| +3.3V
|
|-
| P80
| DGND
|
|-
| P81
| +1.2V
|
|-
| P82
| No connection
|
|-
| P83
| CLK_5MHZ_2
| 5 MHz clock output for DAC
|-
| P84
| No connection
|
|-
| P85
| AD5535/DIN
| DAC serial data input (FPGA out -> DAC in)
|-
| P86
| No connection
|
|-
| P87
| DGND
|
|-
| P89
| No connection
|
|-
| P90
| No connection
|
|-
| P91
| DGND
|
|-
| P92
| +3.3V
|
|-
| P93
| AD7314/CE
| Chip enable for temperature sensor
|-
| P94
| No connection
|
|-
| P95
| DGND
|
|-
| P96
| +3.3V
|
|-
| P97
| AD7928/DOUT
| '''Erroneously wired ADC SPI bus connection''' Connects to DOUT on ADC
|-
| P98
| AD5535/RESET
| Reset pin for DAC
|-
| P99
| DGND
|
|-
| P100
| FPGA/PROG_B
| Used during FPGA configuration - see Xilinx documentation
|}

== EEPROM ==
To facilitate power-on configuration of the FPGA, the control board includes a Xilinx XCF01S EEPROM. The EEPROM is located to the left of the FPGA, above the JTAG header, and has a 20 pin footprint. The EEPROM is labelled U5.

=== Power Details ===
The EEPROM uses +3.3V exclusively, which it receives from the +3.3V power plane, regulated by VR1.

=== Flashing/Burning/Writing ===
Whatever you call it, this refers to storing data in the EEPROM so that it can configure the FPGA at power-on. The EEPROM is programmed using a JTAG interface and the Xilinx Platform USB II cable. It is important to note that in digital board's JTAG chain, the EEPROM is the first device in the chain, unlike in the Xilinx documentation where it is shown as the second device. This should not affect the operation of the board, but should be reflected in the Xilinx software when writing the EEPROM via JTAG.

=== FPGA Configuration ===
The EEPROM and FPGA are hardwired to use a master serial protocol to transfer the program from the EEPROM to the FPGA. This is the protocol recommended in the Xilinx documentation because it minimizes the number of traces necessary to run between the EEPROM and FPGA. All configuration data is sent over a single trace, FPGA/DIN (pin 1 on EEPROM), controlled by the configuration clock signal (FPGA/CCLK) which is automatically generated by the FPGA at power-on. When configuration is complete, FPGA/DONE (pin 10) is pulled high by the FPGA, and the EEPROM and configuration clock are deactivated.

=== Pinout Table ===
{| cellpadding=3 border=1 |
| '''Pin #'''
| '''Net Name'''
| '''Description'''
|-
| 1
| FPGA/DIN
| Serial data line Carries data from the EEPROM to the FPGA
|-
| 2
| No connection
|
|-
| 3
| FPGA/CCLK
| Configuration clock Auto generated by FPGA at power-on, disabled at end of configuration
|-
| 4
| EEPROM/TDI
| This is the EEPROM's TDI This is the entry point for the onboard JTAG chain
|-
| 5
| FPGA/TMS
| JTAG TMS Connects to both FPGA and EEPROM
|-
| 6
| FPGA/TCK
| JTAG TCK Connects to both FPGA and EEPROM
|-
| 7
| FPGA/PROG_B
| Used during configuration See Xilinx documentation
|-
| 8
| FPGA/INIT_B
| Used during configuration - can be used to intiate reconfiguration of FPGA See Xilinx documentation
|-
| 9
| No connection
|
|-
| 10
| FPGA/DONE
| Indicates completion of FPGA configuration High when complete
|-
| 11
| DGND
|
|-
| 12-16
| No connection
|
|-
| 17
| FPGA/TDI
| This is the EEPROM's TDO/FPGA's TDI
|-
| 18-20
| +3.3V
|
|}

== JTAG Header ==
To write the FPGA's program to the EEPROM, the board employs a JTAG based programming system consistent with Xilinx's recommendations. The system is designed to operate with Xilnx's Platform USB II cable and the flying lead adapter.

===Header Location and Size===
The header consists of 14 pins, 100 mil pitch, just below the EEPROM (U5). The header is labelled P1. The pitch of the pins in the header was erroneously selected to be 100 mil, which is not compatible with Xilinx's JTAG ribbon cable. Therefore, the Xilinx flying lead adapter must be used.

===Power Details===
The JTAG interface is powered by the +3.3V power plane, not by the computer's USB port. Power is supplied through pin 2 of the JTAG header.

===Pinout Table===
Note that the header is positioned on the board rotated 180 degrees from the position in which it is shown in the Xilinx documentation. Care must be taken when connecting the flying leads to ensure they are connected to the right pins. Connecting the flying leads to the wrong side of the header will cause all of the leads to short on the digital board's ground plane. This will certainly cause undesired operation, and may or may not cause damage. Improper wiring is most likely to cause damage if one of the flying leads is connected to an odd numbered pin. '''Note from the pinout table below that no flying lead connections should ever be made to the odd numbered pins on the JTAG header.'''

{| cellpadding=3 border=1 |
| '''Pin #'''
| '''Net Name'''
| '''Description'''
|-
| 1, 3, 5, 7, 9, 11, 13 (odd pins)
| DGND
| Ground pins for signal integrity '''Never connect a flying lead to these pins''' Doing so will short to ground and may cause permanent damage if the Platform USB II cable does not have protection against this.
|-
| 2
| +3.3V
| Power source for all JTAG logic
|-
| 4
| FPGA/TMS
| JTAG TMS - connects to EEPROM and FPGA
|-
| 6
| FPGA/TCK
| JTAG TCK - connects to EEPROM and FPGA
|-
| 8
| FPGA/TDO
| JTAG boundary scan chain endpoint
|-
| 10
| EEPROM/TDI
| JTAG boundary scan chain start point
|-
| 12
| No connection
| Pin is floating
|-
| 14
| No connection
| Pin is floating
|}

===JTAG Overview===
The JTAG interface is clocked by the TCK signal. TCK is generated by the Platform USB II cable, and connects directly from the JTAG header to both the EEPROM and FPGA.

The TMS signal is directly connected to both the EEPROM and FPGA, and is the data line over which JTAG test results (in this case programming results) are sent. TMS is used by only one component at a time.

The TDI/TDO lines form a chain that connects to each JTAG component in series. On the control board, the first point in the chain is the EEPROM's TDI. Next is the EEPROM's TDO, which is the same as the FPGA's TDI. The FPGA's TDO then returns to the JTAG header and the Platform USB II cable.

== DAC ==
The control board uses the Analog Devices AD5535, 32-channel, 200V max, digital to analog converter. This chip has a modified BC-124 BGA footprint and is located above the Eurocard connector at the bottom of the board. It is labelled U3.

=== Power Details ===
The DAC is primarily powered by the +5V power island, regulated by an off-board power supply and extensively decoupled in the area of the DAC. The DAC also requires -5V, and a high voltage as discussed in [[#Power Requirements | Power Requirements]]. Both of these voltages are supplied by an off-board supply and decoupled near the DAC. In addition to these voltage levels, the DAC requires a precise +2.5V reference, created by the shunt-type voltage reference VR4.

=== Setting the Output Range ===
The output range of the DAC is set by the 2.5V reference voltage supplied by VR4. The high voltage power supply must supply at a minimum 50 times this voltage, plus 10. Thus, the high voltage power supply should be at least 135V for DAC to operate properly, even though the SiPMs are expected to need only 40V. If it is convenient to use a lower high voltage, VR4 must be replaced to provide lower reference voltage. The high voltage may then be decreased appropriately. To summarize:

* Max output voltage = VREF*50
* Minimum high voltage supply = VREF*50 + 10
* Acceptable range for VREF
** Min: 1V
** Max: 3.75V (AD5535 datasheet specifies 4V max, but this would require AVCC of 5.25V for the DAC, which is not possible in the current board design)

If relevant, R13 is a 100K resistor.

=== Thermal Diode ===
The DAC has a built in thermal diode. The diode drop from anode to cathode is typically 0.65V at 25°C. It changes at a rate of -2.20mV/°C. The anode of this diode is connected to the +5V power island, and the cathode is connected to a 270K resistor to ground. The voltage between the cathode and the resistor is connected to VIN1 (pin 15) on the ADC.

=== Pinout Table ===
See documentation from Analog Devices.

=== Channel Mapping ===
Due to the layout of the balls on the footprint of the DAC, the DAC's internal channel numbers (which must be referenced by the FPGA) have no correlation to the channel numbers on the amplifier board. This table summarizes the mapping between various pins that belong to each channel.

{| cellpadding=3 border=1 |
| '''DAC Channel #'''
| '''DAC Pin #'''
| '''Digital Board Eurocard Pin #'''
| '''Amplifier Board Eurocard Pin #'''
| '''Physical Channel #'''
|-
| 0
| B1
| B3
|
|
|-
| 1
| A2
| C4
|
|
|-
| 2
| D1
| B2
|
|
|-
| 3
| C2
| C3
|
|
|-
| 4
| B3
| B4
|
|
|-
| 5
| E2
| C2
|
|
|-
| 6
| F3
| B1
|
|
|-
| 7
| A4
| B5
|
|
|-
| 8
| E4
| C5
|
|
|-
| 9
| B5
| C6
|
|
|-
| 10
| F5
| C1
|
|
|-
| 11
| A6
| C7
|
|
|-
| 12
| E6
| B6
|
|
|-
| 13
| B7
| B7
|
|
|-
| 14
| F7
| C10
|
|
|-
| 15
| E8
| C8
|
|
|-
| 16
| A8
| B8
|
|
|-
| 17
| B9
| C9
|
|
|-
| 18
| F9
| C16
|
|
|-
| 19
| E10
| B11
|
|
|-
| 20
| A10
| B9
|
|
|-
| 21
| B11
| B10
|
|
|-
| 22
| C12
| B12
|
|
|-
| 23
| D13
| B13
|
|
|-
| 24
| E12
| B14
|
|
|-
| 25
| A12
| C11
|
|
|-
| 26
| B13
| C12
|
|
|-
| 27
| H13
| B16
|
|
|-
| 28
| G14
| B15
|
|
|-
| 29
| C14
| C13
|
|
|-
| 30
| F13
| C15
|
|
|-
| 31
| E14
| C14
|
| DACHEALTH See [[#Channel Descriptions | ADC Channel Descriptions]].
|}

==ADC==
The board includes an Analog Devices AD7928 analog to digital converter. The ADC is located just to the right and slightly below the FPGA. It is labelled U4.

===Power Details===
The ADC is powered by the +5V power island, which is regulated by an off-board power supply and decoupled near the ADC. It also requires a precise (±1%) 2.5V reference to which it compares voltages when converting from analog to digital. Since the +5V power source is not used for comparison, it is flexible and may vary by ±0.25V without affecting ADC precision.

===Setting the Measuring Range===
The measuring range is set programmatically by the FPGA over the SPI bus. The way the ADC is connected on the digital board requires that its measuring range be set to 5V, so the RANGE bit should be set to 1 by the FPGA (see Analog Devices documentation).

===Data Interfacing===
The ADC uses an SPI bus to communicate with the FPGA. This bus is shared with the temperature sensor. SPI related pins include SCLK, CS, DIN, and DOUT. See the Pinout Table below.

===Channel Descriptions===
This table shows what signals are monitored by the ADC.

{| cellpadding=3 border=1 |
| '''ADC Channel #'''
| '''ADC Pin #'''
| '''Net Name'''
| '''Description'''
|-
| VIN0
| 16
| AD7928/VHEALTH
| This net helps to monitor to overall health of power on the board, but is specifically intended to monitor -5V. It's voltage is the output of a resistor divider between the +5 and -5V power supplies, with resistor values of 33.2K, and 100K. Assuming +5V and -5V are both correct, the output of the divider will be +2.51V. A reading of other than 2.51V indicates a problem with one of the power supplies. Problems with the +5V power supply can be ruled out by reading VIN3. Based on the reading from VIN3, the voltage of the -5V supply can be calculated.
|-
| VIN1
| 15
| AD5535/CATHODE
| This is the thermal diode output from the DAC. Should read 4.35V (typical) at 25°C. Drops 2.20mV/°C.
|-
| VIN2
| 14
| +3.3V
| This is the +3.3V power plane. A reading of other than +3.3V indicates a problem with VR1.
|-
| VIN3
| 13
| +5V
| This is the +5V power island. A reading of other than +5V indicates a problem with the +5V power supply.
|-
| VIN4
| 12
| ADC_EXT1
| This trace routes to the backplane via Eurocard pin A7. It is intended to measure the output of thermistor on the amplifier board.
|-
| VIN5
| 11
| +1.2V
| This is the +1.2V power island. This island powers the internal logic of the FPGA. A reading of other than 1.2V indicates a problem with VR3.
|-
| VIN6
| 10
| ADC_EXT2
| This trace routes to the backplane via Eurocard pin A8. It is intended to measure one of the transistor base voltages on the amplifier board.
|-
| VIN7
| 9
| DACHEALTH
| This channel monitors the output of a resistor divider connected to channel 31 of the DAC. The divider consists of three resistors of 200K, 200K, and 10.2K (in order). The ADC reads out the voltage level between the second 200K and then 10.2K resistor. These resistors were selected so that at 200V, the readout voltage will be 4.973V. Since the divider should be linear, the expected voltage at 20V is 0.4973V. Three resistors were used rather than two to avoid exceeding the resistors' power ratings when the DAC is set to its maximum voltage. Note that since this divider will consume up to 484uA of current at 200V, this DAC channel should not be used for anything that might require more than ~200uA of current (the DAC can source 700uA max). The channel is routed to the backplane nonetheless.
|}

===Pinout Table===
{| cellpadding=3 border=1 |
| '''Pin #'''
| '''Net Name'''
| '''Description'''
|-
| 1
| CLK_5MHZ
| SPI clock (SCLK), from FPGA Shared with temperature sensor
|-
| 2
| DIN
| SPI data in, from FPGA Shared with temperature sensor ''Currently wired wrong''
|-
| 3
| CS
| SPI chip select
|-
| 4
| AGND
|
|-
| 5
| +5V
| Power pin
|-
| 6
| +5V
| Power pin
|-
| 7
| AD7928/REF_IN
| +2.5V reference, set by VR2
|-
| 8
| AGND
|
|-
| 9-16
| VIN[7:0]
| See [[#Channel Descriptions | ADC Channel Descriptions]]
|-
| 17
| AGND
|
|-
| 18
| DOUT
| SPI data out ''Currently wired incorrectly''
|-
| 19
| +3.3V
| VDRIVE, powers the SPI logic
|-
| 20
| AGND
|
|}

== Ethernet Controller ==
The board uses a Silicon Laboratories CP2201, 28-pin, ethernet controller. The CP2201 is located just above the FPGA, and is labelled U2.

=== Power Details ===
The CP2201 uses only +3.3V, which is supplied by the +3.3V power plane and regulated by VR1. Appropriate decoupling capacitors can be found near the CP2201.

=== Ethernet Jack ===
To the right of the CP2201 is a Pulse J0011D21NL ethernet jack, labelled J1. This jack has a built-in 1:1 inductive coupling. For best results, connect this jack to a nearby ethernet switch. The jack may also be connected directly to a computer using a crossover cable. Though auto-crossover is not supported by the CP2201, if the computer's NIC supports it, a crossover cable is not necessary to connect directly to a computer.

==== Ethernet Jack Pins ====
These are visible only on the back side of the board. Pin 1 is indicated by a square pad. Pin 8 is the farthest pin from pin 1. Pins are numbered such that the 4 pins closer to the plastic thru-hole connectors are odd (1, 3, 5, 7), and the four pins closer to the CP2201 are are even (2, 4, 6, 8).

* Pin 1: TX+
* Pin 2: AC coupled to DGND
* Pin 3: TX-
* Pin 4: RX+
* Pin 5: AC coupled to DGND
* Pin 6: RX-
* Pin 7: No connection
* Pin 8: DGND (direct)

The two large thru-hole pins (not numbered) connect to the metal shielding on the outside of the jack. These are directly connected to DGND to shield against electrical noise inside the jack.

The two plastic thru-hole pins are not conductive and have no electrical connection. They are present only for structural purposes, presumably to prevent stress on the solder points when an ethernet wire is inserted or removed from the jack.

=== Crystal Oscillator ===
The CP2201 is responsible for driving the 20MHz crystal oscillator. This oscillator clocks both the CP2201 and the FPGA. The crystal oscillator can be found above the right corner of the FPGA. It can be identified by its four surface mount pads and roughly .3" length. It is labelled Y1, though this label is not visible after the oscillator is soldered on. The CP2201 uses an inverting driver to excite the crystal. The output of the crystal is then sent to the CP2201 and the FPGA.

=== Bus Format and Multiplexing ===
The 28-pin CP2201 used on the board only supports multiplexed operation. This means that both address and data information are passed over the same set of 8 traces. Hence, these traces are referred to as the address/data (AD) bus. A separate address line enable (ALE) trace prevents collisions from occuring on these traces. The communication protocol used is the Intel format. See the CP2201's datasheet for more information about this.

=== Pinout Table ===
{| cellpadding=3 border=1 |
| '''Pin #'''
| '''Net Name'''
| '''Description'''
|-
| 1
| CP2201/LA
| Link/activity indicator Routed to backplane but not implemented See CP2201 data sheet for information on how to connect to an LED
|-
| 2
| DGND
| By the data sheet, this pin should be AGND We deliberately set it to DGND to avoid noise on AGND plane
|-
| 3
| +3.3V
| AV+ power pin
|-
| 4
| CP2201/RX-
| Connects to RX- on ethernet jack
|-
| 5
| CP2201/RX+
| Connects to RX+ on ethernet jack
|-
| 6
| CP2201/TX+
| Connects to TX+ on ethernet jack
|-
| 7
| CP2201/TX-
| Connects to TX- on ethernet jack
|-
| 8
| +3.3V
| "VDD" power pin
|-
| 9
| DGND
| "DGND1" per the data sheet
|-
| 10
| CP2201/RESET
| "RST" per the data sheet Connects to FPGA - should be programmatically triggered upon reset of FPGA by RESET jumper
|-
| 11-18
| CP2201/AD[0:7]
| Bits 0-7 of the address/data bus Connect to FPGA
|-
| 19
| +3.3V
| "VDD" power pin
|-
| 20
| DGND
| "DGND2" per the data sheet
|-
| 21
| CP2201/ALE
| Address line enable Connects to FPGA See CP2201 documentation
|-
| 22
| CP2201/RD
| Read strobe for AD bus Connects to FPGA See CP2201 documentation
|-
| 23
| CP2201/WR
| Write strobe for AD bus Connects to FPGA See CP2201 documentation
|-
| 24
| CP2201/CS
| Chip select Connects to FPGA
|-
| 25
| CP2201/INT
| Interrupt request Connects to FPGA
|-
| 26
| DGND
| "MOTEN" (Motorola enable) per the datasheet Tied low to disable Motorola bus format (enable Intel format)
|-
| 27
| CP2201/XTAL2
| Crystal oscillator driver The CP2201 inverts the 20MHz clock signal and feeds it back to the crystal oscillator to encourage larger oscillations
|-
| 28
| FPGA/CLK_IN
| "XTAL1" per the data sheet This is the 20MHz clock input Also connects to the FPGA's clock input
|-
| 29*
| DGND
| This is not a pin but rather the base of the CP2201 package. It is connected to the DGND plane for thermal relief
|}

== Eurocard Connector ==
At the bottom of the control board is the Eurocard connector. The Eurocard connector connects the board to the backplane and also connects the board to its power supplies. The Eurocard has 48 pins arranged in three rows of 16 pins each. Rows B and C are exclusively used to pass SiPM bias voltages to the backplane as described in [[#Channel Mapping | DAC Channel Mapping]]. Here is a table describing the purpose of pins in row A:

=== Row A Pinout Table ===
Note that when viewing the front side of the board with the Eurocard at the bottom, these pins go from right to left. If you look closely at the pins, you will see that pin A1 has a square pad, unlike the round pads of the others.

{| cellpadding=3 border=1 |
| '''Pin #'''
| '''Net Name'''
| '''Description'''
|-
| A1
| CP2201/LA
| Ethernet link/activity indicator routed to backplane
|-
| A2
| High voltage input (+210V max)
| High voltage input for DAC. See [[#DAC | DAC]] for information about what voltage to input here.
|-
| A3
| -5V
| For DAC
|-
| A4
| +5V
| Powers most things on the board
|-
| A5
| AGND
|
|-
| A6
| DGND
|
|-
| A7
| ADC_EXT1
| Connects to ADC to monitor voltages on amplifier board See [[#ADC | ADC]]
|-
| A8
| ADC_EXT2
| Connects to ADC to monitor voltages on amplifier board See [[#ADC | ADC]]
|-
| A9
| No connection
|
|-
| A10
| No connection
|
|-
| A11
| No conneciton
|
|-
| A12
| ID4
| Location identifier bit 4 Used to identify which backplane board is connected to See [[#FPGA | FPGA]]
|-
| A13
| ID3
| Location identifier bit 3 Used to identify which backplane board is connected to See [[#FPGA | FPGA]]
|-
| A14
| ID2
| Location identifier bit 2 Used to identify which backplane board is connected to See [[#FPGA | FPGA]]
|-
| A15
| ID1
| Location identifier bit 1 Used to identify which backplane board is connected to See [[#FPGA | FPGA]]
|-
| A16
| ID0
| Location identifier bit 0 Used to identify which backplane board is connected to See [[#FPGA | FPGA]]
|}

Digital control board documentation

2009-06-16T19:21:54Z

Underwood: /* Ethernet Jack Pins */

This documentation covers the most important things to know while testing the digital control board, including component pinouts, nets, and other information.

== Power Requirements ==
=== Required Voltages ===
All components on the digital board '''except the DAC''' can be tested using only a +5V source. The DAC requires +5V, -5V, and a high voltage corresponding to 10V higher than the maximum desired DAC output voltage (see [[#Setting the Output Range | Setting the Output Range]]). Digital and analog grounds must be connected as well before any testing takes place.

=== Power Pins ===
Power shall be connected to the board as follows:
{| cellpadding=3 border=1 |
| '''Voltage'''
| '''Eurocard Pin'''
|-
| DGND
| A6
|-
| AGND
| A5
|-
| +5V
| A4
|-
| -5V
| A3
|-
| High voltage (DAC max out +10)
| A2
|}

=== Power Supply Sequencing ===
The control board is designed such that voltages may be supplied in any order so long as AGND and DGND are connected properly. However, for initial testing, the preferred order for powering up the board is as follows:

# Ensure AGND/DGND are connected/grounded
# +5V
# -5V
# High voltage

== FPGA ==
The control board uses a Xilinx XC3S50A VQ100 FPGA. It has a 100 pin footprint and is located in the center of the control board.

=== Power Details ===
The FPGA is powered by the 3.3V power plane, which is regulated by VR1. The FPGA also obtains 1.2V for its internal logic from a 1.2V power island, regulated by VR3.

=== Logic Standard ===
The Xilinx XC3S50A supports several different digital logic standards. The control board is hard wired such that the FPGA will use a '''3.3V CMOS''' logic standard.

=== Pinout Table ===
{| cellpadding=3 border=1 |
| '''Pin #'''
| '''Net Name'''
| '''Description'''
|-
| P1
| FPGA/TMS
| JTAG
|-
| P2
| FPGA/TDI
| JTAG
|-
| P3
| AD7928/CS
| SPI chip select for ADC
|-
| P4
| SPI
| '''Erroneously wired SPI bus trace''' Connects to SDO on temp. sensor and DIN on ADC
|-
| P5
| CLK_5MHZ
| 5 MHz clock output for SPI bus (ADC and temp. sensor)
|-
| P6
| No connection
|
|-
| P7
| No connection
|
|-
| P8
| DGND
|
|-
| P9
| No connection
|
|-
| P10
| No connection
|
|-
| P11
| +3.3V
|
|-
| P12
| No connection
|
|-
| P13
| No connection
|
|-
| P14
| DGND
|
|-
| P15
| No connection
|
|-
| P16
| No connection
|
|-
| P17
| +1.2V
|
|-
| P18
| DGND
|
|-
| P19
| No connection
|
|-
| P20
| No connection
|
|-
| P21
| No connection
|
|-
| P22
| +3.3V
|
|-
| P23
| DGND
|
|-
| P24
| DGND
|
|-
| P25
| DGND
|
|-
| P26
| +3.3V
|
|-
| P27
| FPGA/CLK_IN
| 20 MHz clock input from crystal oscillator
|-
| P28
| No connection
|
|-
| P29
| No connection
|
|-
| P30
| No connection
|
|-
| P31
| No connection
|
|-
| P32
| No connection
|
|-
| P33
| No connection
|
|-
| P34
| No connection
|
|-
| P35
| CP2201/INT
| Ethernet controller interrupt
|-
| P36
| MASTER_RESET
| Connects to RESET jumper in upper left of board (active-low, externally pulled up)
|-
| P37
| No connection
|
|-
| P38
| +1.2V
|
|-
| P39
| No connection
|
|-
| P40
| CP2201/CS
| Chip select for ethernet controller
|-
| P41
| CP2201/WR
| Write enable for ethernet controller
|-
| P42
| DGND
|
|-
| P43
| CP2201/RD
| Read enable for ethernet controller
|-
| P44
| CP2201/ALE
| Address line enable for ethernet controller
|-
| P45
| +3.3V
|
|-
| P46
| CP2201/RESET
| Reset pin for ethernet controller
|-
| P47
| DGND
|
|-
| P48
| FPGA/INIT_B
| Used during FPGA configuration - see Xilinx documentation
|-
| P49
| CP2201/AD0
| Ethernet controller address/data bus, bit 0
|-
| P50
| CP2201/AD1
| Ethernet controller address/data bus, bit 1
|-
| P51
| FPGA/DIN
| Serial data input from EEPROM for configuration
|-
| P52
| CP2201/AD2
| Ethernet controller address/data bus, bit 2
|-
| P53
| FPGA/CCLK
| Configuration clock (signal generated by FPGA at power on to clock the configuration process) See Xilinx documentation
|-
| P54
| FPGA/DONE
| Gives configuration status - see Xilinx documentation
|-
| P55
| +3.3V
|
|-
| P56
| CP2201/AD3
| Ethernet controller address/data bus, bit 3
|-
| P57
| CP2201/AD4
| Ethernet controller address/data bus, bit 4
|-
| P58
| DGND
|
|-
| P59
| CP2201/AD5
| Ethernet controller address/data bus, bit 5
|-
| P60
| CP2201/AD6
| Ethernet controller address/date bus, bit 6
|-
| P61
| CP2201/AD7
| Ethernet controller address/date bus, bit 7
|-
| P62
| No connection
|
|-
| P63
| DGND
|
|-
| P64
| No connection
|
|-
| P65
| No connection
|
|-
| P66
| +1.2V
|
|-
| P67
| +3.3V
|
|-
| P68
| +3.3V
|
|-
| P69
| DGND
|
|-
| P70
| ID3
| Backplane location identifier jumper, pins 3 & 4 Active-low, FPGA should pull high
|-
| P71
| ID2
| Backplane location identifier jumper, pins 5 & 6 Active-low, FPGA should pull high
|-
| P72
| ID1
| Backplane location identifier jumper, pins 7 & 8 Active-low, FPGA should pull high
|-
| P73
| ID0
| Backplane location identifier jumper, pins 9 & 10 Active-low, FPGA should pull high
|-
| P74
| DGND
|
|-
| P75
| FPGA/TDO
| JTAG
|-
| P76
| FPGA/TCK
| JTAG
|-
| P77
| ID4
| Backplane location identifier jumper, pins 1 & 2 Active-low, FPGA should pull high
|-
| P78
| No connection
|
|-
| P79
| +3.3V
|
|-
| P80
| DGND
|
|-
| P81
| +1.2V
|
|-
| P82
| No connection
|
|-
| P83
| CLK_5MHZ_2
| 5 MHz clock output for DAC
|-
| P84
| No connection
|
|-
| P85
| AD5535/DIN
| DAC serial data input (FPGA out -> DAC in)
|-
| P86
| No connection
|
|-
| P87
| DGND
|
|-
| P89
| No connection
|
|-
| P90
| No connection
|
|-
| P91
| DGND
|
|-
| P92
| +3.3V
|
|-
| P93
| AD7314/CE
| Chip enable for temperature sensor
|-
| P94
| No connection
|
|-
| P95
| DGND
|
|-
| P96
| +3.3V
|
|-
| P97
| AD7928/DOUT
| '''Erroneously wired ADC SPI bus connection''' Connects to DOUT on ADC
|-
| P98
| AD5535/RESET
| Reset pin for DAC
|-
| P99
| DGND
|
|-
| P100
| FPGA/PROG_B
| Used during FPGA configuration - see Xilinx documentation
|}

== EEPROM ==
To facilitate power-on configuration of the FPGA, the control board includes a Xilinx XCF01S EEPROM. The EEPROM is located to the left of the FPGA, above the JTAG header, and has a 20 pin footprint. The EEPROM is labelled U5.

=== Power Details ===
The EEPROM uses +3.3V exclusively, which it receives from the +3.3V power plane, regulated by VR1.

=== Flashing/Burning/Writing ===
Whatever you call it, this refers to storing data in the EEPROM so that it can configure the FPGA at power-on. The EEPROM is programmed using a JTAG interface and the Xilinx Platform USB II cable. It is important to note that in digital board's JTAG chain, the EEPROM is the first device in the chain, unlike in the Xilinx documentation where it is shown as the second device. This should not affect the operation of the board, but should be reflected in the Xilinx software when writing the EEPROM via JTAG.

=== FPGA Configuration ===
The EEPROM and FPGA are hardwired to use a master serial protocol to transfer the program from the EEPROM to the FPGA. This is the protocol recommended in the Xilinx documentation because it minimizes the number of traces necessary to run between the EEPROM and FPGA. All configuration data is sent over a single trace, FPGA/DIN (pin 1 on EEPROM), controlled by the configuration clock signal (FPGA/CCLK) which is automatically generated by the FPGA at power-on. When configuration is complete, FPGA/DONE (pin 10) is pulled high by the FPGA, and the EEPROM and configuration clock are deactivated.

=== Pinout Table ===
{| cellpadding=3 border=1 |
| '''Pin #'''
| '''Net Name'''
| '''Description'''
|-
| 1
| FPGA/DIN
| Serial data line Carries data from the EEPROM to the FPGA
|-
| 2
| No connection
|
|-
| 3
| FPGA/CCLK
| Configuration clock Auto generated by FPGA at power-on, disabled at end of configuration
|-
| 4
| EEPROM/TDI
| This is the EEPROM's TDI This is the entry point for the onboard JTAG chain
|-
| 5
| FPGA/TMS
| JTAG TMS Connects to both FPGA and EEPROM
|-
| 6
| FPGA/TCK
| JTAG TCK Connects to both FPGA and EEPROM
|-
| 7
| FPGA/PROG_B
| Used during configuration See Xilinx documentation
|-
| 8
| FPGA/INIT_B
| Used during configuration - can be used to intiate reconfiguration of FPGA See Xilinx documentation
|-
| 9
| No connection
|
|-
| 10
| FPGA/DONE
| Indicates completion of FPGA configuration High when complete
|-
| 11
| DGND
|
|-
| 12-16
| No connection
|
|-
| 17
| FPGA/TDI
| This is the EEPROM's TDO/FPGA's TDI
|-
| 18-20
| +3.3V
|
|}

== JTAG Header ==
To write the FPGA's program to the EEPROM, the board employs a JTAG based programming system consistent with Xilinx's recommendations. The system is designed to operate with Xilnx's Platform USB II cable and the flying lead adapter.

===Header Location and Size===
The header consists of 14 pins, 100 mil pitch, just below the EEPROM (U5). The header is labelled P1. The pitch of the pins in the header was erroneously selected to be 100 mil, which is not compatible with Xilinx's JTAG ribbon cable. Therefore, the Xilinx flying lead adapter must be used.

===Power Details===
The JTAG interface is powered by the +3.3V power plane, not by the computer's USB port. Power is supplied through pin 2 of the JTAG header.

===Pinout Table===
Note that the header is positioned on the board rotated 180 degrees from the position in which it is shown in the Xilinx documentation. Care must be taken when connecting the flying leads to ensure they are connected to the right pins. Connecting the flying leads to the wrong side of the header will cause all of the leads to short on the digital board's ground plane. This will certainly cause undesired operation, and may or may not cause damage. Improper wiring is most likely to cause damage if one of the flying leads is connected to an odd numbered pin. '''Note from the pinout table below that no flying lead connections should ever be made to the odd numbered pins on the JTAG header.'''

{| cellpadding=3 border=1 |
| '''Pin #'''
| '''Net Name'''
| '''Description'''
|-
| 1, 3, 5, 7, 9, 11, 13 (odd pins)
| DGND
| Ground pins for signal integrity '''Never connect a flying lead to these pins''' Doing so will short to ground and may cause permanent damage if the Platform USB II cable does not have protection against this.
|-
| 2
| +3.3V
| Power source for all JTAG logic
|-
| 4
| FPGA/TMS
| JTAG TMS - connects to EEPROM and FPGA
|-
| 6
| FPGA/TCK
| JTAG TCK - connects to EEPROM and FPGA
|-
| 8
| FPGA/TDO
| JTAG boundary scan chain endpoint
|-
| 10
| EEPROM/TDI
| JTAG boundary scan chain start point
|-
| 12
| No connection
| Pin is floating
|-
| 14
| No connection
| Pin is floating
|}

===JTAG Overview===
The JTAG interface is clocked by the TCK signal. TCK is generated by the Platform USB II cable, and connects directly from the JTAG header to both the EEPROM and FPGA.

The TMS signal is directly connected to both the EEPROM and FPGA, and is the data line over which JTAG test results (in this case programming results) are sent. TMS is used by only one component at a time.

The TDI/TDO lines form a chain that connects to each JTAG component in series. On the control board, the first point in the chain is the EEPROM's TDI. Next is the EEPROM's TDO, which is the same as the FPGA's TDI. The FPGA's TDO then returns to the JTAG header and the Platform USB II cable.

== DAC ==
The control board uses the Analog Devices AD5535, 32-channel, 200V max, digital to analog converter. This chip has a modified BC-124 BGA footprint and is located above the Eurocard connector at the bottom of the board. It is labelled U3.

=== Power Details ===
The DAC is primarily powered by the +5V power island, regulated by an off-board power supply and extensively decoupled in the area of the DAC. The DAC also requires -5V, and a high voltage as discussed in [[#Power Requirements | Power Requirements]]. Both of these voltages are supplied by an off-board supply and decoupled near the DAC. In addition to these voltage levels, the DAC requires a precise +2.5V reference, created by the shunt-type voltage reference VR4.

=== Setting the Output Range ===
The output range of the DAC is set by the 2.5V reference voltage supplied by VR4. The high voltage power supply must supply at a minimum 50 times this voltage, plus 10. Thus, the high voltage power supply should be at least 135V for DAC to operate properly, even though the SiPMs are expected to need only 40V. If it is convenient to use a lower high voltage, VR4 must be replaced to provide lower reference voltage. The high voltage may then be decreased appropriately. To summarize:

* Max output voltage = VREF*50
* Minimum high voltage supply = VREF*50 + 10
* Acceptable range for VREF
** Min: 1V
** Max: 3.75V (AD5535 datasheet specifies 4V max, but this would require AVCC of 5.25V for the DAC, which is not possible in the current board design)

If relevant, R13 is a 100K resistor.

=== Thermal Diode ===
The DAC has a built in thermal diode. The diode drop from anode to cathode is typically 0.65V at 25°C. It changes at a rate of -2.20mV/°C. The anode of this diode is connected to the +5V power island, and the cathode is connected to a 270K resistor to ground. The voltage between the cathode and the resistor is connected to VIN1 (pin 15) on the ADC.

=== Pinout Table ===
See documentation from Analog Devices.

=== Channel Mapping ===
Due to the layout of the balls on the footprint of the DAC, the DAC's internal channel numbers (which must be referenced by the FPGA) have no correlation to the channel numbers on the amplifier board. This table summarizes the mapping between various pins that belong to each channel.

{| cellpadding=3 border=1 |
| '''DAC Channel #'''
| '''DAC Pin #'''
| '''Digital Board Eurocard Pin #'''
| '''Amplifier Board Eurocard Pin #'''
| '''Physical Channel #'''
|-
| 0
| B1
| B3
|
|
|-
| 1
| A2
| C4
|
|
|-
| 2
| D1
| B2
|
|
|-
| 3
| C2
| C3
|
|
|-
| 4
| B3
| B4
|
|
|-
| 5
| E2
| C2
|
|
|-
| 6
| F3
| B1
|
|
|-
| 7
| A4
| B5
|
|
|-
| 8
| E4
| C5
|
|
|-
| 9
| B5
| C6
|
|
|-
| 10
| F5
| C1
|
|
|-
| 11
| A6
| C7
|
|
|-
| 12
| E6
| B6
|
|
|-
| 13
| B7
| B7
|
|
|-
| 14
| F7
| C10
|
|
|-
| 15
| E8
| C8
|
|
|-
| 16
| A8
| B8
|
|
|-
| 17
| B9
| C9
|
|
|-
| 18
| F9
| C16
|
|
|-
| 19
| E10
| B11
|
|
|-
| 20
| A10
| B9
|
|
|-
| 21
| B11
| B10
|
|
|-
| 22
| C12
| B12
|
|
|-
| 23
| D13
| B13
|
|
|-
| 24
| E12
| B14
|
|
|-
| 25
| A12
| C11
|
|
|-
| 26
| B13
| C12
|
|
|-
| 27
| H13
| B16
|
|
|-
| 28
| G14
| B15
|
|
|-
| 29
| C14
| C13
|
|
|-
| 30
| F13
| C15
|
|
|-
| 31
| E14
| C14
|
| DACHEALTH See [[#Channel Descriptions | ADC Channel Descriptions]].
|}

==ADC==
The board includes an Analog Devices AD7928 analog to digital converter. The ADC is located just to the right and slightly below the FPGA. It is labelled U4.

===Power Details===
The ADC is powered by the +5V power island, which is regulated by an off-board power supply and decoupled near the ADC. It also requires a precise (±1%) 2.5V reference to which it compares voltages when converting from analog to digital. Since the +5V power source is not used for comparison, it is flexible and may vary by ±0.25V without affecting ADC precision.

===Setting the Measuring Range===
The measuring range is set programmatically by the FPGA over the SPI bus. The way the ADC is connected on the digital board requires that its measuring range be set to 5V, so the RANGE bit should be set to 1 by the FPGA (see Analog Devices documentation).

===Data Interfacing===
The ADC uses an SPI bus to communicate with the FPGA. This bus is shared with the temperature sensor. SPI related pins include SCLK, CS, DIN, and DOUT. See the Pinout Table below.

===Channel Descriptions===
This table shows what signals are monitored by the ADC.

{| cellpadding=3 border=1 |
| '''ADC Channel #'''
| '''ADC Pin #'''
| '''Net Name'''
| '''Description'''
|-
| VIN0
| 16
| AD7928/VHEALTH
| This net helps to monitor to overall health of power on the board, but is specifically intended to monitor -5V. It's voltage is the output of a resistor divider between the +5 and -5V power supplies, with resistor values of 33.2K, and 100K. Assuming +5V and -5V are both correct, the output of the divider will be +2.51V. A reading of other than 2.51V indicates a problem with one of the power supplies. Problems with the +5V power supply can be ruled out by reading VIN3. Based on the reading from VIN3, the voltage of the -5V supply can be calculated.
|-
| VIN1
| 15
| AD5535/CATHODE
| This is the thermal diode output from the DAC. Should read 4.35V (typical) at 25°C. Drops 2.20mV/°C.
|-
| VIN2
| 14
| +3.3V
| This is the +3.3V power plane. A reading of other than +3.3V indicates a problem with VR1.
|-
| VIN3
| 13
| +5V
| This is the +5V power island. A reading of other than +5V indicates a problem with the +5V power supply.
|-
| VIN4
| 12
| ADC_EXT1
| This trace routes to the backplane via Eurocard pin A7. It is intended to measure the output of thermistor on the amplifier board.
|-
| VIN5
| 11
| +1.2V
| This is the +1.2V power island. This island powers the internal logic of the FPGA. A reading of other than 1.2V indicates a problem with VR3.
|-
| VIN6
| 10
| ADC_EXT2
| This trace routes to the backplane via Eurocard pin A8. It is intended to measure one of the transistor base voltages on the amplifier board.
|-
| VIN7
| 9
| DACHEALTH
| This channel monitors the output of a resistor divider connected to channel 31 of the DAC. The divider consists of three resistors of 200K, 200K, and 10.2K (in order). The ADC reads out the voltage level between the second 200K and then 10.2K resistor. These resistors were selected so that at 200V, the readout voltage will be 4.973V. Since the divider should be linear, the expected voltage at 20V is 0.4973V. Three resistors were used rather than two to avoid exceeding the resistors' power ratings when the DAC is set to its maximum voltage. Note that since this divider will consume up to 484uA of current at 200V, this DAC channel should not be used for anything that might require more than ~200uA of current (the DAC can source 700uA max). The channel is routed to the backplane nonetheless.
|}

===Pinout Table===
{| cellpadding=3 border=1 |
| '''Pin #'''
| '''Net Name'''
| '''Description'''
|-
| 1
| CLK_5MHZ
| SPI clock (SCLK), from FPGA Shared with temperature sensor
|-
| 2
| DIN
| SPI data in, from FPGA Shared with temperature sensor ''Currently wired wrong''
|-
| 3
| CS
| SPI chip select
|-
| 4
| AGND
|
|-
| 5
| +5V
| Power pin
|-
| 6
| +5V
| Power pin
|-
| 7
| AD7928/REF_IN
| +2.5V reference, set by VR2
|-
| 8
| AGND
|
|-
| 9-16
| VIN[7:0]
| See [[#Channel Descriptions | ADC Channel Descriptions]]
|-
| 17
| AGND
|
|-
| 18
| DOUT
| SPI data out ''Currently wired incorrectly''
|-
| 19
| +3.3V
| VDRIVE, powers the SPI logic
|-
| 20
| AGND
|
|}

== Ethernet Controller ==
The board uses a Silicon Laboratories CP2201, 28-pin, ethernet controller. The CP2201 is located just above the FPGA, and is labelled U2.

=== Power Details ===
The CP2201 uses only +3.3V, which is supplied by the +3.3V power plane and regulated by VR1. Appropriate decoupling capacitors can be found near the CP2201.

=== Ethernet Jack ===
To the right of the CP2201 is a Pulse J0011D21NL ethernet jack, labelled J1. This jack has a built-in 1:1 inductive coupling. For best results, connect this jack to a nearby ethernet switch. The jack may also be connected directly to a computer using a crossover cable. Though auto-crossover is not supported by the CP2201, if the computer's NIC supports it, a crossover cable is not necessary to connect directly to a computer.

==== Ethernet Jack Pins ====
These are visible only on the back side of the board. Pin 1 is indicated by a square pad. Pin 8 is the farthest pin from pin 1. Pins are numbered such that the 4 pins closer to the plastic thru-hole connectors are odd (1, 3, 5, 7), and the four pins closer to the CP2201 are are even (2, 4, 6, 8).

* Pin 1: TX+
* Pin 2: AC coupled to DGND
* Pin 3: TX-
* Pin 4: RX+
* Pin 5: AC coupled to DGND
* Pin 6: RX-
* Pin 7: No connection
* Pin 8: DGND (direct)

The two large thru-hole pins (not numbered) connect to the metal shielding on the outside of the jack. These are directly connected to DGND to shield against electrical noise inside the jack.

The two plastic thru-hole pins are not conductive and have no electrical connection. They are present only for structural purposes, presumably to prevent stress of the solder points when an ethernet wire is inserted or removed from the jack.

=== Crystal Oscillator ===
The CP2201 is responsible for driving the 20MHz crystal oscillator. This oscillator clocks both the CP2201 and the FPGA. The crystal oscillator can be found above the right corner of the FPGA. It can be identified by its four surface mount pads and roughly .3" length. It is labelled Y1, though this label is not visible after the oscillator is soldered on. The CP2201 uses an inverting driver to excite the crystal. The output of the crystal is then sent to the CP2201 and the FPGA.

=== Bus Format and Multiplexing ===
The 28-pin CP2201 used on the board only supports multiplexed operation. This means that both address and data information are passed over the same set of 8 traces. Hence, these traces are referred to as the address/data (AD) bus. A separate address line enable (ALE) trace prevents collisions from occuring on these traces. The communication protocol used is the Intel format. See the CP2201's datasheet for more information about this.

=== Pinout Table ===
{| cellpadding=3 border=1 |
| '''Pin #'''
| '''Net Name'''
| '''Description'''
|-
| 1
| CP2201/LA
| Link/activity indicator Routed to backplane but not implemented See CP2201 data sheet for information on how to connect to an LED
|-
| 2
| DGND
| By the data sheet, this pin should be AGND We deliberately set it to DGND to avoid noise on AGND plane
|-
| 3
| +3.3V
| AV+ power pin
|-
| 4
| CP2201/RX-
| Connects to RX- on ethernet jack
|-
| 5
| CP2201/RX+
| Connects to RX+ on ethernet jack
|-
| 6
| CP2201/TX+
| Connects to TX+ on ethernet jack
|-
| 7
| CP2201/TX-
| Connects to TX- on ethernet jack
|-
| 8
| +3.3V
| "VDD" power pin
|-
| 9
| DGND
| "DGND1" per the data sheet
|-
| 10
| CP2201/RESET
| "RST" per the data sheet Connects to FPGA - should be programmatically triggered upon reset of FPGA by RESET jumper
|-
| 11-18
| CP2201/AD[0:7]
| Bits 0-7 of the address/data bus Connect to FPGA
|-
| 19
| +3.3V
| "VDD" power pin
|-
| 20
| DGND
| "DGND2" per the data sheet
|-
| 21
| CP2201/ALE
| Address line enable Connects to FPGA See CP2201 documentation
|-
| 22
| CP2201/RD
| Read strobe for AD bus Connects to FPGA See CP2201 documentation
|-
| 23
| CP2201/WR
| Write strobe for AD bus Connects to FPGA See CP2201 documentation
|-
| 24
| CP2201/CS
| Chip select Connects to FPGA
|-
| 25
| CP2201/INT
| Interrupt request Connects to FPGA
|-
| 26
| DGND
| "MOTEN" (Motorola enable) per the datasheet Tied low to disable Motorola bus format (enable Intel format)
|-
| 27
| CP2201/XTAL2
| Crystal oscillator driver The CP2201 inverts the 20MHz clock signal and feeds it back to the crystal oscillator to encourage larger oscillations
|-
| 28
| FPGA/CLK_IN
| "XTAL1" per the data sheet This is the 20MHz clock input Also connects to the FPGA's clock input
|-
| 29*
| DGND
| This is not a pin but rather the base of the CP2201 package. It is connected to the DGND plane for thermal relief
|}

== Eurocard Connector ==
At the bottom of the control board is the Eurocard connector. The Eurocard connector connects the board to the backplane and also connects the board to its power supplies. The Eurocard has 48 pins arranged in three rows of 16 pins each. Rows B and C are exclusively used to pass SiPM bias voltages to the backplane as described in [[#Channel Mapping | DAC Channel Mapping]]. Here is a table describing the purpose of pins in row A:

=== Row A Pinout Table ===
Note that when viewing the front side of the board with the Eurocard at the bottom, these pins go from right to left. If you look closely at the pins, you will see that pin A1 has a square pad, unlike the round pads of the others.

{| cellpadding=3 border=1 |
| '''Pin #'''
| '''Net Name'''
| '''Description'''
|-
| A1
| CP2201/LA
| Ethernet link/activity indicator routed to backplane
|-
| A2
| High voltage input (+210V max)
| High voltage input for DAC. See [[#DAC | DAC]] for information about what voltage to input here.
|-
| A3
| -5V
| For DAC
|-
| A4
| +5V
| Powers most things on the board
|-
| A5
| AGND
|
|-
| A6
| DGND
|
|-
| A7
| ADC_EXT1
| Connects to ADC to monitor voltages on amplifier board See [[#ADC | ADC]]
|-
| A8
| ADC_EXT2
| Connects to ADC to monitor voltages on amplifier board See [[#ADC | ADC]]
|-
| A9
| No connection
|
|-
| A10
| No connection
|
|-
| A11
| No conneciton
|
|-
| A12
| ID4
| Location identifier bit 4 Used to identify which backplane board is connected to See [[#FPGA | FPGA]]
|-
| A13
| ID3
| Location identifier bit 3 Used to identify which backplane board is connected to See [[#FPGA | FPGA]]
|-
| A14
| ID2
| Location identifier bit 2 Used to identify which backplane board is connected to See [[#FPGA | FPGA]]
|-
| A15
| ID1
| Location identifier bit 1 Used to identify which backplane board is connected to See [[#FPGA | FPGA]]
|-
| A16
| ID0
| Location identifier bit 0 Used to identify which backplane board is connected to See [[#FPGA | FPGA]]
|}

Digital control board documentation

2009-06-16T19:21:17Z

Underwood: /* Ethernet Jack */ added pin info

This documentation covers the most important things to know while testing the digital control board, including component pinouts, nets, and other information.

== Power Requirements ==
=== Required Voltages ===
All components on the digital board '''except the DAC''' can be tested using only a +5V source. The DAC requires +5V, -5V, and a high voltage corresponding to 10V higher than the maximum desired DAC output voltage (see [[#Setting the Output Range | Setting the Output Range]]). Digital and analog grounds must be connected as well before any testing takes place.

=== Power Pins ===
Power shall be connected to the board as follows:
{| cellpadding=3 border=1 |
| '''Voltage'''
| '''Eurocard Pin'''
|-
| DGND
| A6
|-
| AGND
| A5
|-
| +5V
| A4
|-
| -5V
| A3
|-
| High voltage (DAC max out +10)
| A2
|}

=== Power Supply Sequencing ===
The control board is designed such that voltages may be supplied in any order so long as AGND and DGND are connected properly. However, for initial testing, the preferred order for powering up the board is as follows:

# Ensure AGND/DGND are connected/grounded
# +5V
# -5V
# High voltage

== FPGA ==
The control board uses a Xilinx XC3S50A VQ100 FPGA. It has a 100 pin footprint and is located in the center of the control board.

=== Power Details ===
The FPGA is powered by the 3.3V power plane, which is regulated by VR1. The FPGA also obtains 1.2V for its internal logic from a 1.2V power island, regulated by VR3.

=== Logic Standard ===
The Xilinx XC3S50A supports several different digital logic standards. The control board is hard wired such that the FPGA will use a '''3.3V CMOS''' logic standard.

=== Pinout Table ===
{| cellpadding=3 border=1 |
| '''Pin #'''
| '''Net Name'''
| '''Description'''
|-
| P1
| FPGA/TMS
| JTAG
|-
| P2
| FPGA/TDI
| JTAG
|-
| P3
| AD7928/CS
| SPI chip select for ADC
|-
| P4
| SPI
| '''Erroneously wired SPI bus trace''' Connects to SDO on temp. sensor and DIN on ADC
|-
| P5
| CLK_5MHZ
| 5 MHz clock output for SPI bus (ADC and temp. sensor)
|-
| P6
| No connection
|
|-
| P7
| No connection
|
|-
| P8
| DGND
|
|-
| P9
| No connection
|
|-
| P10
| No connection
|
|-
| P11
| +3.3V
|
|-
| P12
| No connection
|
|-
| P13
| No connection
|
|-
| P14
| DGND
|
|-
| P15
| No connection
|
|-
| P16
| No connection
|
|-
| P17
| +1.2V
|
|-
| P18
| DGND
|
|-
| P19
| No connection
|
|-
| P20
| No connection
|
|-
| P21
| No connection
|
|-
| P22
| +3.3V
|
|-
| P23
| DGND
|
|-
| P24
| DGND
|
|-
| P25
| DGND
|
|-
| P26
| +3.3V
|
|-
| P27
| FPGA/CLK_IN
| 20 MHz clock input from crystal oscillator
|-
| P28
| No connection
|
|-
| P29
| No connection
|
|-
| P30
| No connection
|
|-
| P31
| No connection
|
|-
| P32
| No connection
|
|-
| P33
| No connection
|
|-
| P34
| No connection
|
|-
| P35
| CP2201/INT
| Ethernet controller interrupt
|-
| P36
| MASTER_RESET
| Connects to RESET jumper in upper left of board (active-low, externally pulled up)
|-
| P37
| No connection
|
|-
| P38
| +1.2V
|
|-
| P39
| No connection
|
|-
| P40
| CP2201/CS
| Chip select for ethernet controller
|-
| P41
| CP2201/WR
| Write enable for ethernet controller
|-
| P42
| DGND
|
|-
| P43
| CP2201/RD
| Read enable for ethernet controller
|-
| P44
| CP2201/ALE
| Address line enable for ethernet controller
|-
| P45
| +3.3V
|
|-
| P46
| CP2201/RESET
| Reset pin for ethernet controller
|-
| P47
| DGND
|
|-
| P48
| FPGA/INIT_B
| Used during FPGA configuration - see Xilinx documentation
|-
| P49
| CP2201/AD0
| Ethernet controller address/data bus, bit 0
|-
| P50
| CP2201/AD1
| Ethernet controller address/data bus, bit 1
|-
| P51
| FPGA/DIN
| Serial data input from EEPROM for configuration
|-
| P52
| CP2201/AD2
| Ethernet controller address/data bus, bit 2
|-
| P53
| FPGA/CCLK
| Configuration clock (signal generated by FPGA at power on to clock the configuration process) See Xilinx documentation
|-
| P54
| FPGA/DONE
| Gives configuration status - see Xilinx documentation
|-
| P55
| +3.3V
|
|-
| P56
| CP2201/AD3
| Ethernet controller address/data bus, bit 3
|-
| P57
| CP2201/AD4
| Ethernet controller address/data bus, bit 4
|-
| P58
| DGND
|
|-
| P59
| CP2201/AD5
| Ethernet controller address/data bus, bit 5
|-
| P60
| CP2201/AD6
| Ethernet controller address/date bus, bit 6
|-
| P61
| CP2201/AD7
| Ethernet controller address/date bus, bit 7
|-
| P62
| No connection
|
|-
| P63
| DGND
|
|-
| P64
| No connection
|
|-
| P65
| No connection
|
|-
| P66
| +1.2V
|
|-
| P67
| +3.3V
|
|-
| P68
| +3.3V
|
|-
| P69
| DGND
|
|-
| P70
| ID3
| Backplane location identifier jumper, pins 3 & 4 Active-low, FPGA should pull high
|-
| P71
| ID2
| Backplane location identifier jumper, pins 5 & 6 Active-low, FPGA should pull high
|-
| P72
| ID1
| Backplane location identifier jumper, pins 7 & 8 Active-low, FPGA should pull high
|-
| P73
| ID0
| Backplane location identifier jumper, pins 9 & 10 Active-low, FPGA should pull high
|-
| P74
| DGND
|
|-
| P75
| FPGA/TDO
| JTAG
|-
| P76
| FPGA/TCK
| JTAG
|-
| P77
| ID4
| Backplane location identifier jumper, pins 1 & 2 Active-low, FPGA should pull high
|-
| P78
| No connection
|
|-
| P79
| +3.3V
|
|-
| P80
| DGND
|
|-
| P81
| +1.2V
|
|-
| P82
| No connection
|
|-
| P83
| CLK_5MHZ_2
| 5 MHz clock output for DAC
|-
| P84
| No connection
|
|-
| P85
| AD5535/DIN
| DAC serial data input (FPGA out -> DAC in)
|-
| P86
| No connection
|
|-
| P87
| DGND
|
|-
| P89
| No connection
|
|-
| P90
| No connection
|
|-
| P91
| DGND
|
|-
| P92
| +3.3V
|
|-
| P93
| AD7314/CE
| Chip enable for temperature sensor
|-
| P94
| No connection
|
|-
| P95
| DGND
|
|-
| P96
| +3.3V
|
|-
| P97
| AD7928/DOUT
| '''Erroneously wired ADC SPI bus connection''' Connects to DOUT on ADC
|-
| P98
| AD5535/RESET
| Reset pin for DAC
|-
| P99
| DGND
|
|-
| P100
| FPGA/PROG_B
| Used during FPGA configuration - see Xilinx documentation
|}

== EEPROM ==
To facilitate power-on configuration of the FPGA, the control board includes a Xilinx XCF01S EEPROM. The EEPROM is located to the left of the FPGA, above the JTAG header, and has a 20 pin footprint. The EEPROM is labelled U5.

=== Power Details ===
The EEPROM uses +3.3V exclusively, which it receives from the +3.3V power plane, regulated by VR1.

=== Flashing/Burning/Writing ===
Whatever you call it, this refers to storing data in the EEPROM so that it can configure the FPGA at power-on. The EEPROM is programmed using a JTAG interface and the Xilinx Platform USB II cable. It is important to note that in digital board's JTAG chain, the EEPROM is the first device in the chain, unlike in the Xilinx documentation where it is shown as the second device. This should not affect the operation of the board, but should be reflected in the Xilinx software when writing the EEPROM via JTAG.

=== FPGA Configuration ===
The EEPROM and FPGA are hardwired to use a master serial protocol to transfer the program from the EEPROM to the FPGA. This is the protocol recommended in the Xilinx documentation because it minimizes the number of traces necessary to run between the EEPROM and FPGA. All configuration data is sent over a single trace, FPGA/DIN (pin 1 on EEPROM), controlled by the configuration clock signal (FPGA/CCLK) which is automatically generated by the FPGA at power-on. When configuration is complete, FPGA/DONE (pin 10) is pulled high by the FPGA, and the EEPROM and configuration clock are deactivated.

=== Pinout Table ===
{| cellpadding=3 border=1 |
| '''Pin #'''
| '''Net Name'''
| '''Description'''
|-
| 1
| FPGA/DIN
| Serial data line Carries data from the EEPROM to the FPGA
|-
| 2
| No connection
|
|-
| 3
| FPGA/CCLK
| Configuration clock Auto generated by FPGA at power-on, disabled at end of configuration
|-
| 4
| EEPROM/TDI
| This is the EEPROM's TDI This is the entry point for the onboard JTAG chain
|-
| 5
| FPGA/TMS
| JTAG TMS Connects to both FPGA and EEPROM
|-
| 6
| FPGA/TCK
| JTAG TCK Connects to both FPGA and EEPROM
|-
| 7
| FPGA/PROG_B
| Used during configuration See Xilinx documentation
|-
| 8
| FPGA/INIT_B
| Used during configuration - can be used to intiate reconfiguration of FPGA See Xilinx documentation
|-
| 9
| No connection
|
|-
| 10
| FPGA/DONE
| Indicates completion of FPGA configuration High when complete
|-
| 11
| DGND
|
|-
| 12-16
| No connection
|
|-
| 17
| FPGA/TDI
| This is the EEPROM's TDO/FPGA's TDI
|-
| 18-20
| +3.3V
|
|}

== JTAG Header ==
To write the FPGA's program to the EEPROM, the board employs a JTAG based programming system consistent with Xilinx's recommendations. The system is designed to operate with Xilnx's Platform USB II cable and the flying lead adapter.

===Header Location and Size===
The header consists of 14 pins, 100 mil pitch, just below the EEPROM (U5). The header is labelled P1. The pitch of the pins in the header was erroneously selected to be 100 mil, which is not compatible with Xilinx's JTAG ribbon cable. Therefore, the Xilinx flying lead adapter must be used.

===Power Details===
The JTAG interface is powered by the +3.3V power plane, not by the computer's USB port. Power is supplied through pin 2 of the JTAG header.

===Pinout Table===
Note that the header is positioned on the board rotated 180 degrees from the position in which it is shown in the Xilinx documentation. Care must be taken when connecting the flying leads to ensure they are connected to the right pins. Connecting the flying leads to the wrong side of the header will cause all of the leads to short on the digital board's ground plane. This will certainly cause undesired operation, and may or may not cause damage. Improper wiring is most likely to cause damage if one of the flying leads is connected to an odd numbered pin. '''Note from the pinout table below that no flying lead connections should ever be made to the odd numbered pins on the JTAG header.'''

{| cellpadding=3 border=1 |
| '''Pin #'''
| '''Net Name'''
| '''Description'''
|-
| 1, 3, 5, 7, 9, 11, 13 (odd pins)
| DGND
| Ground pins for signal integrity '''Never connect a flying lead to these pins''' Doing so will short to ground and may cause permanent damage if the Platform USB II cable does not have protection against this.
|-
| 2
| +3.3V
| Power source for all JTAG logic
|-
| 4
| FPGA/TMS
| JTAG TMS - connects to EEPROM and FPGA
|-
| 6
| FPGA/TCK
| JTAG TCK - connects to EEPROM and FPGA
|-
| 8
| FPGA/TDO
| JTAG boundary scan chain endpoint
|-
| 10
| EEPROM/TDI
| JTAG boundary scan chain start point
|-
| 12
| No connection
| Pin is floating
|-
| 14
| No connection
| Pin is floating
|}

===JTAG Overview===
The JTAG interface is clocked by the TCK signal. TCK is generated by the Platform USB II cable, and connects directly from the JTAG header to both the EEPROM and FPGA.

The TMS signal is directly connected to both the EEPROM and FPGA, and is the data line over which JTAG test results (in this case programming results) are sent. TMS is used by only one component at a time.

The TDI/TDO lines form a chain that connects to each JTAG component in series. On the control board, the first point in the chain is the EEPROM's TDI. Next is the EEPROM's TDO, which is the same as the FPGA's TDI. The FPGA's TDO then returns to the JTAG header and the Platform USB II cable.

== DAC ==
The control board uses the Analog Devices AD5535, 32-channel, 200V max, digital to analog converter. This chip has a modified BC-124 BGA footprint and is located above the Eurocard connector at the bottom of the board. It is labelled U3.

=== Power Details ===
The DAC is primarily powered by the +5V power island, regulated by an off-board power supply and extensively decoupled in the area of the DAC. The DAC also requires -5V, and a high voltage as discussed in [[#Power Requirements | Power Requirements]]. Both of these voltages are supplied by an off-board supply and decoupled near the DAC. In addition to these voltage levels, the DAC requires a precise +2.5V reference, created by the shunt-type voltage reference VR4.

=== Setting the Output Range ===
The output range of the DAC is set by the 2.5V reference voltage supplied by VR4. The high voltage power supply must supply at a minimum 50 times this voltage, plus 10. Thus, the high voltage power supply should be at least 135V for DAC to operate properly, even though the SiPMs are expected to need only 40V. If it is convenient to use a lower high voltage, VR4 must be replaced to provide lower reference voltage. The high voltage may then be decreased appropriately. To summarize:

* Max output voltage = VREF*50
* Minimum high voltage supply = VREF*50 + 10
* Acceptable range for VREF
** Min: 1V
** Max: 3.75V (AD5535 datasheet specifies 4V max, but this would require AVCC of 5.25V for the DAC, which is not possible in the current board design)

If relevant, R13 is a 100K resistor.

=== Thermal Diode ===
The DAC has a built in thermal diode. The diode drop from anode to cathode is typically 0.65V at 25°C. It changes at a rate of -2.20mV/°C. The anode of this diode is connected to the +5V power island, and the cathode is connected to a 270K resistor to ground. The voltage between the cathode and the resistor is connected to VIN1 (pin 15) on the ADC.

=== Pinout Table ===
See documentation from Analog Devices.

=== Channel Mapping ===
Due to the layout of the balls on the footprint of the DAC, the DAC's internal channel numbers (which must be referenced by the FPGA) have no correlation to the channel numbers on the amplifier board. This table summarizes the mapping between various pins that belong to each channel.

{| cellpadding=3 border=1 |
| '''DAC Channel #'''
| '''DAC Pin #'''
| '''Digital Board Eurocard Pin #'''
| '''Amplifier Board Eurocard Pin #'''
| '''Physical Channel #'''
|-
| 0
| B1
| B3
|
|
|-
| 1
| A2
| C4
|
|
|-
| 2
| D1
| B2
|
|
|-
| 3
| C2
| C3
|
|
|-
| 4
| B3
| B4
|
|
|-
| 5
| E2
| C2
|
|
|-
| 6
| F3
| B1
|
|
|-
| 7
| A4
| B5
|
|
|-
| 8
| E4
| C5
|
|
|-
| 9
| B5
| C6
|
|
|-
| 10
| F5
| C1
|
|
|-
| 11
| A6
| C7
|
|
|-
| 12
| E6
| B6
|
|
|-
| 13
| B7
| B7
|
|
|-
| 14
| F7
| C10
|
|
|-
| 15
| E8
| C8
|
|
|-
| 16
| A8
| B8
|
|
|-
| 17
| B9
| C9
|
|
|-
| 18
| F9
| C16
|
|
|-
| 19
| E10
| B11
|
|
|-
| 20
| A10
| B9
|
|
|-
| 21
| B11
| B10
|
|
|-
| 22
| C12
| B12
|
|
|-
| 23
| D13
| B13
|
|
|-
| 24
| E12
| B14
|
|
|-
| 25
| A12
| C11
|
|
|-
| 26
| B13
| C12
|
|
|-
| 27
| H13
| B16
|
|
|-
| 28
| G14
| B15
|
|
|-
| 29
| C14
| C13
|
|
|-
| 30
| F13
| C15
|
|
|-
| 31
| E14
| C14
|
| DACHEALTH See [[#Channel Descriptions | ADC Channel Descriptions]].
|}

==ADC==
The board includes an Analog Devices AD7928 analog to digital converter. The ADC is located just to the right and slightly below the FPGA. It is labelled U4.

===Power Details===
The ADC is powered by the +5V power island, which is regulated by an off-board power supply and decoupled near the ADC. It also requires a precise (±1%) 2.5V reference to which it compares voltages when converting from analog to digital. Since the +5V power source is not used for comparison, it is flexible and may vary by ±0.25V without affecting ADC precision.

===Setting the Measuring Range===
The measuring range is set programmatically by the FPGA over the SPI bus. The way the ADC is connected on the digital board requires that its measuring range be set to 5V, so the RANGE bit should be set to 1 by the FPGA (see Analog Devices documentation).

===Data Interfacing===
The ADC uses an SPI bus to communicate with the FPGA. This bus is shared with the temperature sensor. SPI related pins include SCLK, CS, DIN, and DOUT. See the Pinout Table below.

===Channel Descriptions===
This table shows what signals are monitored by the ADC.

{| cellpadding=3 border=1 |
| '''ADC Channel #'''
| '''ADC Pin #'''
| '''Net Name'''
| '''Description'''
|-
| VIN0
| 16
| AD7928/VHEALTH
| This net helps to monitor to overall health of power on the board, but is specifically intended to monitor -5V. It's voltage is the output of a resistor divider between the +5 and -5V power supplies, with resistor values of 33.2K, and 100K. Assuming +5V and -5V are both correct, the output of the divider will be +2.51V. A reading of other than 2.51V indicates a problem with one of the power supplies. Problems with the +5V power supply can be ruled out by reading VIN3. Based on the reading from VIN3, the voltage of the -5V supply can be calculated.
|-
| VIN1
| 15
| AD5535/CATHODE
| This is the thermal diode output from the DAC. Should read 4.35V (typical) at 25°C. Drops 2.20mV/°C.
|-
| VIN2
| 14
| +3.3V
| This is the +3.3V power plane. A reading of other than +3.3V indicates a problem with VR1.
|-
| VIN3
| 13
| +5V
| This is the +5V power island. A reading of other than +5V indicates a problem with the +5V power supply.
|-
| VIN4
| 12
| ADC_EXT1
| This trace routes to the backplane via Eurocard pin A7. It is intended to measure the output of thermistor on the amplifier board.
|-
| VIN5
| 11
| +1.2V
| This is the +1.2V power island. This island powers the internal logic of the FPGA. A reading of other than 1.2V indicates a problem with VR3.
|-
| VIN6
| 10
| ADC_EXT2
| This trace routes to the backplane via Eurocard pin A8. It is intended to measure one of the transistor base voltages on the amplifier board.
|-
| VIN7
| 9
| DACHEALTH
| This channel monitors the output of a resistor divider connected to channel 31 of the DAC. The divider consists of three resistors of 200K, 200K, and 10.2K (in order). The ADC reads out the voltage level between the second 200K and then 10.2K resistor. These resistors were selected so that at 200V, the readout voltage will be 4.973V. Since the divider should be linear, the expected voltage at 20V is 0.4973V. Three resistors were used rather than two to avoid exceeding the resistors' power ratings when the DAC is set to its maximum voltage. Note that since this divider will consume up to 484uA of current at 200V, this DAC channel should not be used for anything that might require more than ~200uA of current (the DAC can source 700uA max). The channel is routed to the backplane nonetheless.
|}

===Pinout Table===
{| cellpadding=3 border=1 |
| '''Pin #'''
| '''Net Name'''
| '''Description'''
|-
| 1
| CLK_5MHZ
| SPI clock (SCLK), from FPGA Shared with temperature sensor
|-
| 2
| DIN
| SPI data in, from FPGA Shared with temperature sensor ''Currently wired wrong''
|-
| 3
| CS
| SPI chip select
|-
| 4
| AGND
|
|-
| 5
| +5V
| Power pin
|-
| 6
| +5V
| Power pin
|-
| 7
| AD7928/REF_IN
| +2.5V reference, set by VR2
|-
| 8
| AGND
|
|-
| 9-16
| VIN[7:0]
| See [[#Channel Descriptions | ADC Channel Descriptions]]
|-
| 17
| AGND
|
|-
| 18
| DOUT
| SPI data out ''Currently wired incorrectly''
|-
| 19
| +3.3V
| VDRIVE, powers the SPI logic
|-
| 20
| AGND
|
|}

== Ethernet Controller ==
The board uses a Silicon Laboratories CP2201, 28-pin, ethernet controller. The CP2201 is located just above the FPGA, and is labelled U2.

=== Power Details ===
The CP2201 uses only +3.3V, which is supplied by the +3.3V power plane and regulated by VR1. Appropriate decoupling capacitors can be found near the CP2201.

=== Ethernet Jack ===
To the right of the CP2201 is a Pulse J0011D21NL ethernet jack, labelled J1. This jack has a built-in 1:1 inductive coupling. For best results, connect this jack to a nearby ethernet switch. The jack may also be connected directly to a computer using a crossover cable. Though auto-crossover is not supported by the CP2201, if the computer's NIC supports it, a crossover cable is not necessary to connect directly to a computer.

==== Ethernet Jack Pins ====
These are visible only on the back side of the board. Pin 1 is indicated by a square pad. Pin 8 is the farthest pin from pin 1. Pins numbered such that the 4 pins closer to the plastic thru-hole connectors are odd (1, 3, 5, 7), and the four pins closer to the CP2201 are are even.

* Pin 1: TX+
* Pin 2: AC coupled to DGND
* Pin 3: TX-
* Pin 4: RX+
* Pin 5: AC coupled to DGND
* Pin 6: RX-
* Pin 7: No connection
* Pin 8: DGND (direct)

The two large thru-hole pins (not numbered) connect to the metal shielding on the outside of the jack. These are directly connected to DGND to shield against electrical noise inside the jack.

The two plastic thru-hole pins are not conductive and have no electrical connection. They are present only for structural purposes, presumably to prevent stress of the solder points when an ethernet wire is inserted or removed from the jack.

=== Crystal Oscillator ===
The CP2201 is responsible for driving the 20MHz crystal oscillator. This oscillator clocks both the CP2201 and the FPGA. The crystal oscillator can be found above the right corner of the FPGA. It can be identified by its four surface mount pads and roughly .3" length. It is labelled Y1, though this label is not visible after the oscillator is soldered on. The CP2201 uses an inverting driver to excite the crystal. The output of the crystal is then sent to the CP2201 and the FPGA.

=== Bus Format and Multiplexing ===
The 28-pin CP2201 used on the board only supports multiplexed operation. This means that both address and data information are passed over the same set of 8 traces. Hence, these traces are referred to as the address/data (AD) bus. A separate address line enable (ALE) trace prevents collisions from occuring on these traces. The communication protocol used is the Intel format. See the CP2201's datasheet for more information about this.

=== Pinout Table ===
{| cellpadding=3 border=1 |
| '''Pin #'''
| '''Net Name'''
| '''Description'''
|-
| 1
| CP2201/LA
| Link/activity indicator Routed to backplane but not implemented See CP2201 data sheet for information on how to connect to an LED
|-
| 2
| DGND
| By the data sheet, this pin should be AGND We deliberately set it to DGND to avoid noise on AGND plane
|-
| 3
| +3.3V
| AV+ power pin
|-
| 4
| CP2201/RX-
| Connects to RX- on ethernet jack
|-
| 5
| CP2201/RX+
| Connects to RX+ on ethernet jack
|-
| 6
| CP2201/TX+
| Connects to TX+ on ethernet jack
|-
| 7
| CP2201/TX-
| Connects to TX- on ethernet jack
|-
| 8
| +3.3V
| "VDD" power pin
|-
| 9
| DGND
| "DGND1" per the data sheet
|-
| 10
| CP2201/RESET
| "RST" per the data sheet Connects to FPGA - should be programmatically triggered upon reset of FPGA by RESET jumper
|-
| 11-18
| CP2201/AD[0:7]
| Bits 0-7 of the address/data bus Connect to FPGA
|-
| 19
| +3.3V
| "VDD" power pin
|-
| 20
| DGND
| "DGND2" per the data sheet
|-
| 21
| CP2201/ALE
| Address line enable Connects to FPGA See CP2201 documentation
|-
| 22
| CP2201/RD
| Read strobe for AD bus Connects to FPGA See CP2201 documentation
|-
| 23
| CP2201/WR
| Write strobe for AD bus Connects to FPGA See CP2201 documentation
|-
| 24
| CP2201/CS
| Chip select Connects to FPGA
|-
| 25
| CP2201/INT
| Interrupt request Connects to FPGA
|-
| 26
| DGND
| "MOTEN" (Motorola enable) per the datasheet Tied low to disable Motorola bus format (enable Intel format)
|-
| 27
| CP2201/XTAL2
| Crystal oscillator driver The CP2201 inverts the 20MHz clock signal and feeds it back to the crystal oscillator to encourage larger oscillations
|-
| 28
| FPGA/CLK_IN
| "XTAL1" per the data sheet This is the 20MHz clock input Also connects to the FPGA's clock input
|-
| 29*
| DGND
| This is not a pin but rather the base of the CP2201 package. It is connected to the DGND plane for thermal relief
|}

== Eurocard Connector ==
At the bottom of the control board is the Eurocard connector. The Eurocard connector connects the board to the backplane and also connects the board to its power supplies. The Eurocard has 48 pins arranged in three rows of 16 pins each. Rows B and C are exclusively used to pass SiPM bias voltages to the backplane as described in [[#Channel Mapping | DAC Channel Mapping]]. Here is a table describing the purpose of pins in row A:

=== Row A Pinout Table ===
Note that when viewing the front side of the board with the Eurocard at the bottom, these pins go from right to left. If you look closely at the pins, you will see that pin A1 has a square pad, unlike the round pads of the others.

{| cellpadding=3 border=1 |
| '''Pin #'''
| '''Net Name'''
| '''Description'''
|-
| A1
| CP2201/LA
| Ethernet link/activity indicator routed to backplane
|-
| A2
| High voltage input (+210V max)
| High voltage input for DAC. See [[#DAC | DAC]] for information about what voltage to input here.
|-
| A3
| -5V
| For DAC
|-
| A4
| +5V
| Powers most things on the board
|-
| A5
| AGND
|
|-
| A6
| DGND
|
|-
| A7
| ADC_EXT1
| Connects to ADC to monitor voltages on amplifier board See [[#ADC | ADC]]
|-
| A8
| ADC_EXT2
| Connects to ADC to monitor voltages on amplifier board See [[#ADC | ADC]]
|-
| A9
| No connection
|
|-
| A10
| No connection
|
|-
| A11
| No conneciton
|
|-
| A12
| ID4
| Location identifier bit 4 Used to identify which backplane board is connected to See [[#FPGA | FPGA]]
|-
| A13
| ID3
| Location identifier bit 3 Used to identify which backplane board is connected to See [[#FPGA | FPGA]]
|-
| A14
| ID2
| Location identifier bit 2 Used to identify which backplane board is connected to See [[#FPGA | FPGA]]
|-
| A15
| ID1
| Location identifier bit 1 Used to identify which backplane board is connected to See [[#FPGA | FPGA]]
|-
| A16
| ID0
| Location identifier bit 0 Used to identify which backplane board is connected to See [[#FPGA | FPGA]]
|}

Digital control board documentation

2009-06-16T19:08:38Z

Underwood: /* Row A Pinout Table */

This documentation covers the most important things to know while testing the digital control board, including component pinouts, nets, and other information.

== Power Requirements ==
=== Required Voltages ===
All components on the digital board '''except the DAC''' can be tested using only a +5V source. The DAC requires +5V, -5V, and a high voltage corresponding to 10V higher than the maximum desired DAC output voltage (see [[#Setting the Output Range | Setting the Output Range]]). Digital and analog grounds must be connected as well before any testing takes place.

=== Power Pins ===
Power shall be connected to the board as follows:
{| cellpadding=3 border=1 |
| '''Voltage'''
| '''Eurocard Pin'''
|-
| DGND
| A6
|-
| AGND
| A5
|-
| +5V
| A4
|-
| -5V
| A3
|-
| High voltage (DAC max out +10)
| A2
|}

=== Power Supply Sequencing ===
The control board is designed such that voltages may be supplied in any order so long as AGND and DGND are connected properly. However, for initial testing, the preferred order for powering up the board is as follows:

# Ensure AGND/DGND are connected/grounded
# +5V
# -5V
# High voltage

== FPGA ==
The control board uses a Xilinx XC3S50A VQ100 FPGA. It has a 100 pin footprint and is located in the center of the control board.

=== Power Details ===
The FPGA is powered by the 3.3V power plane, which is regulated by VR1. The FPGA also obtains 1.2V for its internal logic from a 1.2V power island, regulated by VR3.

=== Logic Standard ===
The Xilinx XC3S50A supports several different digital logic standards. The control board is hard wired such that the FPGA will use a '''3.3V CMOS''' logic standard.

=== Pinout Table ===
{| cellpadding=3 border=1 |
| '''Pin #'''
| '''Net Name'''
| '''Description'''
|-
| P1
| FPGA/TMS
| JTAG
|-
| P2
| FPGA/TDI
| JTAG
|-
| P3
| AD7928/CS
| SPI chip select for ADC
|-
| P4
| SPI
| '''Erroneously wired SPI bus trace''' Connects to SDO on temp. sensor and DIN on ADC
|-
| P5
| CLK_5MHZ
| 5 MHz clock output for SPI bus (ADC and temp. sensor)
|-
| P6
| No connection
|
|-
| P7
| No connection
|
|-
| P8
| DGND
|
|-
| P9
| No connection
|
|-
| P10
| No connection
|
|-
| P11
| +3.3V
|
|-
| P12
| No connection
|
|-
| P13
| No connection
|
|-
| P14
| DGND
|
|-
| P15
| No connection
|
|-
| P16
| No connection
|
|-
| P17
| +1.2V
|
|-
| P18
| DGND
|
|-
| P19
| No connection
|
|-
| P20
| No connection
|
|-
| P21
| No connection
|
|-
| P22
| +3.3V
|
|-
| P23
| DGND
|
|-
| P24
| DGND
|
|-
| P25
| DGND
|
|-
| P26
| +3.3V
|
|-
| P27
| FPGA/CLK_IN
| 20 MHz clock input from crystal oscillator
|-
| P28
| No connection
|
|-
| P29
| No connection
|
|-
| P30
| No connection
|
|-
| P31
| No connection
|
|-
| P32
| No connection
|
|-
| P33
| No connection
|
|-
| P34
| No connection
|
|-
| P35
| CP2201/INT
| Ethernet controller interrupt
|-
| P36
| MASTER_RESET
| Connects to RESET jumper in upper left of board (active-low, externally pulled up)
|-
| P37
| No connection
|
|-
| P38
| +1.2V
|
|-
| P39
| No connection
|
|-
| P40
| CP2201/CS
| Chip select for ethernet controller
|-
| P41
| CP2201/WR
| Write enable for ethernet controller
|-
| P42
| DGND
|
|-
| P43
| CP2201/RD
| Read enable for ethernet controller
|-
| P44
| CP2201/ALE
| Address line enable for ethernet controller
|-
| P45
| +3.3V
|
|-
| P46
| CP2201/RESET
| Reset pin for ethernet controller
|-
| P47
| DGND
|
|-
| P48
| FPGA/INIT_B
| Used during FPGA configuration - see Xilinx documentation
|-
| P49
| CP2201/AD0
| Ethernet controller address/data bus, bit 0
|-
| P50
| CP2201/AD1
| Ethernet controller address/data bus, bit 1
|-
| P51
| FPGA/DIN
| Serial data input from EEPROM for configuration
|-
| P52
| CP2201/AD2
| Ethernet controller address/data bus, bit 2
|-
| P53
| FPGA/CCLK
| Configuration clock (signal generated by FPGA at power on to clock the configuration process) See Xilinx documentation
|-
| P54
| FPGA/DONE
| Gives configuration status - see Xilinx documentation
|-
| P55
| +3.3V
|
|-
| P56
| CP2201/AD3
| Ethernet controller address/data bus, bit 3
|-
| P57
| CP2201/AD4
| Ethernet controller address/data bus, bit 4
|-
| P58
| DGND
|
|-
| P59
| CP2201/AD5
| Ethernet controller address/data bus, bit 5
|-
| P60
| CP2201/AD6
| Ethernet controller address/date bus, bit 6
|-
| P61
| CP2201/AD7
| Ethernet controller address/date bus, bit 7
|-
| P62
| No connection
|
|-
| P63
| DGND
|
|-
| P64
| No connection
|
|-
| P65
| No connection
|
|-
| P66
| +1.2V
|
|-
| P67
| +3.3V
|
|-
| P68
| +3.3V
|
|-
| P69
| DGND
|
|-
| P70
| ID3
| Backplane location identifier jumper, pins 3 & 4 Active-low, FPGA should pull high
|-
| P71
| ID2
| Backplane location identifier jumper, pins 5 & 6 Active-low, FPGA should pull high
|-
| P72
| ID1
| Backplane location identifier jumper, pins 7 & 8 Active-low, FPGA should pull high
|-
| P73
| ID0
| Backplane location identifier jumper, pins 9 & 10 Active-low, FPGA should pull high
|-
| P74
| DGND
|
|-
| P75
| FPGA/TDO
| JTAG
|-
| P76
| FPGA/TCK
| JTAG
|-
| P77
| ID4
| Backplane location identifier jumper, pins 1 & 2 Active-low, FPGA should pull high
|-
| P78
| No connection
|
|-
| P79
| +3.3V
|
|-
| P80
| DGND
|
|-
| P81
| +1.2V
|
|-
| P82
| No connection
|
|-
| P83
| CLK_5MHZ_2
| 5 MHz clock output for DAC
|-
| P84
| No connection
|
|-
| P85
| AD5535/DIN
| DAC serial data input (FPGA out -> DAC in)
|-
| P86
| No connection
|
|-
| P87
| DGND
|
|-
| P89
| No connection
|
|-
| P90
| No connection
|
|-
| P91
| DGND
|
|-
| P92
| +3.3V
|
|-
| P93
| AD7314/CE
| Chip enable for temperature sensor
|-
| P94
| No connection
|
|-
| P95
| DGND
|
|-
| P96
| +3.3V
|
|-
| P97
| AD7928/DOUT
| '''Erroneously wired ADC SPI bus connection''' Connects to DOUT on ADC
|-
| P98
| AD5535/RESET
| Reset pin for DAC
|-
| P99
| DGND
|
|-
| P100
| FPGA/PROG_B
| Used during FPGA configuration - see Xilinx documentation
|}

== EEPROM ==
To facilitate power-on configuration of the FPGA, the control board includes a Xilinx XCF01S EEPROM. The EEPROM is located to the left of the FPGA, above the JTAG header, and has a 20 pin footprint. The EEPROM is labelled U5.

=== Power Details ===
The EEPROM uses +3.3V exclusively, which it receives from the +3.3V power plane, regulated by VR1.

=== Flashing/Burning/Writing ===
Whatever you call it, this refers to storing data in the EEPROM so that it can configure the FPGA at power-on. The EEPROM is programmed using a JTAG interface and the Xilinx Platform USB II cable. It is important to note that in digital board's JTAG chain, the EEPROM is the first device in the chain, unlike in the Xilinx documentation where it is shown as the second device. This should not affect the operation of the board, but should be reflected in the Xilinx software when writing the EEPROM via JTAG.

=== FPGA Configuration ===
The EEPROM and FPGA are hardwired to use a master serial protocol to transfer the program from the EEPROM to the FPGA. This is the protocol recommended in the Xilinx documentation because it minimizes the number of traces necessary to run between the EEPROM and FPGA. All configuration data is sent over a single trace, FPGA/DIN (pin 1 on EEPROM), controlled by the configuration clock signal (FPGA/CCLK) which is automatically generated by the FPGA at power-on. When configuration is complete, FPGA/DONE (pin 10) is pulled high by the FPGA, and the EEPROM and configuration clock are deactivated.

=== Pinout Table ===
{| cellpadding=3 border=1 |
| '''Pin #'''
| '''Net Name'''
| '''Description'''
|-
| 1
| FPGA/DIN
| Serial data line Carries data from the EEPROM to the FPGA
|-
| 2
| No connection
|
|-
| 3
| FPGA/CCLK
| Configuration clock Auto generated by FPGA at power-on, disabled at end of configuration
|-
| 4
| EEPROM/TDI
| This is the EEPROM's TDI This is the entry point for the onboard JTAG chain
|-
| 5
| FPGA/TMS
| JTAG TMS Connects to both FPGA and EEPROM
|-
| 6
| FPGA/TCK
| JTAG TCK Connects to both FPGA and EEPROM
|-
| 7
| FPGA/PROG_B
| Used during configuration See Xilinx documentation
|-
| 8
| FPGA/INIT_B
| Used during configuration - can be used to intiate reconfiguration of FPGA See Xilinx documentation
|-
| 9
| No connection
|
|-
| 10
| FPGA/DONE
| Indicates completion of FPGA configuration High when complete
|-
| 11
| DGND
|
|-
| 12-16
| No connection
|
|-
| 17
| FPGA/TDI
| This is the EEPROM's TDO/FPGA's TDI
|-
| 18-20
| +3.3V
|
|}

== JTAG Header ==
To write the FPGA's program to the EEPROM, the board employs a JTAG based programming system consistent with Xilinx's recommendations. The system is designed to operate with Xilnx's Platform USB II cable and the flying lead adapter.

===Header Location and Size===
The header consists of 14 pins, 100 mil pitch, just below the EEPROM (U5). The header is labelled P1. The pitch of the pins in the header was erroneously selected to be 100 mil, which is not compatible with Xilinx's JTAG ribbon cable. Therefore, the Xilinx flying lead adapter must be used.

===Power Details===
The JTAG interface is powered by the +3.3V power plane, not by the computer's USB port. Power is supplied through pin 2 of the JTAG header.

===Pinout Table===
Note that the header is positioned on the board rotated 180 degrees from the position in which it is shown in the Xilinx documentation. Care must be taken when connecting the flying leads to ensure they are connected to the right pins. Connecting the flying leads to the wrong side of the header will cause all of the leads to short on the digital board's ground plane. This will certainly cause undesired operation, and may or may not cause damage. Improper wiring is most likely to cause damage if one of the flying leads is connected to an odd numbered pin. '''Note from the pinout table below that no flying lead connections should ever be made to the odd numbered pins on the JTAG header.'''

{| cellpadding=3 border=1 |
| '''Pin #'''
| '''Net Name'''
| '''Description'''
|-
| 1, 3, 5, 7, 9, 11, 13 (odd pins)
| DGND
| Ground pins for signal integrity '''Never connect a flying lead to these pins''' Doing so will short to ground and may cause permanent damage if the Platform USB II cable does not have protection against this.
|-
| 2
| +3.3V
| Power source for all JTAG logic
|-
| 4
| FPGA/TMS
| JTAG TMS - connects to EEPROM and FPGA
|-
| 6
| FPGA/TCK
| JTAG TCK - connects to EEPROM and FPGA
|-
| 8
| FPGA/TDO
| JTAG boundary scan chain endpoint
|-
| 10
| EEPROM/TDI
| JTAG boundary scan chain start point
|-
| 12
| No connection
| Pin is floating
|-
| 14
| No connection
| Pin is floating
|}

===JTAG Overview===
The JTAG interface is clocked by the TCK signal. TCK is generated by the Platform USB II cable, and connects directly from the JTAG header to both the EEPROM and FPGA.

The TMS signal is directly connected to both the EEPROM and FPGA, and is the data line over which JTAG test results (in this case programming results) are sent. TMS is used by only one component at a time.

The TDI/TDO lines form a chain that connects to each JTAG component in series. On the control board, the first point in the chain is the EEPROM's TDI. Next is the EEPROM's TDO, which is the same as the FPGA's TDI. The FPGA's TDO then returns to the JTAG header and the Platform USB II cable.

== DAC ==
The control board uses the Analog Devices AD5535, 32-channel, 200V max, digital to analog converter. This chip has a modified BC-124 BGA footprint and is located above the Eurocard connector at the bottom of the board. It is labelled U3.

=== Power Details ===
The DAC is primarily powered by the +5V power island, regulated by an off-board power supply and extensively decoupled in the area of the DAC. The DAC also requires -5V, and a high voltage as discussed in [[#Power Requirements | Power Requirements]]. Both of these voltages are supplied by an off-board supply and decoupled near the DAC. In addition to these voltage levels, the DAC requires a precise +2.5V reference, created by the shunt-type voltage reference VR4.

=== Setting the Output Range ===
The output range of the DAC is set by the 2.5V reference voltage supplied by VR4. The high voltage power supply must supply at a minimum 50 times this voltage, plus 10. Thus, the high voltage power supply should be at least 135V for DAC to operate properly, even though the SiPMs are expected to need only 40V. If it is convenient to use a lower high voltage, VR4 must be replaced to provide lower reference voltage. The high voltage may then be decreased appropriately. To summarize:

* Max output voltage = VREF*50
* Minimum high voltage supply = VREF*50 + 10
* Acceptable range for VREF
** Min: 1V
** Max: 3.75V (AD5535 datasheet specifies 4V max, but this would require AVCC of 5.25V for the DAC, which is not possible in the current board design)

If relevant, R13 is a 100K resistor.

=== Thermal Diode ===
The DAC has a built in thermal diode. The diode drop from anode to cathode is typically 0.65V at 25°C. It changes at a rate of -2.20mV/°C. The anode of this diode is connected to the +5V power island, and the cathode is connected to a 270K resistor to ground. The voltage between the cathode and the resistor is connected to VIN1 (pin 15) on the ADC.

=== Pinout Table ===
See documentation from Analog Devices.

=== Channel Mapping ===
Due to the layout of the balls on the footprint of the DAC, the DAC's internal channel numbers (which must be referenced by the FPGA) have no correlation to the channel numbers on the amplifier board. This table summarizes the mapping between various pins that belong to each channel.

{| cellpadding=3 border=1 |
| '''DAC Channel #'''
| '''DAC Pin #'''
| '''Digital Board Eurocard Pin #'''
| '''Amplifier Board Eurocard Pin #'''
| '''Physical Channel #'''
|-
| 0
| B1
| B3
|
|
|-
| 1
| A2
| C4
|
|
|-
| 2
| D1
| B2
|
|
|-
| 3
| C2
| C3
|
|
|-
| 4
| B3
| B4
|
|
|-
| 5
| E2
| C2
|
|
|-
| 6
| F3
| B1
|
|
|-
| 7
| A4
| B5
|
|
|-
| 8
| E4
| C5
|
|
|-
| 9
| B5
| C6
|
|
|-
| 10
| F5
| C1
|
|
|-
| 11
| A6
| C7
|
|
|-
| 12
| E6
| B6
|
|
|-
| 13
| B7
| B7
|
|
|-
| 14
| F7
| C10
|
|
|-
| 15
| E8
| C8
|
|
|-
| 16
| A8
| B8
|
|
|-
| 17
| B9
| C9
|
|
|-
| 18
| F9
| C16
|
|
|-
| 19
| E10
| B11
|
|
|-
| 20
| A10
| B9
|
|
|-
| 21
| B11
| B10
|
|
|-
| 22
| C12
| B12
|
|
|-
| 23
| D13
| B13
|
|
|-
| 24
| E12
| B14
|
|
|-
| 25
| A12
| C11
|
|
|-
| 26
| B13
| C12
|
|
|-
| 27
| H13
| B16
|
|
|-
| 28
| G14
| B15
|
|
|-
| 29
| C14
| C13
|
|
|-
| 30
| F13
| C15
|
|
|-
| 31
| E14
| C14
|
| DACHEALTH See [[#Channel Descriptions | ADC Channel Descriptions]].
|}

==ADC==
The board includes an Analog Devices AD7928 analog to digital converter. The ADC is located just to the right and slightly below the FPGA. It is labelled U4.

===Power Details===
The ADC is powered by the +5V power island, which is regulated by an off-board power supply and decoupled near the ADC. It also requires a precise (±1%) 2.5V reference to which it compares voltages when converting from analog to digital. Since the +5V power source is not used for comparison, it is flexible and may vary by ±0.25V without affecting ADC precision.

===Setting the Measuring Range===
The measuring range is set programmatically by the FPGA over the SPI bus. The way the ADC is connected on the digital board requires that its measuring range be set to 5V, so the RANGE bit should be set to 1 by the FPGA (see Analog Devices documentation).

===Data Interfacing===
The ADC uses an SPI bus to communicate with the FPGA. This bus is shared with the temperature sensor. SPI related pins include SCLK, CS, DIN, and DOUT. See the Pinout Table below.

===Channel Descriptions===
This table shows what signals are monitored by the ADC.

{| cellpadding=3 border=1 |
| '''ADC Channel #'''
| '''ADC Pin #'''
| '''Net Name'''
| '''Description'''
|-
| VIN0
| 16
| AD7928/VHEALTH
| This net helps to monitor to overall health of power on the board, but is specifically intended to monitor -5V. It's voltage is the output of a resistor divider between the +5 and -5V power supplies, with resistor values of 33.2K, and 100K. Assuming +5V and -5V are both correct, the output of the divider will be +2.51V. A reading of other than 2.51V indicates a problem with one of the power supplies. Problems with the +5V power supply can be ruled out by reading VIN3. Based on the reading from VIN3, the voltage of the -5V supply can be calculated.
|-
| VIN1
| 15
| AD5535/CATHODE
| This is the thermal diode output from the DAC. Should read 4.35V (typical) at 25°C. Drops 2.20mV/°C.
|-
| VIN2
| 14
| +3.3V
| This is the +3.3V power plane. A reading of other than +3.3V indicates a problem with VR1.
|-
| VIN3
| 13
| +5V
| This is the +5V power island. A reading of other than +5V indicates a problem with the +5V power supply.
|-
| VIN4
| 12
| ADC_EXT1
| This trace routes to the backplane via Eurocard pin A7. It is intended to measure the output of thermistor on the amplifier board.
|-
| VIN5
| 11
| +1.2V
| This is the +1.2V power island. This island powers the internal logic of the FPGA. A reading of other than 1.2V indicates a problem with VR3.
|-
| VIN6
| 10
| ADC_EXT2
| This trace routes to the backplane via Eurocard pin A8. It is intended to measure one of the transistor base voltages on the amplifier board.
|-
| VIN7
| 9
| DACHEALTH
| This channel monitors the output of a resistor divider connected to channel 31 of the DAC. The divider consists of three resistors of 200K, 200K, and 10.2K (in order). The ADC reads out the voltage level between the second 200K and then 10.2K resistor. These resistors were selected so that at 200V, the readout voltage will be 4.973V. Since the divider should be linear, the expected voltage at 20V is 0.4973V. Three resistors were used rather than two to avoid exceeding the resistors' power ratings when the DAC is set to its maximum voltage. Note that since this divider will consume up to 484uA of current at 200V, this DAC channel should not be used for anything that might require more than ~200uA of current (the DAC can source 700uA max). The channel is routed to the backplane nonetheless.
|}

===Pinout Table===
{| cellpadding=3 border=1 |
| '''Pin #'''
| '''Net Name'''
| '''Description'''
|-
| 1
| CLK_5MHZ
| SPI clock (SCLK), from FPGA Shared with temperature sensor
|-
| 2
| DIN
| SPI data in, from FPGA Shared with temperature sensor ''Currently wired wrong''
|-
| 3
| CS
| SPI chip select
|-
| 4
| AGND
|
|-
| 5
| +5V
| Power pin
|-
| 6
| +5V
| Power pin
|-
| 7
| AD7928/REF_IN
| +2.5V reference, set by VR2
|-
| 8
| AGND
|
|-
| 9-16
| VIN[7:0]
| See [[#Channel Descriptions | ADC Channel Descriptions]]
|-
| 17
| AGND
|
|-
| 18
| DOUT
| SPI data out ''Currently wired incorrectly''
|-
| 19
| +3.3V
| VDRIVE, powers the SPI logic
|-
| 20
| AGND
|
|}

== Ethernet Controller ==
The board uses a Silicon Laboratories CP2201, 28-pin, ethernet controller. The CP2201 is located just above the FPGA, and is labelled U2.

=== Power Details ===
The CP2201 uses only +3.3V, which is supplied by the +3.3V power plane and regulated by VR1. Appropriate decoupling capacitors can be found near the CP2201.

=== Ethernet Jack ===
To the right of the CP2201 is a Pulse J0011D21NL ethernet jack, labelled J1. This jack has a built-in 1:1 inductive coupling. For best results, connect this jack to a nearby ethernet switch. The jack may also be connected directly to a computer using a crossover cable. Though auto-crossover is not supported by the CP2201, if the computer's NIC supports it, a crossover cable is not necessary to connect directly to a computer.

=== Crystal Oscillator ===
The CP2201 is responsible for driving the 20MHz crystal oscillator. This oscillator clocks both the CP2201 and the FPGA. The crystal oscillator can be found above the right corner of the FPGA. It can be identified by its four surface mount pads and roughly .3" length. It is labelled Y1, though this label is not visible after the oscillator is soldered on. The CP2201 uses an inverting driver to excite the crystal. The output of the crystal is then sent to the CP2201 and the FPGA.

=== Bus Format and Multiplexing ===
The 28-pin CP2201 used on the board only supports multiplexed operation. This means that both address and data information are passed over the same set of 8 traces. Hence, these traces are referred to as the address/data (AD) bus. A separate address line enable (ALE) trace prevents collisions from occuring on these traces. The communication protocol used is the Intel format. See the CP2201's datasheet for more information about this.

=== Pinout Table ===
{| cellpadding=3 border=1 |
| '''Pin #'''
| '''Net Name'''
| '''Description'''
|-
| 1
| CP2201/LA
| Link/activity indicator Routed to backplane but not implemented See CP2201 data sheet for information on how to connect to an LED
|-
| 2
| DGND
| By the data sheet, this pin should be AGND We deliberately set it to DGND to avoid noise on AGND plane
|-
| 3
| +3.3V
| AV+ power pin
|-
| 4
| CP2201/RX-
| Connects to RX- on ethernet jack
|-
| 5
| CP2201/RX+
| Connects to RX+ on ethernet jack
|-
| 6
| CP2201/TX+
| Connects to TX+ on ethernet jack
|-
| 7
| CP2201/TX-
| Connects to TX- on ethernet jack
|-
| 8
| +3.3V
| "VDD" power pin
|-
| 9
| DGND
| "DGND1" per the data sheet
|-
| 10
| CP2201/RESET
| "RST" per the data sheet Connects to FPGA - should be programmatically triggered upon reset of FPGA by RESET jumper
|-
| 11-18
| CP2201/AD[0:7]
| Bits 0-7 of the address/data bus Connect to FPGA
|-
| 19
| +3.3V
| "VDD" power pin
|-
| 20
| DGND
| "DGND2" per the data sheet
|-
| 21
| CP2201/ALE
| Address line enable Connects to FPGA See CP2201 documentation
|-
| 22
| CP2201/RD
| Read strobe for AD bus Connects to FPGA See CP2201 documentation
|-
| 23
| CP2201/WR
| Write strobe for AD bus Connects to FPGA See CP2201 documentation
|-
| 24
| CP2201/CS
| Chip select Connects to FPGA
|-
| 25
| CP2201/INT
| Interrupt request Connects to FPGA
|-
| 26
| DGND
| "MOTEN" (Motorola enable) per the datasheet Tied low to disable Motorola bus format (enable Intel format)
|-
| 27
| CP2201/XTAL2
| Crystal oscillator driver The CP2201 inverts the 20MHz clock signal and feeds it back to the crystal oscillator to encourage larger oscillations
|-
| 28
| FPGA/CLK_IN
| "XTAL1" per the data sheet This is the 20MHz clock input Also connects to the FPGA's clock input
|-
| 29*
| DGND
| This is not a pin but rather the base of the CP2201 package. It is connected to the DGND plane for thermal relief
|}

== Eurocard Connector ==
At the bottom of the control board is the Eurocard connector. The Eurocard connector connects the board to the backplane and also connects the board to its power supplies. The Eurocard has 48 pins arranged in three rows of 16 pins each. Rows B and C are exclusively used to pass SiPM bias voltages to the backplane as described in [[#Channel Mapping | DAC Channel Mapping]]. Here is a table describing the purpose of pins in row A:

=== Row A Pinout Table ===
Note that when viewing the front side of the board with the Eurocard at the bottom, these pins go from right to left. If you look closely at the pins, you will see that pin A1 has a square pad, unlike the round pads of the others.

{| cellpadding=3 border=1 |
| '''Pin #'''
| '''Net Name'''
| '''Description'''
|-
| A1
| CP2201/LA
| Ethernet link/activity indicator routed to backplane
|-
| A2
| High voltage input (+210V max)
| High voltage input for DAC. See [[#DAC | DAC]] for information about what voltage to input here.
|-
| A3
| -5V
| For DAC
|-
| A4
| +5V
| Powers most things on the board
|-
| A5
| AGND
|
|-
| A6
| DGND
|
|-
| A7
| ADC_EXT1
| Connects to ADC to monitor voltages on amplifier board See [[#ADC | ADC]]
|-
| A8
| ADC_EXT2
| Connects to ADC to monitor voltages on amplifier board See [[#ADC | ADC]]
|-
| A9
| No connection
|
|-
| A10
| No connection
|
|-
| A11
| No conneciton
|
|-
| A12
| ID4
| Location identifier bit 4 Used to identify which backplane board is connected to See [[#FPGA | FPGA]]
|-
| A13
| ID3
| Location identifier bit 3 Used to identify which backplane board is connected to See [[#FPGA | FPGA]]
|-
| A14
| ID2
| Location identifier bit 2 Used to identify which backplane board is connected to See [[#FPGA | FPGA]]
|-
| A15
| ID1
| Location identifier bit 1 Used to identify which backplane board is connected to See [[#FPGA | FPGA]]
|-
| A16
| ID0
| Location identifier bit 0 Used to identify which backplane board is connected to See [[#FPGA | FPGA]]
|}

Digital control board documentation

2009-06-16T19:08:08Z

Underwood: /* Eurocard Connector */

This documentation covers the most important things to know while testing the digital control board, including component pinouts, nets, and other information.

== Power Requirements ==
=== Required Voltages ===
All components on the digital board '''except the DAC''' can be tested using only a +5V source. The DAC requires +5V, -5V, and a high voltage corresponding to 10V higher than the maximum desired DAC output voltage (see [[#Setting the Output Range | Setting the Output Range]]). Digital and analog grounds must be connected as well before any testing takes place.

=== Power Pins ===
Power shall be connected to the board as follows:
{| cellpadding=3 border=1 |
| '''Voltage'''
| '''Eurocard Pin'''
|-
| DGND
| A6
|-
| AGND
| A5
|-
| +5V
| A4
|-
| -5V
| A3
|-
| High voltage (DAC max out +10)
| A2
|}

=== Power Supply Sequencing ===
The control board is designed such that voltages may be supplied in any order so long as AGND and DGND are connected properly. However, for initial testing, the preferred order for powering up the board is as follows:

# Ensure AGND/DGND are connected/grounded
# +5V
# -5V
# High voltage

== FPGA ==
The control board uses a Xilinx XC3S50A VQ100 FPGA. It has a 100 pin footprint and is located in the center of the control board.

=== Power Details ===
The FPGA is powered by the 3.3V power plane, which is regulated by VR1. The FPGA also obtains 1.2V for its internal logic from a 1.2V power island, regulated by VR3.

=== Logic Standard ===
The Xilinx XC3S50A supports several different digital logic standards. The control board is hard wired such that the FPGA will use a '''3.3V CMOS''' logic standard.

=== Pinout Table ===
{| cellpadding=3 border=1 |
| '''Pin #'''
| '''Net Name'''
| '''Description'''
|-
| P1
| FPGA/TMS
| JTAG
|-
| P2
| FPGA/TDI
| JTAG
|-
| P3
| AD7928/CS
| SPI chip select for ADC
|-
| P4
| SPI
| '''Erroneously wired SPI bus trace''' Connects to SDO on temp. sensor and DIN on ADC
|-
| P5
| CLK_5MHZ
| 5 MHz clock output for SPI bus (ADC and temp. sensor)
|-
| P6
| No connection
|
|-
| P7
| No connection
|
|-
| P8
| DGND
|
|-
| P9
| No connection
|
|-
| P10
| No connection
|
|-
| P11
| +3.3V
|
|-
| P12
| No connection
|
|-
| P13
| No connection
|
|-
| P14
| DGND
|
|-
| P15
| No connection
|
|-
| P16
| No connection
|
|-
| P17
| +1.2V
|
|-
| P18
| DGND
|
|-
| P19
| No connection
|
|-
| P20
| No connection
|
|-
| P21
| No connection
|
|-
| P22
| +3.3V
|
|-
| P23
| DGND
|
|-
| P24
| DGND
|
|-
| P25
| DGND
|
|-
| P26
| +3.3V
|
|-
| P27
| FPGA/CLK_IN
| 20 MHz clock input from crystal oscillator
|-
| P28
| No connection
|
|-
| P29
| No connection
|
|-
| P30
| No connection
|
|-
| P31
| No connection
|
|-
| P32
| No connection
|
|-
| P33
| No connection
|
|-
| P34
| No connection
|
|-
| P35
| CP2201/INT
| Ethernet controller interrupt
|-
| P36
| MASTER_RESET
| Connects to RESET jumper in upper left of board (active-low, externally pulled up)
|-
| P37
| No connection
|
|-
| P38
| +1.2V
|
|-
| P39
| No connection
|
|-
| P40
| CP2201/CS
| Chip select for ethernet controller
|-
| P41
| CP2201/WR
| Write enable for ethernet controller
|-
| P42
| DGND
|
|-
| P43
| CP2201/RD
| Read enable for ethernet controller
|-
| P44
| CP2201/ALE
| Address line enable for ethernet controller
|-
| P45
| +3.3V
|
|-
| P46
| CP2201/RESET
| Reset pin for ethernet controller
|-
| P47
| DGND
|
|-
| P48
| FPGA/INIT_B
| Used during FPGA configuration - see Xilinx documentation
|-
| P49
| CP2201/AD0
| Ethernet controller address/data bus, bit 0
|-
| P50
| CP2201/AD1
| Ethernet controller address/data bus, bit 1
|-
| P51
| FPGA/DIN
| Serial data input from EEPROM for configuration
|-
| P52
| CP2201/AD2
| Ethernet controller address/data bus, bit 2
|-
| P53
| FPGA/CCLK
| Configuration clock (signal generated by FPGA at power on to clock the configuration process) See Xilinx documentation
|-
| P54
| FPGA/DONE
| Gives configuration status - see Xilinx documentation
|-
| P55
| +3.3V
|
|-
| P56
| CP2201/AD3
| Ethernet controller address/data bus, bit 3
|-
| P57
| CP2201/AD4
| Ethernet controller address/data bus, bit 4
|-
| P58
| DGND
|
|-
| P59
| CP2201/AD5
| Ethernet controller address/data bus, bit 5
|-
| P60
| CP2201/AD6
| Ethernet controller address/date bus, bit 6
|-
| P61
| CP2201/AD7
| Ethernet controller address/date bus, bit 7
|-
| P62
| No connection
|
|-
| P63
| DGND
|
|-
| P64
| No connection
|
|-
| P65
| No connection
|
|-
| P66
| +1.2V
|
|-
| P67
| +3.3V
|
|-
| P68
| +3.3V
|
|-
| P69
| DGND
|
|-
| P70
| ID3
| Backplane location identifier jumper, pins 3 & 4 Active-low, FPGA should pull high
|-
| P71
| ID2
| Backplane location identifier jumper, pins 5 & 6 Active-low, FPGA should pull high
|-
| P72
| ID1
| Backplane location identifier jumper, pins 7 & 8 Active-low, FPGA should pull high
|-
| P73
| ID0
| Backplane location identifier jumper, pins 9 & 10 Active-low, FPGA should pull high
|-
| P74
| DGND
|
|-
| P75
| FPGA/TDO
| JTAG
|-
| P76
| FPGA/TCK
| JTAG
|-
| P77
| ID4
| Backplane location identifier jumper, pins 1 & 2 Active-low, FPGA should pull high
|-
| P78
| No connection
|
|-
| P79
| +3.3V
|
|-
| P80
| DGND
|
|-
| P81
| +1.2V
|
|-
| P82
| No connection
|
|-
| P83
| CLK_5MHZ_2
| 5 MHz clock output for DAC
|-
| P84
| No connection
|
|-
| P85
| AD5535/DIN
| DAC serial data input (FPGA out -> DAC in)
|-
| P86
| No connection
|
|-
| P87
| DGND
|
|-
| P89
| No connection
|
|-
| P90
| No connection
|
|-
| P91
| DGND
|
|-
| P92
| +3.3V
|
|-
| P93
| AD7314/CE
| Chip enable for temperature sensor
|-
| P94
| No connection
|
|-
| P95
| DGND
|
|-
| P96
| +3.3V
|
|-
| P97
| AD7928/DOUT
| '''Erroneously wired ADC SPI bus connection''' Connects to DOUT on ADC
|-
| P98
| AD5535/RESET
| Reset pin for DAC
|-
| P99
| DGND
|
|-
| P100
| FPGA/PROG_B
| Used during FPGA configuration - see Xilinx documentation
|}

== EEPROM ==
To facilitate power-on configuration of the FPGA, the control board includes a Xilinx XCF01S EEPROM. The EEPROM is located to the left of the FPGA, above the JTAG header, and has a 20 pin footprint. The EEPROM is labelled U5.

=== Power Details ===
The EEPROM uses +3.3V exclusively, which it receives from the +3.3V power plane, regulated by VR1.

=== Flashing/Burning/Writing ===
Whatever you call it, this refers to storing data in the EEPROM so that it can configure the FPGA at power-on. The EEPROM is programmed using a JTAG interface and the Xilinx Platform USB II cable. It is important to note that in digital board's JTAG chain, the EEPROM is the first device in the chain, unlike in the Xilinx documentation where it is shown as the second device. This should not affect the operation of the board, but should be reflected in the Xilinx software when writing the EEPROM via JTAG.

=== FPGA Configuration ===
The EEPROM and FPGA are hardwired to use a master serial protocol to transfer the program from the EEPROM to the FPGA. This is the protocol recommended in the Xilinx documentation because it minimizes the number of traces necessary to run between the EEPROM and FPGA. All configuration data is sent over a single trace, FPGA/DIN (pin 1 on EEPROM), controlled by the configuration clock signal (FPGA/CCLK) which is automatically generated by the FPGA at power-on. When configuration is complete, FPGA/DONE (pin 10) is pulled high by the FPGA, and the EEPROM and configuration clock are deactivated.

=== Pinout Table ===
{| cellpadding=3 border=1 |
| '''Pin #'''
| '''Net Name'''
| '''Description'''
|-
| 1
| FPGA/DIN
| Serial data line Carries data from the EEPROM to the FPGA
|-
| 2
| No connection
|
|-
| 3
| FPGA/CCLK
| Configuration clock Auto generated by FPGA at power-on, disabled at end of configuration
|-
| 4
| EEPROM/TDI
| This is the EEPROM's TDI This is the entry point for the onboard JTAG chain
|-
| 5
| FPGA/TMS
| JTAG TMS Connects to both FPGA and EEPROM
|-
| 6
| FPGA/TCK
| JTAG TCK Connects to both FPGA and EEPROM
|-
| 7
| FPGA/PROG_B
| Used during configuration See Xilinx documentation
|-
| 8
| FPGA/INIT_B
| Used during configuration - can be used to intiate reconfiguration of FPGA See Xilinx documentation
|-
| 9
| No connection
|
|-
| 10
| FPGA/DONE
| Indicates completion of FPGA configuration High when complete
|-
| 11
| DGND
|
|-
| 12-16
| No connection
|
|-
| 17
| FPGA/TDI
| This is the EEPROM's TDO/FPGA's TDI
|-
| 18-20
| +3.3V
|
|}

== JTAG Header ==
To write the FPGA's program to the EEPROM, the board employs a JTAG based programming system consistent with Xilinx's recommendations. The system is designed to operate with Xilnx's Platform USB II cable and the flying lead adapter.

===Header Location and Size===
The header consists of 14 pins, 100 mil pitch, just below the EEPROM (U5). The header is labelled P1. The pitch of the pins in the header was erroneously selected to be 100 mil, which is not compatible with Xilinx's JTAG ribbon cable. Therefore, the Xilinx flying lead adapter must be used.

===Power Details===
The JTAG interface is powered by the +3.3V power plane, not by the computer's USB port. Power is supplied through pin 2 of the JTAG header.

===Pinout Table===
Note that the header is positioned on the board rotated 180 degrees from the position in which it is shown in the Xilinx documentation. Care must be taken when connecting the flying leads to ensure they are connected to the right pins. Connecting the flying leads to the wrong side of the header will cause all of the leads to short on the digital board's ground plane. This will certainly cause undesired operation, and may or may not cause damage. Improper wiring is most likely to cause damage if one of the flying leads is connected to an odd numbered pin. '''Note from the pinout table below that no flying lead connections should ever be made to the odd numbered pins on the JTAG header.'''

{| cellpadding=3 border=1 |
| '''Pin #'''
| '''Net Name'''
| '''Description'''
|-
| 1, 3, 5, 7, 9, 11, 13 (odd pins)
| DGND
| Ground pins for signal integrity '''Never connect a flying lead to these pins''' Doing so will short to ground and may cause permanent damage if the Platform USB II cable does not have protection against this.
|-
| 2
| +3.3V
| Power source for all JTAG logic
|-
| 4
| FPGA/TMS
| JTAG TMS - connects to EEPROM and FPGA
|-
| 6
| FPGA/TCK
| JTAG TCK - connects to EEPROM and FPGA
|-
| 8
| FPGA/TDO
| JTAG boundary scan chain endpoint
|-
| 10
| EEPROM/TDI
| JTAG boundary scan chain start point
|-
| 12
| No connection
| Pin is floating
|-
| 14
| No connection
| Pin is floating
|}

===JTAG Overview===
The JTAG interface is clocked by the TCK signal. TCK is generated by the Platform USB II cable, and connects directly from the JTAG header to both the EEPROM and FPGA.

The TMS signal is directly connected to both the EEPROM and FPGA, and is the data line over which JTAG test results (in this case programming results) are sent. TMS is used by only one component at a time.

The TDI/TDO lines form a chain that connects to each JTAG component in series. On the control board, the first point in the chain is the EEPROM's TDI. Next is the EEPROM's TDO, which is the same as the FPGA's TDI. The FPGA's TDO then returns to the JTAG header and the Platform USB II cable.

== DAC ==
The control board uses the Analog Devices AD5535, 32-channel, 200V max, digital to analog converter. This chip has a modified BC-124 BGA footprint and is located above the Eurocard connector at the bottom of the board. It is labelled U3.

=== Power Details ===
The DAC is primarily powered by the +5V power island, regulated by an off-board power supply and extensively decoupled in the area of the DAC. The DAC also requires -5V, and a high voltage as discussed in [[#Power Requirements | Power Requirements]]. Both of these voltages are supplied by an off-board supply and decoupled near the DAC. In addition to these voltage levels, the DAC requires a precise +2.5V reference, created by the shunt-type voltage reference VR4.

=== Setting the Output Range ===
The output range of the DAC is set by the 2.5V reference voltage supplied by VR4. The high voltage power supply must supply at a minimum 50 times this voltage, plus 10. Thus, the high voltage power supply should be at least 135V for DAC to operate properly, even though the SiPMs are expected to need only 40V. If it is convenient to use a lower high voltage, VR4 must be replaced to provide lower reference voltage. The high voltage may then be decreased appropriately. To summarize:

* Max output voltage = VREF*50
* Minimum high voltage supply = VREF*50 + 10
* Acceptable range for VREF
** Min: 1V
** Max: 3.75V (AD5535 datasheet specifies 4V max, but this would require AVCC of 5.25V for the DAC, which is not possible in the current board design)

If relevant, R13 is a 100K resistor.

=== Thermal Diode ===
The DAC has a built in thermal diode. The diode drop from anode to cathode is typically 0.65V at 25°C. It changes at a rate of -2.20mV/°C. The anode of this diode is connected to the +5V power island, and the cathode is connected to a 270K resistor to ground. The voltage between the cathode and the resistor is connected to VIN1 (pin 15) on the ADC.

=== Pinout Table ===
See documentation from Analog Devices.

=== Channel Mapping ===
Due to the layout of the balls on the footprint of the DAC, the DAC's internal channel numbers (which must be referenced by the FPGA) have no correlation to the channel numbers on the amplifier board. This table summarizes the mapping between various pins that belong to each channel.

{| cellpadding=3 border=1 |
| '''DAC Channel #'''
| '''DAC Pin #'''
| '''Digital Board Eurocard Pin #'''
| '''Amplifier Board Eurocard Pin #'''
| '''Physical Channel #'''
|-
| 0
| B1
| B3
|
|
|-
| 1
| A2
| C4
|
|
|-
| 2
| D1
| B2
|
|
|-
| 3
| C2
| C3
|
|
|-
| 4
| B3
| B4
|
|
|-
| 5
| E2
| C2
|
|
|-
| 6
| F3
| B1
|
|
|-
| 7
| A4
| B5
|
|
|-
| 8
| E4
| C5
|
|
|-
| 9
| B5
| C6
|
|
|-
| 10
| F5
| C1
|
|
|-
| 11
| A6
| C7
|
|
|-
| 12
| E6
| B6
|
|
|-
| 13
| B7
| B7
|
|
|-
| 14
| F7
| C10
|
|
|-
| 15
| E8
| C8
|
|
|-
| 16
| A8
| B8
|
|
|-
| 17
| B9
| C9
|
|
|-
| 18
| F9
| C16
|
|
|-
| 19
| E10
| B11
|
|
|-
| 20
| A10
| B9
|
|
|-
| 21
| B11
| B10
|
|
|-
| 22
| C12
| B12
|
|
|-
| 23
| D13
| B13
|
|
|-
| 24
| E12
| B14
|
|
|-
| 25
| A12
| C11
|
|
|-
| 26
| B13
| C12
|
|
|-
| 27
| H13
| B16
|
|
|-
| 28
| G14
| B15
|
|
|-
| 29
| C14
| C13
|
|
|-
| 30
| F13
| C15
|
|
|-
| 31
| E14
| C14
|
| DACHEALTH See [[#Channel Descriptions | ADC Channel Descriptions]].
|}

==ADC==
The board includes an Analog Devices AD7928 analog to digital converter. The ADC is located just to the right and slightly below the FPGA. It is labelled U4.

===Power Details===
The ADC is powered by the +5V power island, which is regulated by an off-board power supply and decoupled near the ADC. It also requires a precise (±1%) 2.5V reference to which it compares voltages when converting from analog to digital. Since the +5V power source is not used for comparison, it is flexible and may vary by ±0.25V without affecting ADC precision.

===Setting the Measuring Range===
The measuring range is set programmatically by the FPGA over the SPI bus. The way the ADC is connected on the digital board requires that its measuring range be set to 5V, so the RANGE bit should be set to 1 by the FPGA (see Analog Devices documentation).

===Data Interfacing===
The ADC uses an SPI bus to communicate with the FPGA. This bus is shared with the temperature sensor. SPI related pins include SCLK, CS, DIN, and DOUT. See the Pinout Table below.

===Channel Descriptions===
This table shows what signals are monitored by the ADC.

{| cellpadding=3 border=1 |
| '''ADC Channel #'''
| '''ADC Pin #'''
| '''Net Name'''
| '''Description'''
|-
| VIN0
| 16
| AD7928/VHEALTH
| This net helps to monitor to overall health of power on the board, but is specifically intended to monitor -5V. It's voltage is the output of a resistor divider between the +5 and -5V power supplies, with resistor values of 33.2K, and 100K. Assuming +5V and -5V are both correct, the output of the divider will be +2.51V. A reading of other than 2.51V indicates a problem with one of the power supplies. Problems with the +5V power supply can be ruled out by reading VIN3. Based on the reading from VIN3, the voltage of the -5V supply can be calculated.
|-
| VIN1
| 15
| AD5535/CATHODE
| This is the thermal diode output from the DAC. Should read 4.35V (typical) at 25°C. Drops 2.20mV/°C.
|-
| VIN2
| 14
| +3.3V
| This is the +3.3V power plane. A reading of other than +3.3V indicates a problem with VR1.
|-
| VIN3
| 13
| +5V
| This is the +5V power island. A reading of other than +5V indicates a problem with the +5V power supply.
|-
| VIN4
| 12
| ADC_EXT1
| This trace routes to the backplane via Eurocard pin A7. It is intended to measure the output of thermistor on the amplifier board.
|-
| VIN5
| 11
| +1.2V
| This is the +1.2V power island. This island powers the internal logic of the FPGA. A reading of other than 1.2V indicates a problem with VR3.
|-
| VIN6
| 10
| ADC_EXT2
| This trace routes to the backplane via Eurocard pin A8. It is intended to measure one of the transistor base voltages on the amplifier board.
|-
| VIN7
| 9
| DACHEALTH
| This channel monitors the output of a resistor divider connected to channel 31 of the DAC. The divider consists of three resistors of 200K, 200K, and 10.2K (in order). The ADC reads out the voltage level between the second 200K and then 10.2K resistor. These resistors were selected so that at 200V, the readout voltage will be 4.973V. Since the divider should be linear, the expected voltage at 20V is 0.4973V. Three resistors were used rather than two to avoid exceeding the resistors' power ratings when the DAC is set to its maximum voltage. Note that since this divider will consume up to 484uA of current at 200V, this DAC channel should not be used for anything that might require more than ~200uA of current (the DAC can source 700uA max). The channel is routed to the backplane nonetheless.
|}

===Pinout Table===
{| cellpadding=3 border=1 |
| '''Pin #'''
| '''Net Name'''
| '''Description'''
|-
| 1
| CLK_5MHZ
| SPI clock (SCLK), from FPGA Shared with temperature sensor
|-
| 2
| DIN
| SPI data in, from FPGA Shared with temperature sensor ''Currently wired wrong''
|-
| 3
| CS
| SPI chip select
|-
| 4
| AGND
|
|-
| 5
| +5V
| Power pin
|-
| 6
| +5V
| Power pin
|-
| 7
| AD7928/REF_IN
| +2.5V reference, set by VR2
|-
| 8
| AGND
|
|-
| 9-16
| VIN[7:0]
| See [[#Channel Descriptions | ADC Channel Descriptions]]
|-
| 17
| AGND
|
|-
| 18
| DOUT
| SPI data out ''Currently wired incorrectly''
|-
| 19
| +3.3V
| VDRIVE, powers the SPI logic
|-
| 20
| AGND
|
|}

== Ethernet Controller ==
The board uses a Silicon Laboratories CP2201, 28-pin, ethernet controller. The CP2201 is located just above the FPGA, and is labelled U2.

=== Power Details ===
The CP2201 uses only +3.3V, which is supplied by the +3.3V power plane and regulated by VR1. Appropriate decoupling capacitors can be found near the CP2201.

=== Ethernet Jack ===
To the right of the CP2201 is a Pulse J0011D21NL ethernet jack, labelled J1. This jack has a built-in 1:1 inductive coupling. For best results, connect this jack to a nearby ethernet switch. The jack may also be connected directly to a computer using a crossover cable. Though auto-crossover is not supported by the CP2201, if the computer's NIC supports it, a crossover cable is not necessary to connect directly to a computer.

=== Crystal Oscillator ===
The CP2201 is responsible for driving the 20MHz crystal oscillator. This oscillator clocks both the CP2201 and the FPGA. The crystal oscillator can be found above the right corner of the FPGA. It can be identified by its four surface mount pads and roughly .3" length. It is labelled Y1, though this label is not visible after the oscillator is soldered on. The CP2201 uses an inverting driver to excite the crystal. The output of the crystal is then sent to the CP2201 and the FPGA.

=== Bus Format and Multiplexing ===
The 28-pin CP2201 used on the board only supports multiplexed operation. This means that both address and data information are passed over the same set of 8 traces. Hence, these traces are referred to as the address/data (AD) bus. A separate address line enable (ALE) trace prevents collisions from occuring on these traces. The communication protocol used is the Intel format. See the CP2201's datasheet for more information about this.

=== Pinout Table ===
{| cellpadding=3 border=1 |
| '''Pin #'''
| '''Net Name'''
| '''Description'''
|-
| 1
| CP2201/LA
| Link/activity indicator Routed to backplane but not implemented See CP2201 data sheet for information on how to connect to an LED
|-
| 2
| DGND
| By the data sheet, this pin should be AGND We deliberately set it to DGND to avoid noise on AGND plane
|-
| 3
| +3.3V
| AV+ power pin
|-
| 4
| CP2201/RX-
| Connects to RX- on ethernet jack
|-
| 5
| CP2201/RX+
| Connects to RX+ on ethernet jack
|-
| 6
| CP2201/TX+
| Connects to TX+ on ethernet jack
|-
| 7
| CP2201/TX-
| Connects to TX- on ethernet jack
|-
| 8
| +3.3V
| "VDD" power pin
|-
| 9
| DGND
| "DGND1" per the data sheet
|-
| 10
| CP2201/RESET
| "RST" per the data sheet Connects to FPGA - should be programmatically triggered upon reset of FPGA by RESET jumper
|-
| 11-18
| CP2201/AD[0:7]
| Bits 0-7 of the address/data bus Connect to FPGA
|-
| 19
| +3.3V
| "VDD" power pin
|-
| 20
| DGND
| "DGND2" per the data sheet
|-
| 21
| CP2201/ALE
| Address line enable Connects to FPGA See CP2201 documentation
|-
| 22
| CP2201/RD
| Read strobe for AD bus Connects to FPGA See CP2201 documentation
|-
| 23
| CP2201/WR
| Write strobe for AD bus Connects to FPGA See CP2201 documentation
|-
| 24
| CP2201/CS
| Chip select Connects to FPGA
|-
| 25
| CP2201/INT
| Interrupt request Connects to FPGA
|-
| 26
| DGND
| "MOTEN" (Motorola enable) per the datasheet Tied low to disable Motorola bus format (enable Intel format)
|-
| 27
| CP2201/XTAL2
| Crystal oscillator driver The CP2201 inverts the 20MHz clock signal and feeds it back to the crystal oscillator to encourage larger oscillations
|-
| 28
| FPGA/CLK_IN
| "XTAL1" per the data sheet This is the 20MHz clock input Also connects to the FPGA's clock input
|-
| 29*
| DGND
| This is not a pin but rather the base of the CP2201 package. It is connected to the DGND plane for thermal relief
|}

== Eurocard Connector ==
At the bottom of the control board is the Eurocard connector. The Eurocard connector connects the board to the backplane and also connects the board to its power supplies. The Eurocard has 48 pins arranged in three rows of 16 pins each. Rows B and C are exclusively used to pass SiPM bias voltages to the backplane as described in [[#Channel Mapping | DAC Channel Mapping]]. Here is a table describing the purpose of pins in row A:

=== Row A Pinout Table ===
Note that when viewing the top of the board with the Eurocard at the bottom, these pins go from right to left. If you look closely at the pins, you will see that pin A1 has a square pad, unlike the round pads of the others.

{| cellpadding=3 border=1 |
| '''Pin #'''
| '''Net Name'''
| '''Description'''
|-
| A1
| CP2201/LA
| Ethernet link/activity indicator routed to backplane
|-
| A2
| High voltage input (+210V max)
| High voltage input for DAC. See [[#DAC | DAC]] for information about what voltage to input here.
|-
| A3
| -5V
| For DAC
|-
| A4
| +5V
| Powers most things on the board
|-
| A5
| AGND
|
|-
| A6
| DGND
|
|-
| A7
| ADC_EXT1
| Connects to ADC to monitor voltages on amplifier board See [[#ADC | ADC]]
|-
| A8
| ADC_EXT2
| Connects to ADC to monitor voltages on amplifier board See [[#ADC | ADC]]
|-
| A9
| No connection
|
|-
| A10
| No connection
|
|-
| A11
| No conneciton
|
|-
| A12
| ID4
| Location identifier bit 4 Used to identify which backplane board is connected to See [[#FPGA | FPGA]]
|-
| A13
| ID3
| Location identifier bit 3 Used to identify which backplane board is connected to See [[#FPGA | FPGA]]
|-
| A14
| ID2
| Location identifier bit 2 Used to identify which backplane board is connected to See [[#FPGA | FPGA]]
|-
| A15
| ID1
| Location identifier bit 1 Used to identify which backplane board is connected to See [[#FPGA | FPGA]]
|-
| A16
| ID0
| Location identifier bit 0 Used to identify which backplane board is connected to See [[#FPGA | FPGA]]
|}

Digital control board documentation

2009-06-16T18:47:16Z

Underwood: eurocard start

This documentation covers the most important things to know while testing the digital control board, including component pinouts, nets, and other information.

== Power Requirements ==
=== Required Voltages ===
All components on the digital board '''except the DAC''' can be tested using only a +5V source. The DAC requires +5V, -5V, and a high voltage corresponding to 10V higher than the maximum desired DAC output voltage (see [[#Setting the Output Range | Setting the Output Range]]). Digital and analog grounds must be connected as well before any testing takes place.

=== Power Pins ===
Power shall be connected to the board as follows:
{| cellpadding=3 border=1 |
| '''Voltage'''
| '''Eurocard Pin'''
|-
| DGND
| A6
|-
| AGND
| A5
|-
| +5V
| A4
|-
| -5V
| A3
|-
| High voltage (DAC max out +10)
| A2
|}

=== Power Supply Sequencing ===
The control board is designed such that voltages may be supplied in any order so long as AGND and DGND are connected properly. However, for initial testing, the preferred order for powering up the board is as follows:

# Ensure AGND/DGND are connected/grounded
# +5V
# -5V
# High voltage

== FPGA ==
The control board uses a Xilinx XC3S50A VQ100 FPGA. It has a 100 pin footprint and is located in the center of the control board.

=== Power Details ===
The FPGA is powered by the 3.3V power plane, which is regulated by VR1. The FPGA also obtains 1.2V for its internal logic from a 1.2V power island, regulated by VR3.

=== Logic Standard ===
The Xilinx XC3S50A supports several different digital logic standards. The control board is hard wired such that the FPGA will use a '''3.3V CMOS''' logic standard.

=== Pinout Table ===
{| cellpadding=3 border=1 |
| '''Pin #'''
| '''Net Name'''
| '''Description'''
|-
| P1
| FPGA/TMS
| JTAG
|-
| P2
| FPGA/TDI
| JTAG
|-
| P3
| AD7928/CS
| SPI chip select for ADC
|-
| P4
| SPI
| '''Erroneously wired SPI bus trace''' Connects to SDO on temp. sensor and DIN on ADC
|-
| P5
| CLK_5MHZ
| 5 MHz clock output for SPI bus (ADC and temp. sensor)
|-
| P6
| No connection
|
|-
| P7
| No connection
|
|-
| P8
| DGND
|
|-
| P9
| No connection
|
|-
| P10
| No connection
|
|-
| P11
| +3.3V
|
|-
| P12
| No connection
|
|-
| P13
| No connection
|
|-
| P14
| DGND
|
|-
| P15
| No connection
|
|-
| P16
| No connection
|
|-
| P17
| +1.2V
|
|-
| P18
| DGND
|
|-
| P19
| No connection
|
|-
| P20
| No connection
|
|-
| P21
| No connection
|
|-
| P22
| +3.3V
|
|-
| P23
| DGND
|
|-
| P24
| DGND
|
|-
| P25
| DGND
|
|-
| P26
| +3.3V
|
|-
| P27
| FPGA/CLK_IN
| 20 MHz clock input from crystal oscillator
|-
| P28
| No connection
|
|-
| P29
| No connection
|
|-
| P30
| No connection
|
|-
| P31
| No connection
|
|-
| P32
| No connection
|
|-
| P33
| No connection
|
|-
| P34
| No connection
|
|-
| P35
| CP2201/INT
| Ethernet controller interrupt
|-
| P36
| MASTER_RESET
| Connects to RESET jumper in upper left of board (active-low, externally pulled up)
|-
| P37
| No connection
|
|-
| P38
| +1.2V
|
|-
| P39
| No connection
|
|-
| P40
| CP2201/CS
| Chip select for ethernet controller
|-
| P41
| CP2201/WR
| Write enable for ethernet controller
|-
| P42
| DGND
|
|-
| P43
| CP2201/RD
| Read enable for ethernet controller
|-
| P44
| CP2201/ALE
| Address line enable for ethernet controller
|-
| P45
| +3.3V
|
|-
| P46
| CP2201/RESET
| Reset pin for ethernet controller
|-
| P47
| DGND
|
|-
| P48
| FPGA/INIT_B
| Used during FPGA configuration - see Xilinx documentation
|-
| P49
| CP2201/AD0
| Ethernet controller address/data bus, bit 0
|-
| P50
| CP2201/AD1
| Ethernet controller address/data bus, bit 1
|-
| P51
| FPGA/DIN
| Serial data input from EEPROM for configuration
|-
| P52
| CP2201/AD2
| Ethernet controller address/data bus, bit 2
|-
| P53
| FPGA/CCLK
| Configuration clock (signal generated by FPGA at power on to clock the configuration process) See Xilinx documentation
|-
| P54
| FPGA/DONE
| Gives configuration status - see Xilinx documentation
|-
| P55
| +3.3V
|
|-
| P56
| CP2201/AD3
| Ethernet controller address/data bus, bit 3
|-
| P57
| CP2201/AD4
| Ethernet controller address/data bus, bit 4
|-
| P58
| DGND
|
|-
| P59
| CP2201/AD5
| Ethernet controller address/data bus, bit 5
|-
| P60
| CP2201/AD6
| Ethernet controller address/date bus, bit 6
|-
| P61
| CP2201/AD7
| Ethernet controller address/date bus, bit 7
|-
| P62
| No connection
|
|-
| P63
| DGND
|
|-
| P64
| No connection
|
|-
| P65
| No connection
|
|-
| P66
| +1.2V
|
|-
| P67
| +3.3V
|
|-
| P68
| +3.3V
|
|-
| P69
| DGND
|
|-
| P70
| ID3
| Backplane location identifier jumper, pins 3 & 4 Active-low, FPGA should pull high
|-
| P71
| ID2
| Backplane location identifier jumper, pins 5 & 6 Active-low, FPGA should pull high
|-
| P72
| ID1
| Backplane location identifier jumper, pins 7 & 8 Active-low, FPGA should pull high
|-
| P73
| ID0
| Backplane location identifier jumper, pins 9 & 10 Active-low, FPGA should pull high
|-
| P74
| DGND
|
|-
| P75
| FPGA/TDO
| JTAG
|-
| P76
| FPGA/TCK
| JTAG
|-
| P77
| ID4
| Backplane location identifier jumper, pins 1 & 2 Active-low, FPGA should pull high
|-
| P78
| No connection
|
|-
| P79
| +3.3V
|
|-
| P80
| DGND
|
|-
| P81
| +1.2V
|
|-
| P82
| No connection
|
|-
| P83
| CLK_5MHZ_2
| 5 MHz clock output for DAC
|-
| P84
| No connection
|
|-
| P85
| AD5535/DIN
| DAC serial data input (FPGA out -> DAC in)
|-
| P86
| No connection
|
|-
| P87
| DGND
|
|-
| P89
| No connection
|
|-
| P90
| No connection
|
|-
| P91
| DGND
|
|-
| P92
| +3.3V
|
|-
| P93
| AD7314/CE
| Chip enable for temperature sensor
|-
| P94
| No connection
|
|-
| P95
| DGND
|
|-
| P96
| +3.3V
|
|-
| P97
| AD7928/DOUT
| '''Erroneously wired ADC SPI bus connection''' Connects to DOUT on ADC
|-
| P98
| AD5535/RESET
| Reset pin for DAC
|-
| P99
| DGND
|
|-
| P100
| FPGA/PROG_B
| Used during FPGA configuration - see Xilinx documentation
|}

== EEPROM ==
To facilitate power-on configuration of the FPGA, the control board includes a Xilinx XCF01S EEPROM. The EEPROM is located to the left of the FPGA, above the JTAG header, and has a 20 pin footprint. The EEPROM is labelled U5.

=== Power Details ===
The EEPROM uses +3.3V exclusively, which it receives from the +3.3V power plane, regulated by VR1.

=== Flashing/Burning/Writing ===
Whatever you call it, this refers to storing data in the EEPROM so that it can configure the FPGA at power-on. The EEPROM is programmed using a JTAG interface and the Xilinx Platform USB II cable. It is important to note that in digital board's JTAG chain, the EEPROM is the first device in the chain, unlike in the Xilinx documentation where it is shown as the second device. This should not affect the operation of the board, but should be reflected in the Xilinx software when writing the EEPROM via JTAG.

=== FPGA Configuration ===
The EEPROM and FPGA are hardwired to use a master serial protocol to transfer the program from the EEPROM to the FPGA. This is the protocol recommended in the Xilinx documentation because it minimizes the number of traces necessary to run between the EEPROM and FPGA. All configuration data is sent over a single trace, FPGA/DIN (pin 1 on EEPROM), controlled by the configuration clock signal (FPGA/CCLK) which is automatically generated by the FPGA at power-on. When configuration is complete, FPGA/DONE (pin 10) is pulled high by the FPGA, and the EEPROM and configuration clock are deactivated.

=== Pinout Table ===
{| cellpadding=3 border=1 |
| '''Pin #'''
| '''Net Name'''
| '''Description'''
|-
| 1
| FPGA/DIN
| Serial data line Carries data from the EEPROM to the FPGA
|-
| 2
| No connection
|
|-
| 3
| FPGA/CCLK
| Configuration clock Auto generated by FPGA at power-on, disabled at end of configuration
|-
| 4
| EEPROM/TDI
| This is the EEPROM's TDI This is the entry point for the onboard JTAG chain
|-
| 5
| FPGA/TMS
| JTAG TMS Connects to both FPGA and EEPROM
|-
| 6
| FPGA/TCK
| JTAG TCK Connects to both FPGA and EEPROM
|-
| 7
| FPGA/PROG_B
| Used during configuration See Xilinx documentation
|-
| 8
| FPGA/INIT_B
| Used during configuration - can be used to intiate reconfiguration of FPGA See Xilinx documentation
|-
| 9
| No connection
|
|-
| 10
| FPGA/DONE
| Indicates completion of FPGA configuration High when complete
|-
| 11
| DGND
|
|-
| 12-16
| No connection
|
|-
| 17
| FPGA/TDI
| This is the EEPROM's TDO/FPGA's TDI
|-
| 18-20
| +3.3V
|
|}

== JTAG Header ==
To write the FPGA's program to the EEPROM, the board employs a JTAG based programming system consistent with Xilinx's recommendations. The system is designed to operate with Xilnx's Platform USB II cable and the flying lead adapter.

===Header Location and Size===
The header consists of 14 pins, 100 mil pitch, just below the EEPROM (U5). The header is labelled P1. The pitch of the pins in the header was erroneously selected to be 100 mil, which is not compatible with Xilinx's JTAG ribbon cable. Therefore, the Xilinx flying lead adapter must be used.

===Power Details===
The JTAG interface is powered by the +3.3V power plane, not by the computer's USB port. Power is supplied through pin 2 of the JTAG header.

===Pinout Table===
Note that the header is positioned on the board rotated 180 degrees from the position in which it is shown in the Xilinx documentation. Care must be taken when connecting the flying leads to ensure they are connected to the right pins. Connecting the flying leads to the wrong side of the header will cause all of the leads to short on the digital board's ground plane. This will certainly cause undesired operation, and may or may not cause damage. Improper wiring is most likely to cause damage if one of the flying leads is connected to an odd numbered pin. '''Note from the pinout table below that no flying lead connections should ever be made to the odd numbered pins on the JTAG header.'''

{| cellpadding=3 border=1 |
| '''Pin #'''
| '''Net Name'''
| '''Description'''
|-
| 1, 3, 5, 7, 9, 11, 13 (odd pins)
| DGND
| Ground pins for signal integrity '''Never connect a flying lead to these pins''' Doing so will short to ground and may cause permanent damage if the Platform USB II cable does not have protection against this.
|-
| 2
| +3.3V
| Power source for all JTAG logic
|-
| 4
| FPGA/TMS
| JTAG TMS - connects to EEPROM and FPGA
|-
| 6
| FPGA/TCK
| JTAG TCK - connects to EEPROM and FPGA
|-
| 8
| FPGA/TDO
| JTAG boundary scan chain endpoint
|-
| 10
| EEPROM/TDI
| JTAG boundary scan chain start point
|-
| 12
| No connection
| Pin is floating
|-
| 14
| No connection
| Pin is floating
|}

===JTAG Overview===
The JTAG interface is clocked by the TCK signal. TCK is generated by the Platform USB II cable, and connects directly from the JTAG header to both the EEPROM and FPGA.

The TMS signal is directly connected to both the EEPROM and FPGA, and is the data line over which JTAG test results (in this case programming results) are sent. TMS is used by only one component at a time.

The TDI/TDO lines form a chain that connects to each JTAG component in series. On the control board, the first point in the chain is the EEPROM's TDI. Next is the EEPROM's TDO, which is the same as the FPGA's TDI. The FPGA's TDO then returns to the JTAG header and the Platform USB II cable.

== DAC ==
The control board uses the Analog Devices AD5535, 32-channel, 200V max, digital to analog converter. This chip has a modified BC-124 BGA footprint and is located above the Eurocard connector at the bottom of the board. It is labelled U3.

=== Power Details ===
The DAC is primarily powered by the +5V power island, regulated by an off-board power supply and extensively decoupled in the area of the DAC. The DAC also requires -5V, and a high voltage as discussed in [[#Power Requirements | Power Requirements]]. Both of these voltages are supplied by an off-board supply and decoupled near the DAC. In addition to these voltage levels, the DAC requires a precise +2.5V reference, created by the shunt-type voltage reference VR4.

=== Setting the Output Range ===
The output range of the DAC is set by the 2.5V reference voltage supplied by VR4. The high voltage power supply must supply at a minimum 50 times this voltage, plus 10. Thus, the high voltage power supply should be at least 135V for DAC to operate properly, even though the SiPMs are expected to need only 40V. If it is convenient to use a lower high voltage, VR4 must be replaced to provide lower reference voltage. The high voltage may then be decreased appropriately. To summarize:

* Max output voltage = VREF*50
* Minimum high voltage supply = VREF*50 + 10
* Acceptable range for VREF
** Min: 1V
** Max: 3.75V (AD5535 datasheet specifies 4V max, but this would require AVCC of 5.25V for the DAC, which is not possible in the current board design)

If relevant, R13 is a 100K resistor.

=== Thermal Diode ===
The DAC has a built in thermal diode. The diode drop from anode to cathode is typically 0.65V at 25°C. It changes at a rate of -2.20mV/°C. The anode of this diode is connected to the +5V power island, and the cathode is connected to a 270K resistor to ground. The voltage between the cathode and the resistor is connected to VIN1 (pin 15) on the ADC.

=== Pinout Table ===
See documentation from Analog Devices.

=== Channel Mapping ===
Due to the layout of the balls on the footprint of the DAC, the DAC's internal channel numbers (which must be referenced by the FPGA) have no correlation to the channel numbers on the amplifier board. This table summarizes the mapping between various pins that belong to each channel.

{| cellpadding=3 border=1 |
| '''DAC Channel #'''
| '''DAC Pin #'''
| '''Digital Board Eurocard Pin #'''
| '''Amplifier Board Eurocard Pin #'''
| '''Physical Channel #'''
|-
| 0
| B1
| B3
|
|
|-
| 1
| A2
| C4
|
|
|-
| 2
| D1
| B2
|
|
|-
| 3
| C2
| C3
|
|
|-
| 4
| B3
| B4
|
|
|-
| 5
| E2
| C2
|
|
|-
| 6
| F3
| B1
|
|
|-
| 7
| A4
| B5
|
|
|-
| 8
| E4
| C5
|
|
|-
| 9
| B5
| C6
|
|
|-
| 10
| F5
| C1
|
|
|-
| 11
| A6
| C7
|
|
|-
| 12
| E6
| B6
|
|
|-
| 13
| B7
| B7
|
|
|-
| 14
| F7
| C10
|
|
|-
| 15
| E8
| C8
|
|
|-
| 16
| A8
| B8
|
|
|-
| 17
| B9
| C9
|
|
|-
| 18
| F9
| C16
|
|
|-
| 19
| E10
| B11
|
|
|-
| 20
| A10
| B9
|
|
|-
| 21
| B11
| B10
|
|
|-
| 22
| C12
| B12
|
|
|-
| 23
| D13
| B13
|
|
|-
| 24
| E12
| B14
|
|
|-
| 25
| A12
| C11
|
|
|-
| 26
| B13
| C12
|
|
|-
| 27
| H13
| B16
|
|
|-
| 28
| G14
| B15
|
|
|-
| 29
| C14
| C13
|
|
|-
| 30
| F13
| C15
|
|
|-
| 31
| E14
| C14
|
| DACHEALTH See [[#Channel Descriptions | ADC Channel Descriptions]].
|}

==ADC==
The board includes an Analog Devices AD7928 analog to digital converter. The ADC is located just to the right and slightly below the FPGA. It is labelled U4.

===Power Details===
The ADC is powered by the +5V power island, which is regulated by an off-board power supply and decoupled near the ADC. It also requires a precise (±1%) 2.5V reference to which it compares voltages when converting from analog to digital. Since the +5V power source is not used for comparison, it is flexible and may vary by ±0.25V without affecting ADC precision.

===Setting the Measuring Range===
The measuring range is set programmatically by the FPGA over the SPI bus. The way the ADC is connected on the digital board requires that its measuring range be set to 5V, so the RANGE bit should be set to 1 by the FPGA (see Analog Devices documentation).

===Data Interfacing===
The ADC uses an SPI bus to communicate with the FPGA. This bus is shared with the temperature sensor. SPI related pins include SCLK, CS, DIN, and DOUT. See the Pinout Table below.

===Channel Descriptions===
This table shows what signals are monitored by the ADC.

{| cellpadding=3 border=1 |
| '''ADC Channel #'''
| '''ADC Pin #'''
| '''Net Name'''
| '''Description'''
|-
| VIN0
| 16
| AD7928/VHEALTH
| This net helps to monitor to overall health of power on the board, but is specifically intended to monitor -5V. It's voltage is the output of a resistor divider between the +5 and -5V power supplies, with resistor values of 33.2K, and 100K. Assuming +5V and -5V are both correct, the output of the divider will be +2.51V. A reading of other than 2.51V indicates a problem with one of the power supplies. Problems with the +5V power supply can be ruled out by reading VIN3. Based on the reading from VIN3, the voltage of the -5V supply can be calculated.
|-
| VIN1
| 15
| AD5535/CATHODE
| This is the thermal diode output from the DAC. Should read 4.35V (typical) at 25°C. Drops 2.20mV/°C.
|-
| VIN2
| 14
| +3.3V
| This is the +3.3V power plane. A reading of other than +3.3V indicates a problem with VR1.
|-
| VIN3
| 13
| +5V
| This is the +5V power island. A reading of other than +5V indicates a problem with the +5V power supply.
|-
| VIN4
| 12
| ADC_EXT1
| This trace routes to the backplane via Eurocard pin A7. It is intended to measure the output of thermistor on the amplifier board.
|-
| VIN5
| 11
| +1.2V
| This is the +1.2V power island. This island powers the internal logic of the FPGA. A reading of other than 1.2V indicates a problem with VR3.
|-
| VIN6
| 10
| ADC_EXT2
| This trace routes to the backplane via Eurocard pin A8. It is intended to measure one of the transistor base voltages on the amplifier board.
|-
| VIN7
| 9
| DACHEALTH
| This channel monitors the output of a resistor divider connected to channel 31 of the DAC. The divider consists of three resistors of 200K, 200K, and 10.2K (in order). The ADC reads out the voltage level between the second 200K and then 10.2K resistor. These resistors were selected so that at 200V, the readout voltage will be 4.973V. Since the divider should be linear, the expected voltage at 20V is 0.4973V. Three resistors were used rather than two to avoid exceeding the resistors' power ratings when the DAC is set to its maximum voltage. Note that since this divider will consume up to 484uA of current at 200V, this DAC channel should not be used for anything that might require more than ~200uA of current (the DAC can source 700uA max). The channel is routed to the backplane nonetheless.
|}

===Pinout Table===
{| cellpadding=3 border=1 |
| '''Pin #'''
| '''Net Name'''
| '''Description'''
|-
| 1
| CLK_5MHZ
| SPI clock (SCLK), from FPGA Shared with temperature sensor
|-
| 2
| DIN
| SPI data in, from FPGA Shared with temperature sensor ''Currently wired wrong''
|-
| 3
| CS
| SPI chip select
|-
| 4
| AGND
|
|-
| 5
| +5V
| Power pin
|-
| 6
| +5V
| Power pin
|-
| 7
| AD7928/REF_IN
| +2.5V reference, set by VR2
|-
| 8
| AGND
|
|-
| 9-16
| VIN[7:0]
| See [[#Channel Descriptions | ADC Channel Descriptions]]
|-
| 17
| AGND
|
|-
| 18
| DOUT
| SPI data out ''Currently wired incorrectly''
|-
| 19
| +3.3V
| VDRIVE, powers the SPI logic
|-
| 20
| AGND
|
|}

== Ethernet Controller ==
The board uses a Silicon Laboratories CP2201, 28-pin, ethernet controller. The CP2201 is located just above the FPGA, and is labelled U2.

=== Power Details ===
The CP2201 uses only +3.3V, which is supplied by the +3.3V power plane and regulated by VR1. Appropriate decoupling capacitors can be found near the CP2201.

=== Ethernet Jack ===
To the right of the CP2201 is a Pulse J0011D21NL ethernet jack, labelled J1. This jack has a built-in 1:1 inductive coupling. For best results, connect this jack to a nearby ethernet switch. The jack may also be connected directly to a computer using a crossover cable. Though auto-crossover is not supported by the CP2201, if the computer's NIC supports it, a crossover cable is not necessary to connect directly to a computer.

=== Crystal Oscillator ===
The CP2201 is responsible for driving the 20MHz crystal oscillator. This oscillator clocks both the CP2201 and the FPGA. The crystal oscillator can be found above the right corner of the FPGA. It can be identified by its four surface mount pads and roughly .3" length. It is labelled Y1, though this label is not visible after the oscillator is soldered on. The CP2201 uses an inverting driver to excite the crystal. The output of the crystal is then sent to the CP2201 and the FPGA.

=== Bus Format and Multiplexing ===
The 28-pin CP2201 used on the board only supports multiplexed operation. This means that both address and data information are passed over the same set of 8 traces. Hence, these traces are referred to as the address/data (AD) bus. A separate address line enable (ALE) trace prevents collisions from occuring on these traces. The communication protocol used is the Intel format. See the CP2201's datasheet for more information about this.

=== Pinout Table ===
{| cellpadding=3 border=1 |
| '''Pin #'''
| '''Net Name'''
| '''Description'''
|-
| 1
| CP2201/LA
| Link/activity indicator Routed to backplane but not implemented See CP2201 data sheet for information on how to connect to an LED
|-
| 2
| DGND
| By the data sheet, this pin should be AGND We deliberately set it to DGND to avoid noise on AGND plane
|-
| 3
| +3.3V
| AV+ power pin
|-
| 4
| CP2201/RX-
| Connects to RX- on ethernet jack
|-
| 5
| CP2201/RX+
| Connects to RX+ on ethernet jack
|-
| 6
| CP2201/TX+
| Connects to TX+ on ethernet jack
|-
| 7
| CP2201/TX-
| Connects to TX- on ethernet jack
|-
| 8
| +3.3V
| "VDD" power pin
|-
| 9
| DGND
| "DGND1" per the data sheet
|-
| 10
| CP2201/RESET
| "RST" per the data sheet Connects to FPGA - should be programmatically triggered upon reset of FPGA by RESET jumper
|-
| 11-18
| CP2201/AD[0:7]
| Bits 0-7 of the address/data bus Connect to FPGA
|-
| 19
| +3.3V
| "VDD" power pin
|-
| 20
| DGND
| "DGND2" per the data sheet
|-
| 21
| CP2201/ALE
| Address line enable Connects to FPGA See CP2201 documentation
|-
| 22
| CP2201/RD
| Read strobe for AD bus Connects to FPGA See CP2201 documentation
|-
| 23
| CP2201/WR
| Write strobe for AD bus Connects to FPGA See CP2201 documentation
|-
| 24
| CP2201/CS
| Chip select Connects to FPGA
|-
| 25
| CP2201/INT
| Interrupt request Connects to FPGA
|-
| 26
| DGND
| "MOTEN" (Motorola enable) per the datasheet Tied low to disable Motorola bus format (enable Intel format)
|-
| 27
| CP2201/XTAL2
| Crystal oscillator driver The CP2201 inverts the 20MHz clock signal and feeds it back to the crystal oscillator to encourage larger oscillations
|-
| 28
| FPGA/CLK_IN
| "XTAL1" per the data sheet This is the 20MHz clock input Also connects to the FPGA's clock input
|-
| 29*
| DGND
| This is not a pin but rather the base of the CP2201 package. It is connected to the DGND plane for thermal relief
|}

== Eurocard Connector ==
At the bottom of the control board is the Eurocard connector. The Eurocard connector connects the board to the backplane and also connects the board to its power supplies. The Eurocard has 48 pins arranged in three rows of 16 pins each. Rows B and C are exclusively used to pass SiPM bias voltages to the backplane as described in

Digital control board documentation

2009-06-16T18:36:50Z

Underwood: /* Bus Format and Multiplexing */

This documentation covers the most important things to know while testing the digital control board, including component pinouts, nets, and other information.

== Power Requirements ==
=== Required Voltages ===
All components on the digital board '''except the DAC''' can be tested using only a +5V source. The DAC requires +5V, -5V, and a high voltage corresponding to 10V higher than the maximum desired DAC output voltage (see [[#Setting the Output Range | Setting the Output Range]]). Digital and analog grounds must be connected as well before any testing takes place.

=== Power Pins ===
Power shall be connected to the board as follows:
{| cellpadding=3 border=1 |
| '''Voltage'''
| '''Eurocard Pin'''
|-
| DGND
| A6
|-
| AGND
| A5
|-
| +5V
| A4
|-
| -5V
| A3
|-
| High voltage (DAC max out +10)
| A2
|}

=== Power Supply Sequencing ===
The control board is designed such that voltages may be supplied in any order so long as AGND and DGND are connected properly. However, for initial testing, the preferred order for powering up the board is as follows:

# Ensure AGND/DGND are connected/grounded
# +5V
# -5V
# High voltage

== FPGA ==
The control board uses a Xilinx XC3S50A VQ100 FPGA. It has a 100 pin footprint and is located in the center of the control board.

=== Power Details ===
The FPGA is powered by the 3.3V power plane, which is regulated by VR1. The FPGA also obtains 1.2V for its internal logic from a 1.2V power island, regulated by VR3.

=== Logic Standard ===
The Xilinx XC3S50A supports several different digital logic standards. The control board is hard wired such that the FPGA will use a '''3.3V CMOS''' logic standard.

=== Pinout Table ===
{| cellpadding=3 border=1 |
| '''Pin #'''
| '''Net Name'''
| '''Description'''
|-
| P1
| FPGA/TMS
| JTAG
|-
| P2
| FPGA/TDI
| JTAG
|-
| P3
| AD7928/CS
| SPI chip select for ADC
|-
| P4
| SPI
| '''Erroneously wired SPI bus trace''' Connects to SDO on temp. sensor and DIN on ADC
|-
| P5
| CLK_5MHZ
| 5 MHz clock output for SPI bus (ADC and temp. sensor)
|-
| P6
| No connection
|
|-
| P7
| No connection
|
|-
| P8
| DGND
|
|-
| P9
| No connection
|
|-
| P10
| No connection
|
|-
| P11
| +3.3V
|
|-
| P12
| No connection
|
|-
| P13
| No connection
|
|-
| P14
| DGND
|
|-
| P15
| No connection
|
|-
| P16
| No connection
|
|-
| P17
| +1.2V
|
|-
| P18
| DGND
|
|-
| P19
| No connection
|
|-
| P20
| No connection
|
|-
| P21
| No connection
|
|-
| P22
| +3.3V
|
|-
| P23
| DGND
|
|-
| P24
| DGND
|
|-
| P25
| DGND
|
|-
| P26
| +3.3V
|
|-
| P27
| FPGA/CLK_IN
| 20 MHz clock input from crystal oscillator
|-
| P28
| No connection
|
|-
| P29
| No connection
|
|-
| P30
| No connection
|
|-
| P31
| No connection
|
|-
| P32
| No connection
|
|-
| P33
| No connection
|
|-
| P34
| No connection
|
|-
| P35
| CP2201/INT
| Ethernet controller interrupt
|-
| P36
| MASTER_RESET
| Connects to RESET jumper in upper left of board (active-low, externally pulled up)
|-
| P37
| No connection
|
|-
| P38
| +1.2V
|
|-
| P39
| No connection
|
|-
| P40
| CP2201/CS
| Chip select for ethernet controller
|-
| P41
| CP2201/WR
| Write enable for ethernet controller
|-
| P42
| DGND
|
|-
| P43
| CP2201/RD
| Read enable for ethernet controller
|-
| P44
| CP2201/ALE
| Address line enable for ethernet controller
|-
| P45
| +3.3V
|
|-
| P46
| CP2201/RESET
| Reset pin for ethernet controller
|-
| P47
| DGND
|
|-
| P48
| FPGA/INIT_B
| Used during FPGA configuration - see Xilinx documentation
|-
| P49
| CP2201/AD0
| Ethernet controller address/data bus, bit 0
|-
| P50
| CP2201/AD1
| Ethernet controller address/data bus, bit 1
|-
| P51
| FPGA/DIN
| Serial data input from EEPROM for configuration
|-
| P52
| CP2201/AD2
| Ethernet controller address/data bus, bit 2
|-
| P53
| FPGA/CCLK
| Configuration clock (signal generated by FPGA at power on to clock the configuration process) See Xilinx documentation
|-
| P54
| FPGA/DONE
| Gives configuration status - see Xilinx documentation
|-
| P55
| +3.3V
|
|-
| P56
| CP2201/AD3
| Ethernet controller address/data bus, bit 3
|-
| P57
| CP2201/AD4
| Ethernet controller address/data bus, bit 4
|-
| P58
| DGND
|
|-
| P59
| CP2201/AD5
| Ethernet controller address/data bus, bit 5
|-
| P60
| CP2201/AD6
| Ethernet controller address/date bus, bit 6
|-
| P61
| CP2201/AD7
| Ethernet controller address/date bus, bit 7
|-
| P62
| No connection
|
|-
| P63
| DGND
|
|-
| P64
| No connection
|
|-
| P65
| No connection
|
|-
| P66
| +1.2V
|
|-
| P67
| +3.3V
|
|-
| P68
| +3.3V
|
|-
| P69
| DGND
|
|-
| P70
| ID3
| Backplane location identifier jumper, pins 3 & 4 Active-low, FPGA should pull high
|-
| P71
| ID2
| Backplane location identifier jumper, pins 5 & 6 Active-low, FPGA should pull high
|-
| P72
| ID1
| Backplane location identifier jumper, pins 7 & 8 Active-low, FPGA should pull high
|-
| P73
| ID0
| Backplane location identifier jumper, pins 9 & 10 Active-low, FPGA should pull high
|-
| P74
| DGND
|
|-
| P75
| FPGA/TDO
| JTAG
|-
| P76
| FPGA/TCK
| JTAG
|-
| P77
| ID4
| Backplane location identifier jumper, pins 1 & 2 Active-low, FPGA should pull high
|-
| P78
| No connection
|
|-
| P79
| +3.3V
|
|-
| P80
| DGND
|
|-
| P81
| +1.2V
|
|-
| P82
| No connection
|
|-
| P83
| CLK_5MHZ_2
| 5 MHz clock output for DAC
|-
| P84
| No connection
|
|-
| P85
| AD5535/DIN
| DAC serial data input (FPGA out -> DAC in)
|-
| P86
| No connection
|
|-
| P87
| DGND
|
|-
| P89
| No connection
|
|-
| P90
| No connection
|
|-
| P91
| DGND
|
|-
| P92
| +3.3V
|
|-
| P93
| AD7314/CE
| Chip enable for temperature sensor
|-
| P94
| No connection
|
|-
| P95
| DGND
|
|-
| P96
| +3.3V
|
|-
| P97
| AD7928/DOUT
| '''Erroneously wired ADC SPI bus connection''' Connects to DOUT on ADC
|-
| P98
| AD5535/RESET
| Reset pin for DAC
|-
| P99
| DGND
|
|-
| P100
| FPGA/PROG_B
| Used during FPGA configuration - see Xilinx documentation
|}

== EEPROM ==
To facilitate power-on configuration of the FPGA, the control board includes a Xilinx XCF01S EEPROM. The EEPROM is located to the left of the FPGA, above the JTAG header, and has a 20 pin footprint. The EEPROM is labelled U5.

=== Power Details ===
The EEPROM uses +3.3V exclusively, which it receives from the +3.3V power plane, regulated by VR1.

=== Flashing/Burning/Writing ===
Whatever you call it, this refers to storing data in the EEPROM so that it can configure the FPGA at power-on. The EEPROM is programmed using a JTAG interface and the Xilinx Platform USB II cable. It is important to note that in digital board's JTAG chain, the EEPROM is the first device in the chain, unlike in the Xilinx documentation where it is shown as the second device. This should not affect the operation of the board, but should be reflected in the Xilinx software when writing the EEPROM via JTAG.

=== FPGA Configuration ===
The EEPROM and FPGA are hardwired to use a master serial protocol to transfer the program from the EEPROM to the FPGA. This is the protocol recommended in the Xilinx documentation because it minimizes the number of traces necessary to run between the EEPROM and FPGA. All configuration data is sent over a single trace, FPGA/DIN (pin 1 on EEPROM), controlled by the configuration clock signal (FPGA/CCLK) which is automatically generated by the FPGA at power-on. When configuration is complete, FPGA/DONE (pin 10) is pulled high by the FPGA, and the EEPROM and configuration clock are deactivated.

=== Pinout Table ===
{| cellpadding=3 border=1 |
| '''Pin #'''
| '''Net Name'''
| '''Description'''
|-
| 1
| FPGA/DIN
| Serial data line Carries data from the EEPROM to the FPGA
|-
| 2
| No connection
|
|-
| 3
| FPGA/CCLK
| Configuration clock Auto generated by FPGA at power-on, disabled at end of configuration
|-
| 4
| EEPROM/TDI
| This is the EEPROM's TDI This is the entry point for the onboard JTAG chain
|-
| 5
| FPGA/TMS
| JTAG TMS Connects to both FPGA and EEPROM
|-
| 6
| FPGA/TCK
| JTAG TCK Connects to both FPGA and EEPROM
|-
| 7
| FPGA/PROG_B
| Used during configuration See Xilinx documentation
|-
| 8
| FPGA/INIT_B
| Used during configuration - can be used to intiate reconfiguration of FPGA See Xilinx documentation
|-
| 9
| No connection
|
|-
| 10
| FPGA/DONE
| Indicates completion of FPGA configuration High when complete
|-
| 11
| DGND
|
|-
| 12-16
| No connection
|
|-
| 17
| FPGA/TDI
| This is the EEPROM's TDO/FPGA's TDI
|-
| 18-20
| +3.3V
|
|}

== JTAG Header ==
To write the FPGA's program to the EEPROM, the board employs a JTAG based programming system consistent with Xilinx's recommendations. The system is designed to operate with Xilnx's Platform USB II cable and the flying lead adapter.

===Header Location and Size===
The header consists of 14 pins, 100 mil pitch, just below the EEPROM (U5). The header is labelled P1. The pitch of the pins in the header was erroneously selected to be 100 mil, which is not compatible with Xilinx's JTAG ribbon cable. Therefore, the Xilinx flying lead adapter must be used.

===Power Details===
The JTAG interface is powered by the +3.3V power plane, not by the computer's USB port. Power is supplied through pin 2 of the JTAG header.

===Pinout Table===
Note that the header is positioned on the board rotated 180 degrees from the position in which it is shown in the Xilinx documentation. Care must be taken when connecting the flying leads to ensure they are connected to the right pins. Connecting the flying leads to the wrong side of the header will cause all of the leads to short on the digital board's ground plane. This will certainly cause undesired operation, and may or may not cause damage. Improper wiring is most likely to cause damage if one of the flying leads is connected to an odd numbered pin. '''Note from the pinout table below that no flying lead connections should ever be made to the odd numbered pins on the JTAG header.'''

{| cellpadding=3 border=1 |
| '''Pin #'''
| '''Net Name'''
| '''Description'''
|-
| 1, 3, 5, 7, 9, 11, 13 (odd pins)
| DGND
| Ground pins for signal integrity '''Never connect a flying lead to these pins''' Doing so will short to ground and may cause permanent damage if the Platform USB II cable does not have protection against this.
|-
| 2
| +3.3V
| Power source for all JTAG logic
|-
| 4
| FPGA/TMS
| JTAG TMS - connects to EEPROM and FPGA
|-
| 6
| FPGA/TCK
| JTAG TCK - connects to EEPROM and FPGA
|-
| 8
| FPGA/TDO
| JTAG boundary scan chain endpoint
|-
| 10
| EEPROM/TDI
| JTAG boundary scan chain start point
|-
| 12
| No connection
| Pin is floating
|-
| 14
| No connection
| Pin is floating
|}

===JTAG Overview===
The JTAG interface is clocked by the TCK signal. TCK is generated by the Platform USB II cable, and connects directly from the JTAG header to both the EEPROM and FPGA.

The TMS signal is directly connected to both the EEPROM and FPGA, and is the data line over which JTAG test results (in this case programming results) are sent. TMS is used by only one component at a time.

The TDI/TDO lines form a chain that connects to each JTAG component in series. On the control board, the first point in the chain is the EEPROM's TDI. Next is the EEPROM's TDO, which is the same as the FPGA's TDI. The FPGA's TDO then returns to the JTAG header and the Platform USB II cable.

== DAC ==
The control board uses the Analog Devices AD5535, 32-channel, 200V max, digital to analog converter. This chip has a modified BC-124 BGA footprint and is located above the Eurocard connector at the bottom of the board. It is labelled U3.

=== Power Details ===
The DAC is primarily powered by the +5V power island, regulated by an off-board power supply and extensively decoupled in the area of the DAC. The DAC also requires -5V, and a high voltage as discussed in [[#Power Requirements | Power Requirements]]. Both of these voltages are supplied by an off-board supply and decoupled near the DAC. In addition to these voltage levels, the DAC requires a precise +2.5V reference, created by the shunt-type voltage reference VR4.

=== Setting the Output Range ===
The output range of the DAC is set by the 2.5V reference voltage supplied by VR4. The high voltage power supply must supply at a minimum 50 times this voltage, plus 10. Thus, the high voltage power supply should be at least 135V for DAC to operate properly, even though the SiPMs are expected to need only 40V. If it is convenient to use a lower high voltage, VR4 must be replaced to provide lower reference voltage. The high voltage may then be decreased appropriately. To summarize:

* Max output voltage = VREF*50
* Minimum high voltage supply = VREF*50 + 10
* Acceptable range for VREF
** Min: 1V
** Max: 3.75V (AD5535 datasheet specifies 4V max, but this would require AVCC of 5.25V for the DAC, which is not possible in the current board design)

If relevant, R13 is a 100K resistor.

=== Thermal Diode ===
The DAC has a built in thermal diode. The diode drop from anode to cathode is typically 0.65V at 25°C. It changes at a rate of -2.20mV/°C. The anode of this diode is connected to the +5V power island, and the cathode is connected to a 270K resistor to ground. The voltage between the cathode and the resistor is connected to VIN1 (pin 15) on the ADC.

=== Pinout Table ===
See documentation from Analog Devices.

=== Channel Mapping ===
Due to the layout of the balls on the footprint of the DAC, the DAC's internal channel numbers (which must be referenced by the FPGA) have no correlation to the channel numbers on the amplifier board. This table summarizes the mapping between various pins that belong to each channel.

{| cellpadding=3 border=1 |
| '''DAC Channel #'''
| '''DAC Pin #'''
| '''Digital Board Eurocard Pin #'''
| '''Amplifier Board Eurocard Pin #'''
| '''Physical Channel #'''
|-
| 0
| B1
| B3
|
|
|-
| 1
| A2
| C4
|
|
|-
| 2
| D1
| B2
|
|
|-
| 3
| C2
| C3
|
|
|-
| 4
| B3
| B4
|
|
|-
| 5
| E2
| C2
|
|
|-
| 6
| F3
| B1
|
|
|-
| 7
| A4
| B5
|
|
|-
| 8
| E4
| C5
|
|
|-
| 9
| B5
| C6
|
|
|-
| 10
| F5
| C1
|
|
|-
| 11
| A6
| C7
|
|
|-
| 12
| E6
| B6
|
|
|-
| 13
| B7
| B7
|
|
|-
| 14
| F7
| C10
|
|
|-
| 15
| E8
| C8
|
|
|-
| 16
| A8
| B8
|
|
|-
| 17
| B9
| C9
|
|
|-
| 18
| F9
| C16
|
|
|-
| 19
| E10
| B11
|
|
|-
| 20
| A10
| B9
|
|
|-
| 21
| B11
| B10
|
|
|-
| 22
| C12
| B12
|
|
|-
| 23
| D13
| B13
|
|
|-
| 24
| E12
| B14
|
|
|-
| 25
| A12
| C11
|
|
|-
| 26
| B13
| C12
|
|
|-
| 27
| H13
| B16
|
|
|-
| 28
| G14
| B15
|
|
|-
| 29
| C14
| C13
|
|
|-
| 30
| F13
| C15
|
|
|-
| 31
| E14
| C14
|
| DACHEALTH See [[#Channel Descriptions | ADC Channel Descriptions]].
|}

==ADC==
The board includes an Analog Devices AD7928 analog to digital converter. The ADC is located just to the right and slightly below the FPGA. It is labelled U4.

===Power Details===
The ADC is powered by the +5V power island, which is regulated by an off-board power supply and decoupled near the ADC. It also requires a precise (±1%) 2.5V reference to which it compares voltages when converting from analog to digital. Since the +5V power source is not used for comparison, it is flexible and may vary by ±0.25V without affecting ADC precision.

===Setting the Measuring Range===
The measuring range is set programmatically by the FPGA over the SPI bus. The way the ADC is connected on the digital board requires that its measuring range be set to 5V, so the RANGE bit should be set to 1 by the FPGA (see Analog Devices documentation).

===Data Interfacing===
The ADC uses an SPI bus to communicate with the FPGA. This bus is shared with the temperature sensor. SPI related pins include SCLK, CS, DIN, and DOUT. See the Pinout Table below.

===Channel Descriptions===
This table shows what signals are monitored by the ADC.

{| cellpadding=3 border=1 |
| '''ADC Channel #'''
| '''ADC Pin #'''
| '''Net Name'''
| '''Description'''
|-
| VIN0
| 16
| AD7928/VHEALTH
| This net helps to monitor to overall health of power on the board, but is specifically intended to monitor -5V. It's voltage is the output of a resistor divider between the +5 and -5V power supplies, with resistor values of 33.2K, and 100K. Assuming +5V and -5V are both correct, the output of the divider will be +2.51V. A reading of other than 2.51V indicates a problem with one of the power supplies. Problems with the +5V power supply can be ruled out by reading VIN3. Based on the reading from VIN3, the voltage of the -5V supply can be calculated.
|-
| VIN1
| 15
| AD5535/CATHODE
| This is the thermal diode output from the DAC. Should read 4.35V (typical) at 25°C. Drops 2.20mV/°C.
|-
| VIN2
| 14
| +3.3V
| This is the +3.3V power plane. A reading of other than +3.3V indicates a problem with VR1.
|-
| VIN3
| 13
| +5V
| This is the +5V power island. A reading of other than +5V indicates a problem with the +5V power supply.
|-
| VIN4
| 12
| ADC_EXT1
| This trace routes to the backplane via Eurocard pin A7. It is intended to measure the output of thermistor on the amplifier board.
|-
| VIN5
| 11
| +1.2V
| This is the +1.2V power island. This island powers the internal logic of the FPGA. A reading of other than 1.2V indicates a problem with VR3.
|-
| VIN6
| 10
| ADC_EXT2
| This trace routes to the backplane via Eurocard pin A8. It is intended to measure one of the transistor base voltages on the amplifier board.
|-
| VIN7
| 9
| DACHEALTH
| This channel monitors the output of a resistor divider connected to channel 31 of the DAC. The divider consists of three resistors of 200K, 200K, and 10.2K (in order). The ADC reads out the voltage level between the second 200K and then 10.2K resistor. These resistors were selected so that at 200V, the readout voltage will be 4.973V. Since the divider should be linear, the expected voltage at 20V is 0.4973V. Three resistors were used rather than two to avoid exceeding the resistors' power ratings when the DAC is set to its maximum voltage. Note that since this divider will consume up to 484uA of current at 200V, this DAC channel should not be used for anything that might require more than ~200uA of current (the DAC can source 700uA max). The channel is routed to the backplane nonetheless.
|}

===Pinout Table===
{| cellpadding=3 border=1 |
| '''Pin #'''
| '''Net Name'''
| '''Description'''
|-
| 1
| CLK_5MHZ
| SPI clock (SCLK), from FPGA Shared with temperature sensor
|-
| 2
| DIN
| SPI data in, from FPGA Shared with temperature sensor ''Currently wired wrong''
|-
| 3
| CS
| SPI chip select
|-
| 4
| AGND
|
|-
| 5
| +5V
| Power pin
|-
| 6
| +5V
| Power pin
|-
| 7
| AD7928/REF_IN
| +2.5V reference, set by VR2
|-
| 8
| AGND
|
|-
| 9-16
| VIN[7:0]
| See [[#Channel Descriptions | ADC Channel Descriptions]]
|-
| 17
| AGND
|
|-
| 18
| DOUT
| SPI data out ''Currently wired incorrectly''
|-
| 19
| +3.3V
| VDRIVE, powers the SPI logic
|-
| 20
| AGND
|
|}

== Ethernet Controller ==
The board uses a Silicon Laboratories CP2201, 28-pin, ethernet controller. The CP2201 is located just above the FPGA, and is labelled U2.

=== Power Details ===
The CP2201 uses only +3.3V, which is supplied by the +3.3V power plane and regulated by VR1. Appropriate decoupling capacitors can be found near the CP2201.

=== Ethernet Jack ===
To the right of the CP2201 is a Pulse J0011D21NL ethernet jack, labelled J1. This jack has a built-in 1:1 inductive coupling. For best results, connect this jack to a nearby ethernet switch. The jack may also be connected directly to a computer using a crossover cable. Though auto-crossover is not supported by the CP2201, if the computer's NIC supports it, a crossover cable is not necessary to connect directly to a computer.

=== Crystal Oscillator ===
The CP2201 is responsible for driving the 20MHz crystal oscillator. This oscillator clocks both the CP2201 and the FPGA. The crystal oscillator can be found above the right corner of the FPGA. It can be identified by its four surface mount pads and roughly .3" length. It is labelled Y1, though this label is not visible after the oscillator is soldered on. The CP2201 uses an inverting driver to excite the crystal. The output of the crystal is then sent to the CP2201 and the FPGA.

=== Bus Format and Multiplexing ===
The 28-pin CP2201 used on the board only supports multiplexed operation. This means that both address and data information are passed over the same set of 8 traces. Hence, these traces are referred to as the address/data (AD) bus. A separate address line enable (ALE) trace prevents collisions from occuring on these traces. The communication protocol used is the Intel format. See the CP2201's datasheet for more information about this.

=== Pinout Table ===
{| cellpadding=3 border=1 |
| '''Pin #'''
| '''Net Name'''
| '''Description'''
|-
| 1
| CP2201/LA
| Link/activity indicator Routed to backplane but not implemented See CP2201 data sheet for information on how to connect to an LED
|-
| 2
| DGND
| By the data sheet, this pin should be AGND We deliberately set it to DGND to avoid noise on AGND plane
|-
| 3
| +3.3V
| AV+ power pin
|-
| 4
| CP2201/RX-
| Connects to RX- on ethernet jack
|-
| 5
| CP2201/RX+
| Connects to RX+ on ethernet jack
|-
| 6
| CP2201/TX+
| Connects to TX+ on ethernet jack
|-
| 7
| CP2201/TX-
| Connects to TX- on ethernet jack
|-
| 8
| +3.3V
| "VDD" power pin
|-
| 9
| DGND
| "DGND1" per the data sheet
|-
| 10
| CP2201/RESET
| "RST" per the data sheet Connects to FPGA - should be programmatically triggered upon reset of FPGA by RESET jumper
|-
| 11-18
| CP2201/AD[0:7]
| Bits 0-7 of the address/data bus Connect to FPGA
|-
| 19
| +3.3V
| "VDD" power pin
|-
| 20
| DGND
| "DGND2" per the data sheet
|-
| 21
| CP2201/ALE
| Address line enable Connects to FPGA See CP2201 documentation
|-
| 22
| CP2201/RD
| Read strobe for AD bus Connects to FPGA See CP2201 documentation
|-
| 23
| CP2201/WR
| Write strobe for AD bus Connects to FPGA See CP2201 documentation
|-
| 24
| CP2201/CS
| Chip select Connects to FPGA
|-
| 25
| CP2201/INT
| Interrupt request Connects to FPGA
|-
| 26
| DGND
| "MOTEN" (Motorola enable) per the datasheet Tied low to disable Motorola bus format (enable Intel format)
|-
| 27
| CP2201/XTAL2
| Crystal oscillator driver The CP2201 inverts the 20MHz clock signal and feeds it back to the crystal oscillator to encourage larger oscillations
|-
| 28
| FPGA/CLK_IN
| "XTAL1" per the data sheet This is the 20MHz clock input Also connects to the FPGA's clock input
|-
| 29*
| DGND
| This is not a pin but rather the base of the CP2201 package. It is connected to the DGND plane for thermal relief
|}

Digital control board documentation

2009-06-16T18:36:11Z

Underwood: /* Pinout Table */

This documentation covers the most important things to know while testing the digital control board, including component pinouts, nets, and other information.

== Power Requirements ==
=== Required Voltages ===
All components on the digital board '''except the DAC''' can be tested using only a +5V source. The DAC requires +5V, -5V, and a high voltage corresponding to 10V higher than the maximum desired DAC output voltage (see [[#Setting the Output Range | Setting the Output Range]]). Digital and analog grounds must be connected as well before any testing takes place.

=== Power Pins ===
Power shall be connected to the board as follows:
{| cellpadding=3 border=1 |
| '''Voltage'''
| '''Eurocard Pin'''
|-
| DGND
| A6
|-
| AGND
| A5
|-
| +5V
| A4
|-
| -5V
| A3
|-
| High voltage (DAC max out +10)
| A2
|}

=== Power Supply Sequencing ===
The control board is designed such that voltages may be supplied in any order so long as AGND and DGND are connected properly. However, for initial testing, the preferred order for powering up the board is as follows:

# Ensure AGND/DGND are connected/grounded
# +5V
# -5V
# High voltage

== FPGA ==
The control board uses a Xilinx XC3S50A VQ100 FPGA. It has a 100 pin footprint and is located in the center of the control board.

=== Power Details ===
The FPGA is powered by the 3.3V power plane, which is regulated by VR1. The FPGA also obtains 1.2V for its internal logic from a 1.2V power island, regulated by VR3.

=== Logic Standard ===
The Xilinx XC3S50A supports several different digital logic standards. The control board is hard wired such that the FPGA will use a '''3.3V CMOS''' logic standard.

=== Pinout Table ===
{| cellpadding=3 border=1 |
| '''Pin #'''
| '''Net Name'''
| '''Description'''
|-
| P1
| FPGA/TMS
| JTAG
|-
| P2
| FPGA/TDI
| JTAG
|-
| P3
| AD7928/CS
| SPI chip select for ADC
|-
| P4
| SPI
| '''Erroneously wired SPI bus trace''' Connects to SDO on temp. sensor and DIN on ADC
|-
| P5
| CLK_5MHZ
| 5 MHz clock output for SPI bus (ADC and temp. sensor)
|-
| P6
| No connection
|
|-
| P7
| No connection
|
|-
| P8
| DGND
|
|-
| P9
| No connection
|
|-
| P10
| No connection
|
|-
| P11
| +3.3V
|
|-
| P12
| No connection
|
|-
| P13
| No connection
|
|-
| P14
| DGND
|
|-
| P15
| No connection
|
|-
| P16
| No connection
|
|-
| P17
| +1.2V
|
|-
| P18
| DGND
|
|-
| P19
| No connection
|
|-
| P20
| No connection
|
|-
| P21
| No connection
|
|-
| P22
| +3.3V
|
|-
| P23
| DGND
|
|-
| P24
| DGND
|
|-
| P25
| DGND
|
|-
| P26
| +3.3V
|
|-
| P27
| FPGA/CLK_IN
| 20 MHz clock input from crystal oscillator
|-
| P28
| No connection
|
|-
| P29
| No connection
|
|-
| P30
| No connection
|
|-
| P31
| No connection
|
|-
| P32
| No connection
|
|-
| P33
| No connection
|
|-
| P34
| No connection
|
|-
| P35
| CP2201/INT
| Ethernet controller interrupt
|-
| P36
| MASTER_RESET
| Connects to RESET jumper in upper left of board (active-low, externally pulled up)
|-
| P37
| No connection
|
|-
| P38
| +1.2V
|
|-
| P39
| No connection
|
|-
| P40
| CP2201/CS
| Chip select for ethernet controller
|-
| P41
| CP2201/WR
| Write enable for ethernet controller
|-
| P42
| DGND
|
|-
| P43
| CP2201/RD
| Read enable for ethernet controller
|-
| P44
| CP2201/ALE
| Address line enable for ethernet controller
|-
| P45
| +3.3V
|
|-
| P46
| CP2201/RESET
| Reset pin for ethernet controller
|-
| P47
| DGND
|
|-
| P48
| FPGA/INIT_B
| Used during FPGA configuration - see Xilinx documentation
|-
| P49
| CP2201/AD0
| Ethernet controller address/data bus, bit 0
|-
| P50
| CP2201/AD1
| Ethernet controller address/data bus, bit 1
|-
| P51
| FPGA/DIN
| Serial data input from EEPROM for configuration
|-
| P52
| CP2201/AD2
| Ethernet controller address/data bus, bit 2
|-
| P53
| FPGA/CCLK
| Configuration clock (signal generated by FPGA at power on to clock the configuration process) See Xilinx documentation
|-
| P54
| FPGA/DONE
| Gives configuration status - see Xilinx documentation
|-
| P55
| +3.3V
|
|-
| P56
| CP2201/AD3
| Ethernet controller address/data bus, bit 3
|-
| P57
| CP2201/AD4
| Ethernet controller address/data bus, bit 4
|-
| P58
| DGND
|
|-
| P59
| CP2201/AD5
| Ethernet controller address/data bus, bit 5
|-
| P60
| CP2201/AD6
| Ethernet controller address/date bus, bit 6
|-
| P61
| CP2201/AD7
| Ethernet controller address/date bus, bit 7
|-
| P62
| No connection
|
|-
| P63
| DGND
|
|-
| P64
| No connection
|
|-
| P65
| No connection
|
|-
| P66
| +1.2V
|
|-
| P67
| +3.3V
|
|-
| P68
| +3.3V
|
|-
| P69
| DGND
|
|-
| P70
| ID3
| Backplane location identifier jumper, pins 3 & 4 Active-low, FPGA should pull high
|-
| P71
| ID2
| Backplane location identifier jumper, pins 5 & 6 Active-low, FPGA should pull high
|-
| P72
| ID1
| Backplane location identifier jumper, pins 7 & 8 Active-low, FPGA should pull high
|-
| P73
| ID0
| Backplane location identifier jumper, pins 9 & 10 Active-low, FPGA should pull high
|-
| P74
| DGND
|
|-
| P75
| FPGA/TDO
| JTAG
|-
| P76
| FPGA/TCK
| JTAG
|-
| P77
| ID4
| Backplane location identifier jumper, pins 1 & 2 Active-low, FPGA should pull high
|-
| P78
| No connection
|
|-
| P79
| +3.3V
|
|-
| P80
| DGND
|
|-
| P81
| +1.2V
|
|-
| P82
| No connection
|
|-
| P83
| CLK_5MHZ_2
| 5 MHz clock output for DAC
|-
| P84
| No connection
|
|-
| P85
| AD5535/DIN
| DAC serial data input (FPGA out -> DAC in)
|-
| P86
| No connection
|
|-
| P87
| DGND
|
|-
| P89
| No connection
|
|-
| P90
| No connection
|
|-
| P91
| DGND
|
|-
| P92
| +3.3V
|
|-
| P93
| AD7314/CE
| Chip enable for temperature sensor
|-
| P94
| No connection
|
|-
| P95
| DGND
|
|-
| P96
| +3.3V
|
|-
| P97
| AD7928/DOUT
| '''Erroneously wired ADC SPI bus connection''' Connects to DOUT on ADC
|-
| P98
| AD5535/RESET
| Reset pin for DAC
|-
| P99
| DGND
|
|-
| P100
| FPGA/PROG_B
| Used during FPGA configuration - see Xilinx documentation
|}

== EEPROM ==
To facilitate power-on configuration of the FPGA, the control board includes a Xilinx XCF01S EEPROM. The EEPROM is located to the left of the FPGA, above the JTAG header, and has a 20 pin footprint. The EEPROM is labelled U5.

=== Power Details ===
The EEPROM uses +3.3V exclusively, which it receives from the +3.3V power plane, regulated by VR1.

=== Flashing/Burning/Writing ===
Whatever you call it, this refers to storing data in the EEPROM so that it can configure the FPGA at power-on. The EEPROM is programmed using a JTAG interface and the Xilinx Platform USB II cable. It is important to note that in digital board's JTAG chain, the EEPROM is the first device in the chain, unlike in the Xilinx documentation where it is shown as the second device. This should not affect the operation of the board, but should be reflected in the Xilinx software when writing the EEPROM via JTAG.

=== FPGA Configuration ===
The EEPROM and FPGA are hardwired to use a master serial protocol to transfer the program from the EEPROM to the FPGA. This is the protocol recommended in the Xilinx documentation because it minimizes the number of traces necessary to run between the EEPROM and FPGA. All configuration data is sent over a single trace, FPGA/DIN (pin 1 on EEPROM), controlled by the configuration clock signal (FPGA/CCLK) which is automatically generated by the FPGA at power-on. When configuration is complete, FPGA/DONE (pin 10) is pulled high by the FPGA, and the EEPROM and configuration clock are deactivated.

=== Pinout Table ===
{| cellpadding=3 border=1 |
| '''Pin #'''
| '''Net Name'''
| '''Description'''
|-
| 1
| FPGA/DIN
| Serial data line Carries data from the EEPROM to the FPGA
|-
| 2
| No connection
|
|-
| 3
| FPGA/CCLK
| Configuration clock Auto generated by FPGA at power-on, disabled at end of configuration
|-
| 4
| EEPROM/TDI
| This is the EEPROM's TDI This is the entry point for the onboard JTAG chain
|-
| 5
| FPGA/TMS
| JTAG TMS Connects to both FPGA and EEPROM
|-
| 6
| FPGA/TCK
| JTAG TCK Connects to both FPGA and EEPROM
|-
| 7
| FPGA/PROG_B
| Used during configuration See Xilinx documentation
|-
| 8
| FPGA/INIT_B
| Used during configuration - can be used to intiate reconfiguration of FPGA See Xilinx documentation
|-
| 9
| No connection
|
|-
| 10
| FPGA/DONE
| Indicates completion of FPGA configuration High when complete
|-
| 11
| DGND
|
|-
| 12-16
| No connection
|
|-
| 17
| FPGA/TDI
| This is the EEPROM's TDO/FPGA's TDI
|-
| 18-20
| +3.3V
|
|}

== JTAG Header ==
To write the FPGA's program to the EEPROM, the board employs a JTAG based programming system consistent with Xilinx's recommendations. The system is designed to operate with Xilnx's Platform USB II cable and the flying lead adapter.

===Header Location and Size===
The header consists of 14 pins, 100 mil pitch, just below the EEPROM (U5). The header is labelled P1. The pitch of the pins in the header was erroneously selected to be 100 mil, which is not compatible with Xilinx's JTAG ribbon cable. Therefore, the Xilinx flying lead adapter must be used.

===Power Details===
The JTAG interface is powered by the +3.3V power plane, not by the computer's USB port. Power is supplied through pin 2 of the JTAG header.

===Pinout Table===
Note that the header is positioned on the board rotated 180 degrees from the position in which it is shown in the Xilinx documentation. Care must be taken when connecting the flying leads to ensure they are connected to the right pins. Connecting the flying leads to the wrong side of the header will cause all of the leads to short on the digital board's ground plane. This will certainly cause undesired operation, and may or may not cause damage. Improper wiring is most likely to cause damage if one of the flying leads is connected to an odd numbered pin. '''Note from the pinout table below that no flying lead connections should ever be made to the odd numbered pins on the JTAG header.'''

{| cellpadding=3 border=1 |
| '''Pin #'''
| '''Net Name'''
| '''Description'''
|-
| 1, 3, 5, 7, 9, 11, 13 (odd pins)
| DGND
| Ground pins for signal integrity '''Never connect a flying lead to these pins''' Doing so will short to ground and may cause permanent damage if the Platform USB II cable does not have protection against this.
|-
| 2
| +3.3V
| Power source for all JTAG logic
|-
| 4
| FPGA/TMS
| JTAG TMS - connects to EEPROM and FPGA
|-
| 6
| FPGA/TCK
| JTAG TCK - connects to EEPROM and FPGA
|-
| 8
| FPGA/TDO
| JTAG boundary scan chain endpoint
|-
| 10
| EEPROM/TDI
| JTAG boundary scan chain start point
|-
| 12
| No connection
| Pin is floating
|-
| 14
| No connection
| Pin is floating
|}

===JTAG Overview===
The JTAG interface is clocked by the TCK signal. TCK is generated by the Platform USB II cable, and connects directly from the JTAG header to both the EEPROM and FPGA.

The TMS signal is directly connected to both the EEPROM and FPGA, and is the data line over which JTAG test results (in this case programming results) are sent. TMS is used by only one component at a time.

The TDI/TDO lines form a chain that connects to each JTAG component in series. On the control board, the first point in the chain is the EEPROM's TDI. Next is the EEPROM's TDO, which is the same as the FPGA's TDI. The FPGA's TDO then returns to the JTAG header and the Platform USB II cable.

== DAC ==
The control board uses the Analog Devices AD5535, 32-channel, 200V max, digital to analog converter. This chip has a modified BC-124 BGA footprint and is located above the Eurocard connector at the bottom of the board. It is labelled U3.

=== Power Details ===
The DAC is primarily powered by the +5V power island, regulated by an off-board power supply and extensively decoupled in the area of the DAC. The DAC also requires -5V, and a high voltage as discussed in [[#Power Requirements | Power Requirements]]. Both of these voltages are supplied by an off-board supply and decoupled near the DAC. In addition to these voltage levels, the DAC requires a precise +2.5V reference, created by the shunt-type voltage reference VR4.

=== Setting the Output Range ===
The output range of the DAC is set by the 2.5V reference voltage supplied by VR4. The high voltage power supply must supply at a minimum 50 times this voltage, plus 10. Thus, the high voltage power supply should be at least 135V for DAC to operate properly, even though the SiPMs are expected to need only 40V. If it is convenient to use a lower high voltage, VR4 must be replaced to provide lower reference voltage. The high voltage may then be decreased appropriately. To summarize:

* Max output voltage = VREF*50
* Minimum high voltage supply = VREF*50 + 10
* Acceptable range for VREF
** Min: 1V
** Max: 3.75V (AD5535 datasheet specifies 4V max, but this would require AVCC of 5.25V for the DAC, which is not possible in the current board design)

If relevant, R13 is a 100K resistor.

=== Thermal Diode ===
The DAC has a built in thermal diode. The diode drop from anode to cathode is typically 0.65V at 25°C. It changes at a rate of -2.20mV/°C. The anode of this diode is connected to the +5V power island, and the cathode is connected to a 270K resistor to ground. The voltage between the cathode and the resistor is connected to VIN1 (pin 15) on the ADC.

=== Pinout Table ===
See documentation from Analog Devices.

=== Channel Mapping ===
Due to the layout of the balls on the footprint of the DAC, the DAC's internal channel numbers (which must be referenced by the FPGA) have no correlation to the channel numbers on the amplifier board. This table summarizes the mapping between various pins that belong to each channel.

{| cellpadding=3 border=1 |
| '''DAC Channel #'''
| '''DAC Pin #'''
| '''Digital Board Eurocard Pin #'''
| '''Amplifier Board Eurocard Pin #'''
| '''Physical Channel #'''
|-
| 0
| B1
| B3
|
|
|-
| 1
| A2
| C4
|
|
|-
| 2
| D1
| B2
|
|
|-
| 3
| C2
| C3
|
|
|-
| 4
| B3
| B4
|
|
|-
| 5
| E2
| C2
|
|
|-
| 6
| F3
| B1
|
|
|-
| 7
| A4
| B5
|
|
|-
| 8
| E4
| C5
|
|
|-
| 9
| B5
| C6
|
|
|-
| 10
| F5
| C1
|
|
|-
| 11
| A6
| C7
|
|
|-
| 12
| E6
| B6
|
|
|-
| 13
| B7
| B7
|
|
|-
| 14
| F7
| C10
|
|
|-
| 15
| E8
| C8
|
|
|-
| 16
| A8
| B8
|
|
|-
| 17
| B9
| C9
|
|
|-
| 18
| F9
| C16
|
|
|-
| 19
| E10
| B11
|
|
|-
| 20
| A10
| B9
|
|
|-
| 21
| B11
| B10
|
|
|-
| 22
| C12
| B12
|
|
|-
| 23
| D13
| B13
|
|
|-
| 24
| E12
| B14
|
|
|-
| 25
| A12
| C11
|
|
|-
| 26
| B13
| C12
|
|
|-
| 27
| H13
| B16
|
|
|-
| 28
| G14
| B15
|
|
|-
| 29
| C14
| C13
|
|
|-
| 30
| F13
| C15
|
|
|-
| 31
| E14
| C14
|
| DACHEALTH See [[#Channel Descriptions | ADC Channel Descriptions]].
|}

==ADC==
The board includes an Analog Devices AD7928 analog to digital converter. The ADC is located just to the right and slightly below the FPGA. It is labelled U4.

===Power Details===
The ADC is powered by the +5V power island, which is regulated by an off-board power supply and decoupled near the ADC. It also requires a precise (±1%) 2.5V reference to which it compares voltages when converting from analog to digital. Since the +5V power source is not used for comparison, it is flexible and may vary by ±0.25V without affecting ADC precision.

===Setting the Measuring Range===
The measuring range is set programmatically by the FPGA over the SPI bus. The way the ADC is connected on the digital board requires that its measuring range be set to 5V, so the RANGE bit should be set to 1 by the FPGA (see Analog Devices documentation).

===Data Interfacing===
The ADC uses an SPI bus to communicate with the FPGA. This bus is shared with the temperature sensor. SPI related pins include SCLK, CS, DIN, and DOUT. See the Pinout Table below.

===Channel Descriptions===
This table shows what signals are monitored by the ADC.

{| cellpadding=3 border=1 |
| '''ADC Channel #'''
| '''ADC Pin #'''
| '''Net Name'''
| '''Description'''
|-
| VIN0
| 16
| AD7928/VHEALTH
| This net helps to monitor to overall health of power on the board, but is specifically intended to monitor -5V. It's voltage is the output of a resistor divider between the +5 and -5V power supplies, with resistor values of 33.2K, and 100K. Assuming +5V and -5V are both correct, the output of the divider will be +2.51V. A reading of other than 2.51V indicates a problem with one of the power supplies. Problems with the +5V power supply can be ruled out by reading VIN3. Based on the reading from VIN3, the voltage of the -5V supply can be calculated.
|-
| VIN1
| 15
| AD5535/CATHODE
| This is the thermal diode output from the DAC. Should read 4.35V (typical) at 25°C. Drops 2.20mV/°C.
|-
| VIN2
| 14
| +3.3V
| This is the +3.3V power plane. A reading of other than +3.3V indicates a problem with VR1.
|-
| VIN3
| 13
| +5V
| This is the +5V power island. A reading of other than +5V indicates a problem with the +5V power supply.
|-
| VIN4
| 12
| ADC_EXT1
| This trace routes to the backplane via Eurocard pin A7. It is intended to measure the output of thermistor on the amplifier board.
|-
| VIN5
| 11
| +1.2V
| This is the +1.2V power island. This island powers the internal logic of the FPGA. A reading of other than 1.2V indicates a problem with VR3.
|-
| VIN6
| 10
| ADC_EXT2
| This trace routes to the backplane via Eurocard pin A8. It is intended to measure one of the transistor base voltages on the amplifier board.
|-
| VIN7
| 9
| DACHEALTH
| This channel monitors the output of a resistor divider connected to channel 31 of the DAC. The divider consists of three resistors of 200K, 200K, and 10.2K (in order). The ADC reads out the voltage level between the second 200K and then 10.2K resistor. These resistors were selected so that at 200V, the readout voltage will be 4.973V. Since the divider should be linear, the expected voltage at 20V is 0.4973V. Three resistors were used rather than two to avoid exceeding the resistors' power ratings when the DAC is set to its maximum voltage. Note that since this divider will consume up to 484uA of current at 200V, this DAC channel should not be used for anything that might require more than ~200uA of current (the DAC can source 700uA max). The channel is routed to the backplane nonetheless.
|}

===Pinout Table===
{| cellpadding=3 border=1 |
| '''Pin #'''
| '''Net Name'''
| '''Description'''
|-
| 1
| CLK_5MHZ
| SPI clock (SCLK), from FPGA Shared with temperature sensor
|-
| 2
| DIN
| SPI data in, from FPGA Shared with temperature sensor ''Currently wired wrong''
|-
| 3
| CS
| SPI chip select
|-
| 4
| AGND
|
|-
| 5
| +5V
| Power pin
|-
| 6
| +5V
| Power pin
|-
| 7
| AD7928/REF_IN
| +2.5V reference, set by VR2
|-
| 8
| AGND
|
|-
| 9-16
| VIN[7:0]
| See [[#Channel Descriptions | ADC Channel Descriptions]]
|-
| 17
| AGND
|
|-
| 18
| DOUT
| SPI data out ''Currently wired incorrectly''
|-
| 19
| +3.3V
| VDRIVE, powers the SPI logic
|-
| 20
| AGND
|
|}

== Ethernet Controller ==
The board uses a Silicon Laboratories CP2201, 28-pin, ethernet controller. The CP2201 is located just above the FPGA, and is labelled U2.

=== Power Details ===
The CP2201 uses only +3.3V, which is supplied by the +3.3V power plane and regulated by VR1. Appropriate decoupling capacitors can be found near the CP2201.

=== Ethernet Jack ===
To the right of the CP2201 is a Pulse J0011D21NL ethernet jack, labelled J1. This jack has a built-in 1:1 inductive coupling. For best results, connect this jack to a nearby ethernet switch. The jack may also be connected directly to a computer using a crossover cable. Though auto-crossover is not supported by the CP2201, if the computer's NIC supports it, a crossover cable is not necessary to connect directly to a computer.

=== Crystal Oscillator ===
The CP2201 is responsible for driving the 20MHz crystal oscillator. This oscillator clocks both the CP2201 and the FPGA. The crystal oscillator can be found above the right corner of the FPGA. It can be identified by its four surface mount pads and roughly .3" length. It is labelled Y1, though this label is not visible after the oscillator is soldered on. The CP2201 uses an inverting driver to excite the crystal. The output of the crystal is then sent to the CP2201 and the FPGA.

=== Bus Format and Multiplexing ===
The 28-pin CP2201 used on the board only supports multiplexed operation. This means that both address and data information is passed over the same set of 8 traces. Hence, these traces are referred to as the address/data (AD) bus. A separate address line enable (ALE) trace prevents collisions from occuring on these traces. The communication protocol used is the Intel format. See the CP2201's datasheet for more information about this.

=== Pinout Table ===
{| cellpadding=3 border=1 |
| '''Pin #'''
| '''Net Name'''
| '''Description'''
|-
| 1
| CP2201/LA
| Link/activity indicator Routed to backplane but not implemented See CP2201 data sheet for information on how to connect to an LED
|-
| 2
| DGND
| By the data sheet, this pin should be AGND We deliberately set it to DGND to avoid noise on AGND plane
|-
| 3
| +3.3V
| AV+ power pin
|-
| 4
| CP2201/RX-
| Connects to RX- on ethernet jack
|-
| 5
| CP2201/RX+
| Connects to RX+ on ethernet jack
|-
| 6
| CP2201/TX+
| Connects to TX+ on ethernet jack
|-
| 7
| CP2201/TX-
| Connects to TX- on ethernet jack
|-
| 8
| +3.3V
| "VDD" power pin
|-
| 9
| DGND
| "DGND1" per the data sheet
|-
| 10
| CP2201/RESET
| "RST" per the data sheet Connects to FPGA - should be programmatically triggered upon reset of FPGA by RESET jumper
|-
| 11-18
| CP2201/AD[0:7]
| Bits 0-7 of the address/data bus Connect to FPGA
|-
| 19
| +3.3V
| "VDD" power pin
|-
| 20
| DGND
| "DGND2" per the data sheet
|-
| 21
| CP2201/ALE
| Address line enable Connects to FPGA See CP2201 documentation
|-
| 22
| CP2201/RD
| Read strobe for AD bus Connects to FPGA See CP2201 documentation
|-
| 23
| CP2201/WR
| Write strobe for AD bus Connects to FPGA See CP2201 documentation
|-
| 24
| CP2201/CS
| Chip select Connects to FPGA
|-
| 25
| CP2201/INT
| Interrupt request Connects to FPGA
|-
| 26
| DGND
| "MOTEN" (Motorola enable) per the datasheet Tied low to disable Motorola bus format (enable Intel format)
|-
| 27
| CP2201/XTAL2
| Crystal oscillator driver The CP2201 inverts the 20MHz clock signal and feeds it back to the crystal oscillator to encourage larger oscillations
|-
| 28
| FPGA/CLK_IN
| "XTAL1" per the data sheet This is the 20MHz clock input Also connects to the FPGA's clock input
|-
| 29*
| DGND
| This is not a pin but rather the base of the CP2201 package. It is connected to the DGND plane for thermal relief
|}

Digital control board documentation

2009-06-16T17:59:13Z

Underwood: /* Crystal Oscillator */

This documentation covers the most important things to know while testing the digital control board, including component pinouts, nets, and other information.

== Power Requirements ==
=== Required Voltages ===
All components on the digital board '''except the DAC''' can be tested using only a +5V source. The DAC requires +5V, -5V, and a high voltage corresponding to 10V higher than the maximum desired DAC output voltage (see [[#Setting the Output Range | Setting the Output Range]]). Digital and analog grounds must be connected as well before any testing takes place.

=== Power Pins ===
Power shall be connected to the board as follows:
{| cellpadding=3 border=1 |
| '''Voltage'''
| '''Eurocard Pin'''
|-
| DGND
| A6
|-
| AGND
| A5
|-
| +5V
| A4
|-
| -5V
| A3
|-
| High voltage (DAC max out +10)
| A2
|}

=== Power Supply Sequencing ===
The control board is designed such that voltages may be supplied in any order so long as AGND and DGND are connected properly. However, for initial testing, the preferred order for powering up the board is as follows:

# Ensure AGND/DGND are connected/grounded
# +5V
# -5V
# High voltage

== FPGA ==
The control board uses a Xilinx XC3S50A VQ100 FPGA. It has a 100 pin footprint and is located in the center of the control board.

=== Power Details ===
The FPGA is powered by the 3.3V power plane, which is regulated by VR1. The FPGA also obtains 1.2V for its internal logic from a 1.2V power island, regulated by VR3.

=== Logic Standard ===
The Xilinx XC3S50A supports several different digital logic standards. The control board is hard wired such that the FPGA will use a '''3.3V CMOS''' logic standard.

=== Pinout Table ===
{| cellpadding=3 border=1 |
| '''Pin #'''
| '''Net Name'''
| '''Description'''
|-
| P1
| FPGA/TMS
| JTAG
|-
| P2
| FPGA/TDI
| JTAG
|-
| P3
| AD7928/CS
| SPI chip select for ADC
|-
| P4
| SPI
| '''Erroneously wired SPI bus trace''' Connects to SDO on temp. sensor and DIN on ADC
|-
| P5
| CLK_5MHZ
| 5 MHz clock output for SPI bus (ADC and temp. sensor)
|-
| P6
| No connection
|
|-
| P7
| No connection
|
|-
| P8
| DGND
|
|-
| P9
| No connection
|
|-
| P10
| No connection
|
|-
| P11
| +3.3V
|
|-
| P12
| No connection
|
|-
| P13
| No connection
|
|-
| P14
| DGND
|
|-
| P15
| No connection
|
|-
| P16
| No connection
|
|-
| P17
| +1.2V
|
|-
| P18
| DGND
|
|-
| P19
| No connection
|
|-
| P20
| No connection
|
|-
| P21
| No connection
|
|-
| P22
| +3.3V
|
|-
| P23
| DGND
|
|-
| P24
| DGND
|
|-
| P25
| DGND
|
|-
| P26
| +3.3V
|
|-
| P27
| FPGA/CLK_IN
| 20 MHz clock input from crystal oscillator
|-
| P28
| No connection
|
|-
| P29
| No connection
|
|-
| P30
| No connection
|
|-
| P31
| No connection
|
|-
| P32
| No connection
|
|-
| P33
| No connection
|
|-
| P34
| No connection
|
|-
| P35
| CP2201/INT
| Ethernet controller interrupt
|-
| P36
| MASTER_RESET
| Connects to RESET jumper in upper left of board (active-low, externally pulled up)
|-
| P37
| No connection
|
|-
| P38
| +1.2V
|
|-
| P39
| No connection
|
|-
| P40
| CP2201/CS
| Chip select for ethernet controller
|-
| P41
| CP2201/WR
| Write enable for ethernet controller
|-
| P42
| DGND
|
|-
| P43
| CP2201/RD
| Read enable for ethernet controller
|-
| P44
| CP2201/ALE
| Address line enable for ethernet controller
|-
| P45
| +3.3V
|
|-
| P46
| CP2201/RESET
| Reset pin for ethernet controller
|-
| P47
| DGND
|
|-
| P48
| FPGA/INIT_B
| Used during FPGA configuration - see Xilinx documentation
|-
| P49
| CP2201/AD0
| Ethernet controller address/data bus, bit 0
|-
| P50
| CP2201/AD1
| Ethernet controller address/data bus, bit 1
|-
| P51
| FPGA/DIN
| Serial data input from EEPROM for configuration
|-
| P52
| CP2201/AD2
| Ethernet controller address/data bus, bit 2
|-
| P53
| FPGA/CCLK
| Configuration clock (signal generated by FPGA at power on to clock the configuration process) See Xilinx documentation
|-
| P54
| FPGA/DONE
| Gives configuration status - see Xilinx documentation
|-
| P55
| +3.3V
|
|-
| P56
| CP2201/AD3
| Ethernet controller address/data bus, bit 3
|-
| P57
| CP2201/AD4
| Ethernet controller address/data bus, bit 4
|-
| P58
| DGND
|
|-
| P59
| CP2201/AD5
| Ethernet controller address/data bus, bit 5
|-
| P60
| CP2201/AD6
| Ethernet controller address/date bus, bit 6
|-
| P61
| CP2201/AD7
| Ethernet controller address/date bus, bit 7
|-
| P62
| No connection
|
|-
| P63
| DGND
|
|-
| P64
| No connection
|
|-
| P65
| No connection
|
|-
| P66
| +1.2V
|
|-
| P67
| +3.3V
|
|-
| P68
| +3.3V
|
|-
| P69
| DGND
|
|-
| P70
| ID3
| Backplane location identifier jumper, pins 3 & 4 Active-low, FPGA should pull high
|-
| P71
| ID2
| Backplane location identifier jumper, pins 5 & 6 Active-low, FPGA should pull high
|-
| P72
| ID1
| Backplane location identifier jumper, pins 7 & 8 Active-low, FPGA should pull high
|-
| P73
| ID0
| Backplane location identifier jumper, pins 9 & 10 Active-low, FPGA should pull high
|-
| P74
| DGND
|
|-
| P75
| FPGA/TDO
| JTAG
|-
| P76
| FPGA/TCK
| JTAG
|-
| P77
| ID4
| Backplane location identifier jumper, pins 1 & 2 Active-low, FPGA should pull high
|-
| P78
| No connection
|
|-
| P79
| +3.3V
|
|-
| P80
| DGND
|
|-
| P81
| +1.2V
|
|-
| P82
| No connection
|
|-
| P83
| CLK_5MHZ_2
| 5 MHz clock output for DAC
|-
| P84
| No connection
|
|-
| P85
| AD5535/DIN
| DAC serial data input (FPGA out -> DAC in)
|-
| P86
| No connection
|
|-
| P87
| DGND
|
|-
| P89
| No connection
|
|-
| P90
| No connection
|
|-
| P91
| DGND
|
|-
| P92
| +3.3V
|
|-
| P93
| AD7314/CE
| Chip enable for temperature sensor
|-
| P94
| No connection
|
|-
| P95
| DGND
|
|-
| P96
| +3.3V
|
|-
| P97
| AD7928/DOUT
| '''Erroneously wired ADC SPI bus connection''' Connects to DOUT on ADC
|-
| P98
| AD5535/RESET
| Reset pin for DAC
|-
| P99
| DGND
|
|-
| P100
| FPGA/PROG_B
| Used during FPGA configuration - see Xilinx documentation
|}

== EEPROM ==
To facilitate power-on configuration of the FPGA, the control board includes a Xilinx XCF01S EEPROM. The EEPROM is located to the left of the FPGA, above the JTAG header, and has a 20 pin footprint. The EEPROM is labelled U5.

=== Power Details ===
The EEPROM uses +3.3V exclusively, which it receives from the +3.3V power plane, regulated by VR1.

=== Flashing/Burning/Writing ===
Whatever you call it, this refers to storing data in the EEPROM so that it can configure the FPGA at power-on. The EEPROM is programmed using a JTAG interface and the Xilinx Platform USB II cable. It is important to note that in digital board's JTAG chain, the EEPROM is the first device in the chain, unlike in the Xilinx documentation where it is shown as the second device. This should not affect the operation of the board, but should be reflected in the Xilinx software when writing the EEPROM via JTAG.

=== FPGA Configuration ===
The EEPROM and FPGA are hardwired to use a master serial protocol to transfer the program from the EEPROM to the FPGA. This is the protocol recommended in the Xilinx documentation because it minimizes the number of traces necessary to run between the EEPROM and FPGA. All configuration data is sent over a single trace, FPGA/DIN (pin 1 on EEPROM), controlled by the configuration clock signal (FPGA/CCLK) which is automatically generated by the FPGA at power-on. When configuration is complete, FPGA/DONE (pin 10) is pulled high by the FPGA, and the EEPROM and configuration clock are deactivated.

=== Pinout Table ===
{| cellpadding=3 border=1 |
| '''Pin #'''
| '''Net Name'''
| '''Description'''
|-
| 1
| FPGA/DIN
| Serial data line Carries data from the EEPROM to the FPGA
|-
| 2
| No connection
|
|-
| 3
| FPGA/CCLK
| Configuration clock Auto generated by FPGA at power-on, disabled at end of configuration
|-
| 4
| EEPROM/TDI
| This is the EEPROM's TDI This is the entry point for the onboard JTAG chain
|-
| 5
| FPGA/TMS
| JTAG TMS Connects to both FPGA and EEPROM
|-
| 6
| FPGA/TCK
| JTAG TCK Connects to both FPGA and EEPROM
|-
| 7
| FPGA/PROG_B
| Used during configuration See Xilinx documentation
|-
| 8
| FPGA/INIT_B
| Used during configuration - can be used to intiate reconfiguration of FPGA See Xilinx documentation
|-
| 9
| No connection
|
|-
| 10
| FPGA/DONE
| Indicates completion of FPGA configuration High when complete
|-
| 11
| DGND
|
|-
| 12-16
| No connection
|
|-
| 17
| FPGA/TDI
| This is the EEPROM's TDO/FPGA's TDI
|-
| 18-20
| +3.3V
|
|}

== JTAG Header ==
To write the FPGA's program to the EEPROM, the board employs a JTAG based programming system consistent with Xilinx's recommendations. The system is designed to operate with Xilnx's Platform USB II cable and the flying lead adapter.

===Header Location and Size===
The header consists of 14 pins, 100 mil pitch, just below the EEPROM (U5). The header is labelled P1. The pitch of the pins in the header was erroneously selected to be 100 mil, which is not compatible with Xilinx's JTAG ribbon cable. Therefore, the Xilinx flying lead adapter must be used.

===Power Details===
The JTAG interface is powered by the +3.3V power plane, not by the computer's USB port. Power is supplied through pin 2 of the JTAG header.

===Pinout Table===
Note that the header is positioned on the board rotated 180 degrees from the position in which it is shown in the Xilinx documentation. Care must be taken when connecting the flying leads to ensure they are connected to the right pins. Connecting the flying leads to the wrong side of the header will cause all of the leads to short on the digital board's ground plane. This will certainly cause undesired operation, and may or may not cause damage. Improper wiring is most likely to cause damage if one of the flying leads is connected to an odd numbered pin. '''Note from the pinout table below that no flying lead connections should ever be made to the odd numbered pins on the JTAG header.'''

{| cellpadding=3 border=1 |
| '''Pin #'''
| '''Net Name'''
| '''Description'''
|-
| 1, 3, 5, 7, 9, 11, 13 (odd pins)
| DGND
| Ground pins for signal integrity '''Never connect a flying lead to these pins''' Doing so will short to ground and may cause permanent damage if the Platform USB II cable does not have protection against this.
|-
| 2
| +3.3V
| Power source for all JTAG logic
|-
| 4
| FPGA/TMS
| JTAG TMS - connects to EEPROM and FPGA
|-
| 6
| FPGA/TCK
| JTAG TCK - connects to EEPROM and FPGA
|-
| 8
| FPGA/TDO
| JTAG boundary scan chain endpoint
|-
| 10
| EEPROM/TDI
| JTAG boundary scan chain start point
|-
| 12
| No connection
| Pin is floating
|-
| 14
| No connection
| Pin is floating
|}

===JTAG Overview===
The JTAG interface is clocked by the TCK signal. TCK is generated by the Platform USB II cable, and connects directly from the JTAG header to both the EEPROM and FPGA.

The TMS signal is directly connected to both the EEPROM and FPGA, and is the data line over which JTAG test results (in this case programming results) are sent. TMS is used by only one component at a time.

The TDI/TDO lines form a chain that connects to each JTAG component in series. On the control board, the first point in the chain is the EEPROM's TDI. Next is the EEPROM's TDO, which is the same as the FPGA's TDI. The FPGA's TDO then returns to the JTAG header and the Platform USB II cable.

== DAC ==
The control board uses the Analog Devices AD5535, 32-channel, 200V max, digital to analog converter. This chip has a modified BC-124 BGA footprint and is located above the Eurocard connector at the bottom of the board. It is labelled U3.

=== Power Details ===
The DAC is primarily powered by the +5V power island, regulated by an off-board power supply and extensively decoupled in the area of the DAC. The DAC also requires -5V, and a high voltage as discussed in [[#Power Requirements | Power Requirements]]. Both of these voltages are supplied by an off-board supply and decoupled near the DAC. In addition to these voltage levels, the DAC requires a precise +2.5V reference, created by the shunt-type voltage reference VR4.

=== Setting the Output Range ===
The output range of the DAC is set by the 2.5V reference voltage supplied by VR4. The high voltage power supply must supply at a minimum 50 times this voltage, plus 10. Thus, the high voltage power supply should be at least 135V for DAC to operate properly, even though the SiPMs are expected to need only 40V. If it is convenient to use a lower high voltage, VR4 must be replaced to provide lower reference voltage. The high voltage may then be decreased appropriately. To summarize:

* Max output voltage = VREF*50
* Minimum high voltage supply = VREF*50 + 10
* Acceptable range for VREF
** Min: 1V
** Max: 3.75V (AD5535 datasheet specifies 4V max, but this would require AVCC of 5.25V for the DAC, which is not possible in the current board design)

If relevant, R13 is a 100K resistor.

=== Thermal Diode ===
The DAC has a built in thermal diode. The diode drop from anode to cathode is typically 0.65V at 25°C. It changes at a rate of -2.20mV/°C. The anode of this diode is connected to the +5V power island, and the cathode is connected to a 270K resistor to ground. The voltage between the cathode and the resistor is connected to VIN1 (pin 15) on the ADC.

=== Pinout Table ===
See documentation from Analog Devices.

=== Channel Mapping ===
Due to the layout of the balls on the footprint of the DAC, the DAC's internal channel numbers (which must be referenced by the FPGA) have no correlation to the channel numbers on the amplifier board. This table summarizes the mapping between various pins that belong to each channel.

{| cellpadding=3 border=1 |
| '''DAC Channel #'''
| '''DAC Pin #'''
| '''Digital Board Eurocard Pin #'''
| '''Amplifier Board Eurocard Pin #'''
| '''Physical Channel #'''
|-
| 0
| B1
| B3
|
|
|-
| 1
| A2
| C4
|
|
|-
| 2
| D1
| B2
|
|
|-
| 3
| C2
| C3
|
|
|-
| 4
| B3
| B4
|
|
|-
| 5
| E2
| C2
|
|
|-
| 6
| F3
| B1
|
|
|-
| 7
| A4
| B5
|
|
|-
| 8
| E4
| C5
|
|
|-
| 9
| B5
| C6
|
|
|-
| 10
| F5
| C1
|
|
|-
| 11
| A6
| C7
|
|
|-
| 12
| E6
| B6
|
|
|-
| 13
| B7
| B7
|
|
|-
| 14
| F7
| C10
|
|
|-
| 15
| E8
| C8
|
|
|-
| 16
| A8
| B8
|
|
|-
| 17
| B9
| C9
|
|
|-
| 18
| F9
| C16
|
|
|-
| 19
| E10
| B11
|
|
|-
| 20
| A10
| B9
|
|
|-
| 21
| B11
| B10
|
|
|-
| 22
| C12
| B12
|
|
|-
| 23
| D13
| B13
|
|
|-
| 24
| E12
| B14
|
|
|-
| 25
| A12
| C11
|
|
|-
| 26
| B13
| C12
|
|
|-
| 27
| H13
| B16
|
|
|-
| 28
| G14
| B15
|
|
|-
| 29
| C14
| C13
|
|
|-
| 30
| F13
| C15
|
|
|-
| 31
| E14
| C14
|
| DACHEALTH See [[#Channel Descriptions | ADC Channel Descriptions]].
|}

==ADC==
The board includes an Analog Devices AD7928 analog to digital converter. The ADC is located just to the right and slightly below the FPGA. It is labelled U4.

===Power Details===
The ADC is powered by the +5V power island, which is regulated by an off-board power supply and decoupled near the ADC. It also requires a precise (±1%) 2.5V reference to which it compares voltages when converting from analog to digital. Since the +5V power source is not used for comparison, it is flexible and may vary by ±0.25V without affecting ADC precision.

===Setting the Measuring Range===
The measuring range is set programmatically by the FPGA over the SPI bus. The way the ADC is connected on the digital board requires that its measuring range be set to 5V, so the RANGE bit should be set to 1 by the FPGA (see Analog Devices documentation).

===Data Interfacing===
The ADC uses an SPI bus to communicate with the FPGA. This bus is shared with the temperature sensor. SPI related pins include SCLK, CS, DIN, and DOUT. See the Pinout Table below.

===Channel Descriptions===
This table shows what signals are monitored by the ADC.

{| cellpadding=3 border=1 |
| '''ADC Channel #'''
| '''ADC Pin #'''
| '''Net Name'''
| '''Description'''
|-
| VIN0
| 16
| AD7928/VHEALTH
| This net helps to monitor to overall health of power on the board, but is specifically intended to monitor -5V. It's voltage is the output of a resistor divider between the +5 and -5V power supplies, with resistor values of 33.2K, and 100K. Assuming +5V and -5V are both correct, the output of the divider will be +2.51V. A reading of other than 2.51V indicates a problem with one of the power supplies. Problems with the +5V power supply can be ruled out by reading VIN3. Based on the reading from VIN3, the voltage of the -5V supply can be calculated.
|-
| VIN1
| 15
| AD5535/CATHODE
| This is the thermal diode output from the DAC. Should read 4.35V (typical) at 25°C. Drops 2.20mV/°C.
|-
| VIN2
| 14
| +3.3V
| This is the +3.3V power plane. A reading of other than +3.3V indicates a problem with VR1.
|-
| VIN3
| 13
| +5V
| This is the +5V power island. A reading of other than +5V indicates a problem with the +5V power supply.
|-
| VIN4
| 12
| ADC_EXT1
| This trace routes to the backplane via Eurocard pin A7. It is intended to measure the output of thermistor on the amplifier board.
|-
| VIN5
| 11
| +1.2V
| This is the +1.2V power island. This island powers the internal logic of the FPGA. A reading of other than 1.2V indicates a problem with VR3.
|-
| VIN6
| 10
| ADC_EXT2
| This trace routes to the backplane via Eurocard pin A8. It is intended to measure one of the transistor base voltages on the amplifier board.
|-
| VIN7
| 9
| DACHEALTH
| This channel monitors the output of a resistor divider connected to channel 31 of the DAC. The divider consists of three resistors of 200K, 200K, and 10.2K (in order). The ADC reads out the voltage level between the second 200K and then 10.2K resistor. These resistors were selected so that at 200V, the readout voltage will be 4.973V. Since the divider should be linear, the expected voltage at 20V is 0.4973V. Three resistors were used rather than two to avoid exceeding the resistors' power ratings when the DAC is set to its maximum voltage. Note that since this divider will consume up to 484uA of current at 200V, this DAC channel should not be used for anything that might require more than ~200uA of current (the DAC can source 700uA max). The channel is routed to the backplane nonetheless.
|}

===Pinout Table===
{| cellpadding=3 border=1 |
| '''Pin #'''
| '''Net Name'''
| '''Description'''
|-
| 1
| CLK_5MHZ
| SPI clock (SCLK), from FPGA Shared with temperature sensor
|-
| 2
| DIN
| SPI data in, from FPGA Shared with temperature sensor ''Currently wired wrong''
|-
| 3
| CS
| SPI chip select
|-
| 4
| AGND
|
|-
| 5
| +5V
| Power pin
|-
| 6
| +5V
| Power pin
|-
| 7
| AD7928/REF_IN
| +2.5V reference, set by VR2
|-
| 8
| AGND
|
|-
| 9-16
| VIN[7:0]
| See [[#Channel Descriptions | ADC Channel Descriptions]]
|-
| 17
| AGND
|
|-
| 18
| DOUT
| SPI data out ''Currently wired incorrectly''
|-
| 19
| +3.3V
| VDRIVE, powers the SPI logic
|-
| 20
| AGND
|
|}

== Ethernet Controller ==
The board uses a Silicon Laboratories CP2201, 28-pin, ethernet controller. The CP2201 is located just above the FPGA, and is labelled U2.

=== Power Details ===
The CP2201 uses only +3.3V, which is supplied by the +3.3V power plane and regulated by VR1. Appropriate decoupling capacitors can be found near the CP2201.

=== Ethernet Jack ===
To the right of the CP2201 is a Pulse J0011D21NL ethernet jack, labelled J1. This jack has a built-in 1:1 inductive coupling. For best results, connect this jack to a nearby ethernet switch. The jack may also be connected directly to a computer using a crossover cable. Though auto-crossover is not supported by the CP2201, if the computer's NIC supports it, a crossover cable is not necessary to connect directly to a computer.

=== Crystal Oscillator ===
The CP2201 is responsible for driving the 20MHz crystal oscillator. This oscillator clocks both the CP2201 and the FPGA. The crystal oscillator can be found above the right corner of the FPGA. It can be identified by its four surface mount pads and roughly .3" length. It is labelled Y1, though this label is not visible after the oscillator is soldered on. The CP2201 uses an inverting driver to excite the crystal. The output of the crystal is then sent to the CP2201 and the FPGA.

=== Bus Format and Multiplexing ===
The 28-pin CP2201 used on the board only supports multiplexed operation. This means that both address and data information is passed over the same set of 8 traces. Hence, these traces are referred to as the address/data (AD) bus. A separate address line enable (ALE) trace prevents collisions from occuring on these traces. The communication protocol used is the Intel format. See the CP2201's datasheet for more information about this.

=== Pinout Table ===

Digital control board documentation

2009-06-16T17:58:31Z

Underwood: started CP2201

This documentation covers the most important things to know while testing the digital control board, including component pinouts, nets, and other information.

== Power Requirements ==
=== Required Voltages ===
All components on the digital board '''except the DAC''' can be tested using only a +5V source. The DAC requires +5V, -5V, and a high voltage corresponding to 10V higher than the maximum desired DAC output voltage (see [[#Setting the Output Range | Setting the Output Range]]). Digital and analog grounds must be connected as well before any testing takes place.

=== Power Pins ===
Power shall be connected to the board as follows:
{| cellpadding=3 border=1 |
| '''Voltage'''
| '''Eurocard Pin'''
|-
| DGND
| A6
|-
| AGND
| A5
|-
| +5V
| A4
|-
| -5V
| A3
|-
| High voltage (DAC max out +10)
| A2
|}

=== Power Supply Sequencing ===
The control board is designed such that voltages may be supplied in any order so long as AGND and DGND are connected properly. However, for initial testing, the preferred order for powering up the board is as follows:

# Ensure AGND/DGND are connected/grounded
# +5V
# -5V
# High voltage

== FPGA ==
The control board uses a Xilinx XC3S50A VQ100 FPGA. It has a 100 pin footprint and is located in the center of the control board.

=== Power Details ===
The FPGA is powered by the 3.3V power plane, which is regulated by VR1. The FPGA also obtains 1.2V for its internal logic from a 1.2V power island, regulated by VR3.

=== Logic Standard ===
The Xilinx XC3S50A supports several different digital logic standards. The control board is hard wired such that the FPGA will use a '''3.3V CMOS''' logic standard.

=== Pinout Table ===
{| cellpadding=3 border=1 |
| '''Pin #'''
| '''Net Name'''
| '''Description'''
|-
| P1
| FPGA/TMS
| JTAG
|-
| P2
| FPGA/TDI
| JTAG
|-
| P3
| AD7928/CS
| SPI chip select for ADC
|-
| P4
| SPI
| '''Erroneously wired SPI bus trace''' Connects to SDO on temp. sensor and DIN on ADC
|-
| P5
| CLK_5MHZ
| 5 MHz clock output for SPI bus (ADC and temp. sensor)
|-
| P6
| No connection
|
|-
| P7
| No connection
|
|-
| P8
| DGND
|
|-
| P9
| No connection
|
|-
| P10
| No connection
|
|-
| P11
| +3.3V
|
|-
| P12
| No connection
|
|-
| P13
| No connection
|
|-
| P14
| DGND
|
|-
| P15
| No connection
|
|-
| P16
| No connection
|
|-
| P17
| +1.2V
|
|-
| P18
| DGND
|
|-
| P19
| No connection
|
|-
| P20
| No connection
|
|-
| P21
| No connection
|
|-
| P22
| +3.3V
|
|-
| P23
| DGND
|
|-
| P24
| DGND
|
|-
| P25
| DGND
|
|-
| P26
| +3.3V
|
|-
| P27
| FPGA/CLK_IN
| 20 MHz clock input from crystal oscillator
|-
| P28
| No connection
|
|-
| P29
| No connection
|
|-
| P30
| No connection
|
|-
| P31
| No connection
|
|-
| P32
| No connection
|
|-
| P33
| No connection
|
|-
| P34
| No connection
|
|-
| P35
| CP2201/INT
| Ethernet controller interrupt
|-
| P36
| MASTER_RESET
| Connects to RESET jumper in upper left of board (active-low, externally pulled up)
|-
| P37
| No connection
|
|-
| P38
| +1.2V
|
|-
| P39
| No connection
|
|-
| P40
| CP2201/CS
| Chip select for ethernet controller
|-
| P41
| CP2201/WR
| Write enable for ethernet controller
|-
| P42
| DGND
|
|-
| P43
| CP2201/RD
| Read enable for ethernet controller
|-
| P44
| CP2201/ALE
| Address line enable for ethernet controller
|-
| P45
| +3.3V
|
|-
| P46
| CP2201/RESET
| Reset pin for ethernet controller
|-
| P47
| DGND
|
|-
| P48
| FPGA/INIT_B
| Used during FPGA configuration - see Xilinx documentation
|-
| P49
| CP2201/AD0
| Ethernet controller address/data bus, bit 0
|-
| P50
| CP2201/AD1
| Ethernet controller address/data bus, bit 1
|-
| P51
| FPGA/DIN
| Serial data input from EEPROM for configuration
|-
| P52
| CP2201/AD2
| Ethernet controller address/data bus, bit 2
|-
| P53
| FPGA/CCLK
| Configuration clock (signal generated by FPGA at power on to clock the configuration process) See Xilinx documentation
|-
| P54
| FPGA/DONE
| Gives configuration status - see Xilinx documentation
|-
| P55
| +3.3V
|
|-
| P56
| CP2201/AD3
| Ethernet controller address/data bus, bit 3
|-
| P57
| CP2201/AD4
| Ethernet controller address/data bus, bit 4
|-
| P58
| DGND
|
|-
| P59
| CP2201/AD5
| Ethernet controller address/data bus, bit 5
|-
| P60
| CP2201/AD6
| Ethernet controller address/date bus, bit 6
|-
| P61
| CP2201/AD7
| Ethernet controller address/date bus, bit 7
|-
| P62
| No connection
|
|-
| P63
| DGND
|
|-
| P64
| No connection
|
|-
| P65
| No connection
|
|-
| P66
| +1.2V
|
|-
| P67
| +3.3V
|
|-
| P68
| +3.3V
|
|-
| P69
| DGND
|
|-
| P70
| ID3
| Backplane location identifier jumper, pins 3 & 4 Active-low, FPGA should pull high
|-
| P71
| ID2
| Backplane location identifier jumper, pins 5 & 6 Active-low, FPGA should pull high
|-
| P72
| ID1
| Backplane location identifier jumper, pins 7 & 8 Active-low, FPGA should pull high
|-
| P73
| ID0
| Backplane location identifier jumper, pins 9 & 10 Active-low, FPGA should pull high
|-
| P74
| DGND
|
|-
| P75
| FPGA/TDO
| JTAG
|-
| P76
| FPGA/TCK
| JTAG
|-
| P77
| ID4
| Backplane location identifier jumper, pins 1 & 2 Active-low, FPGA should pull high
|-
| P78
| No connection
|
|-
| P79
| +3.3V
|
|-
| P80
| DGND
|
|-
| P81
| +1.2V
|
|-
| P82
| No connection
|
|-
| P83
| CLK_5MHZ_2
| 5 MHz clock output for DAC
|-
| P84
| No connection
|
|-
| P85
| AD5535/DIN
| DAC serial data input (FPGA out -> DAC in)
|-
| P86
| No connection
|
|-
| P87
| DGND
|
|-
| P89
| No connection
|
|-
| P90
| No connection
|
|-
| P91
| DGND
|
|-
| P92
| +3.3V
|
|-
| P93
| AD7314/CE
| Chip enable for temperature sensor
|-
| P94
| No connection
|
|-
| P95
| DGND
|
|-
| P96
| +3.3V
|
|-
| P97
| AD7928/DOUT
| '''Erroneously wired ADC SPI bus connection''' Connects to DOUT on ADC
|-
| P98
| AD5535/RESET
| Reset pin for DAC
|-
| P99
| DGND
|
|-
| P100
| FPGA/PROG_B
| Used during FPGA configuration - see Xilinx documentation
|}

== EEPROM ==
To facilitate power-on configuration of the FPGA, the control board includes a Xilinx XCF01S EEPROM. The EEPROM is located to the left of the FPGA, above the JTAG header, and has a 20 pin footprint. The EEPROM is labelled U5.

=== Power Details ===
The EEPROM uses +3.3V exclusively, which it receives from the +3.3V power plane, regulated by VR1.

=== Flashing/Burning/Writing ===
Whatever you call it, this refers to storing data in the EEPROM so that it can configure the FPGA at power-on. The EEPROM is programmed using a JTAG interface and the Xilinx Platform USB II cable. It is important to note that in digital board's JTAG chain, the EEPROM is the first device in the chain, unlike in the Xilinx documentation where it is shown as the second device. This should not affect the operation of the board, but should be reflected in the Xilinx software when writing the EEPROM via JTAG.

=== FPGA Configuration ===
The EEPROM and FPGA are hardwired to use a master serial protocol to transfer the program from the EEPROM to the FPGA. This is the protocol recommended in the Xilinx documentation because it minimizes the number of traces necessary to run between the EEPROM and FPGA. All configuration data is sent over a single trace, FPGA/DIN (pin 1 on EEPROM), controlled by the configuration clock signal (FPGA/CCLK) which is automatically generated by the FPGA at power-on. When configuration is complete, FPGA/DONE (pin 10) is pulled high by the FPGA, and the EEPROM and configuration clock are deactivated.

=== Pinout Table ===
{| cellpadding=3 border=1 |
| '''Pin #'''
| '''Net Name'''
| '''Description'''
|-
| 1
| FPGA/DIN
| Serial data line Carries data from the EEPROM to the FPGA
|-
| 2
| No connection
|
|-
| 3
| FPGA/CCLK
| Configuration clock Auto generated by FPGA at power-on, disabled at end of configuration
|-
| 4
| EEPROM/TDI
| This is the EEPROM's TDI This is the entry point for the onboard JTAG chain
|-
| 5
| FPGA/TMS
| JTAG TMS Connects to both FPGA and EEPROM
|-
| 6
| FPGA/TCK
| JTAG TCK Connects to both FPGA and EEPROM
|-
| 7
| FPGA/PROG_B
| Used during configuration See Xilinx documentation
|-
| 8
| FPGA/INIT_B
| Used during configuration - can be used to intiate reconfiguration of FPGA See Xilinx documentation
|-
| 9
| No connection
|
|-
| 10
| FPGA/DONE
| Indicates completion of FPGA configuration High when complete
|-
| 11
| DGND
|
|-
| 12-16
| No connection
|
|-
| 17
| FPGA/TDI
| This is the EEPROM's TDO/FPGA's TDI
|-
| 18-20
| +3.3V
|
|}

== JTAG Header ==
To write the FPGA's program to the EEPROM, the board employs a JTAG based programming system consistent with Xilinx's recommendations. The system is designed to operate with Xilnx's Platform USB II cable and the flying lead adapter.

===Header Location and Size===
The header consists of 14 pins, 100 mil pitch, just below the EEPROM (U5). The header is labelled P1. The pitch of the pins in the header was erroneously selected to be 100 mil, which is not compatible with Xilinx's JTAG ribbon cable. Therefore, the Xilinx flying lead adapter must be used.

===Power Details===
The JTAG interface is powered by the +3.3V power plane, not by the computer's USB port. Power is supplied through pin 2 of the JTAG header.

===Pinout Table===
Note that the header is positioned on the board rotated 180 degrees from the position in which it is shown in the Xilinx documentation. Care must be taken when connecting the flying leads to ensure they are connected to the right pins. Connecting the flying leads to the wrong side of the header will cause all of the leads to short on the digital board's ground plane. This will certainly cause undesired operation, and may or may not cause damage. Improper wiring is most likely to cause damage if one of the flying leads is connected to an odd numbered pin. '''Note from the pinout table below that no flying lead connections should ever be made to the odd numbered pins on the JTAG header.'''

{| cellpadding=3 border=1 |
| '''Pin #'''
| '''Net Name'''
| '''Description'''
|-
| 1, 3, 5, 7, 9, 11, 13 (odd pins)
| DGND
| Ground pins for signal integrity '''Never connect a flying lead to these pins''' Doing so will short to ground and may cause permanent damage if the Platform USB II cable does not have protection against this.
|-
| 2
| +3.3V
| Power source for all JTAG logic
|-
| 4
| FPGA/TMS
| JTAG TMS - connects to EEPROM and FPGA
|-
| 6
| FPGA/TCK
| JTAG TCK - connects to EEPROM and FPGA
|-
| 8
| FPGA/TDO
| JTAG boundary scan chain endpoint
|-
| 10
| EEPROM/TDI
| JTAG boundary scan chain start point
|-
| 12
| No connection
| Pin is floating
|-
| 14
| No connection
| Pin is floating
|}

===JTAG Overview===
The JTAG interface is clocked by the TCK signal. TCK is generated by the Platform USB II cable, and connects directly from the JTAG header to both the EEPROM and FPGA.

The TMS signal is directly connected to both the EEPROM and FPGA, and is the data line over which JTAG test results (in this case programming results) are sent. TMS is used by only one component at a time.

The TDI/TDO lines form a chain that connects to each JTAG component in series. On the control board, the first point in the chain is the EEPROM's TDI. Next is the EEPROM's TDO, which is the same as the FPGA's TDI. The FPGA's TDO then returns to the JTAG header and the Platform USB II cable.

== DAC ==
The control board uses the Analog Devices AD5535, 32-channel, 200V max, digital to analog converter. This chip has a modified BC-124 BGA footprint and is located above the Eurocard connector at the bottom of the board. It is labelled U3.

=== Power Details ===
The DAC is primarily powered by the +5V power island, regulated by an off-board power supply and extensively decoupled in the area of the DAC. The DAC also requires -5V, and a high voltage as discussed in [[#Power Requirements | Power Requirements]]. Both of these voltages are supplied by an off-board supply and decoupled near the DAC. In addition to these voltage levels, the DAC requires a precise +2.5V reference, created by the shunt-type voltage reference VR4.

=== Setting the Output Range ===
The output range of the DAC is set by the 2.5V reference voltage supplied by VR4. The high voltage power supply must supply at a minimum 50 times this voltage, plus 10. Thus, the high voltage power supply should be at least 135V for DAC to operate properly, even though the SiPMs are expected to need only 40V. If it is convenient to use a lower high voltage, VR4 must be replaced to provide lower reference voltage. The high voltage may then be decreased appropriately. To summarize:

* Max output voltage = VREF*50
* Minimum high voltage supply = VREF*50 + 10
* Acceptable range for VREF
** Min: 1V
** Max: 3.75V (AD5535 datasheet specifies 4V max, but this would require AVCC of 5.25V for the DAC, which is not possible in the current board design)

If relevant, R13 is a 100K resistor.

=== Thermal Diode ===
The DAC has a built in thermal diode. The diode drop from anode to cathode is typically 0.65V at 25°C. It changes at a rate of -2.20mV/°C. The anode of this diode is connected to the +5V power island, and the cathode is connected to a 270K resistor to ground. The voltage between the cathode and the resistor is connected to VIN1 (pin 15) on the ADC.

=== Pinout Table ===
See documentation from Analog Devices.

=== Channel Mapping ===
Due to the layout of the balls on the footprint of the DAC, the DAC's internal channel numbers (which must be referenced by the FPGA) have no correlation to the channel numbers on the amplifier board. This table summarizes the mapping between various pins that belong to each channel.

{| cellpadding=3 border=1 |
| '''DAC Channel #'''
| '''DAC Pin #'''
| '''Digital Board Eurocard Pin #'''
| '''Amplifier Board Eurocard Pin #'''
| '''Physical Channel #'''
|-
| 0
| B1
| B3
|
|
|-
| 1
| A2
| C4
|
|
|-
| 2
| D1
| B2
|
|
|-
| 3
| C2
| C3
|
|
|-
| 4
| B3
| B4
|
|
|-
| 5
| E2
| C2
|
|
|-
| 6
| F3
| B1
|
|
|-
| 7
| A4
| B5
|
|
|-
| 8
| E4
| C5
|
|
|-
| 9
| B5
| C6
|
|
|-
| 10
| F5
| C1
|
|
|-
| 11
| A6
| C7
|
|
|-
| 12
| E6
| B6
|
|
|-
| 13
| B7
| B7
|
|
|-
| 14
| F7
| C10
|
|
|-
| 15
| E8
| C8
|
|
|-
| 16
| A8
| B8
|
|
|-
| 17
| B9
| C9
|
|
|-
| 18
| F9
| C16
|
|
|-
| 19
| E10
| B11
|
|
|-
| 20
| A10
| B9
|
|
|-
| 21
| B11
| B10
|
|
|-
| 22
| C12
| B12
|
|
|-
| 23
| D13
| B13
|
|
|-
| 24
| E12
| B14
|
|
|-
| 25
| A12
| C11
|
|
|-
| 26
| B13
| C12
|
|
|-
| 27
| H13
| B16
|
|
|-
| 28
| G14
| B15
|
|
|-
| 29
| C14
| C13
|
|
|-
| 30
| F13
| C15
|
|
|-
| 31
| E14
| C14
|
| DACHEALTH See [[#Channel Descriptions | ADC Channel Descriptions]].
|}

==ADC==
The board includes an Analog Devices AD7928 analog to digital converter. The ADC is located just to the right and slightly below the FPGA. It is labelled U4.

===Power Details===
The ADC is powered by the +5V power island, which is regulated by an off-board power supply and decoupled near the ADC. It also requires a precise (±1%) 2.5V reference to which it compares voltages when converting from analog to digital. Since the +5V power source is not used for comparison, it is flexible and may vary by ±0.25V without affecting ADC precision.

===Setting the Measuring Range===
The measuring range is set programmatically by the FPGA over the SPI bus. The way the ADC is connected on the digital board requires that its measuring range be set to 5V, so the RANGE bit should be set to 1 by the FPGA (see Analog Devices documentation).

===Data Interfacing===
The ADC uses an SPI bus to communicate with the FPGA. This bus is shared with the temperature sensor. SPI related pins include SCLK, CS, DIN, and DOUT. See the Pinout Table below.

===Channel Descriptions===
This table shows what signals are monitored by the ADC.

{| cellpadding=3 border=1 |
| '''ADC Channel #'''
| '''ADC Pin #'''
| '''Net Name'''
| '''Description'''
|-
| VIN0
| 16
| AD7928/VHEALTH
| This net helps to monitor to overall health of power on the board, but is specifically intended to monitor -5V. It's voltage is the output of a resistor divider between the +5 and -5V power supplies, with resistor values of 33.2K, and 100K. Assuming +5V and -5V are both correct, the output of the divider will be +2.51V. A reading of other than 2.51V indicates a problem with one of the power supplies. Problems with the +5V power supply can be ruled out by reading VIN3. Based on the reading from VIN3, the voltage of the -5V supply can be calculated.
|-
| VIN1
| 15
| AD5535/CATHODE
| This is the thermal diode output from the DAC. Should read 4.35V (typical) at 25°C. Drops 2.20mV/°C.
|-
| VIN2
| 14
| +3.3V
| This is the +3.3V power plane. A reading of other than +3.3V indicates a problem with VR1.
|-
| VIN3
| 13
| +5V
| This is the +5V power island. A reading of other than +5V indicates a problem with the +5V power supply.
|-
| VIN4
| 12
| ADC_EXT1
| This trace routes to the backplane via Eurocard pin A7. It is intended to measure the output of thermistor on the amplifier board.
|-
| VIN5
| 11
| +1.2V
| This is the +1.2V power island. This island powers the internal logic of the FPGA. A reading of other than 1.2V indicates a problem with VR3.
|-
| VIN6
| 10
| ADC_EXT2
| This trace routes to the backplane via Eurocard pin A8. It is intended to measure one of the transistor base voltages on the amplifier board.
|-
| VIN7
| 9
| DACHEALTH
| This channel monitors the output of a resistor divider connected to channel 31 of the DAC. The divider consists of three resistors of 200K, 200K, and 10.2K (in order). The ADC reads out the voltage level between the second 200K and then 10.2K resistor. These resistors were selected so that at 200V, the readout voltage will be 4.973V. Since the divider should be linear, the expected voltage at 20V is 0.4973V. Three resistors were used rather than two to avoid exceeding the resistors' power ratings when the DAC is set to its maximum voltage. Note that since this divider will consume up to 484uA of current at 200V, this DAC channel should not be used for anything that might require more than ~200uA of current (the DAC can source 700uA max). The channel is routed to the backplane nonetheless.
|}

===Pinout Table===
{| cellpadding=3 border=1 |
| '''Pin #'''
| '''Net Name'''
| '''Description'''
|-
| 1
| CLK_5MHZ
| SPI clock (SCLK), from FPGA Shared with temperature sensor
|-
| 2
| DIN
| SPI data in, from FPGA Shared with temperature sensor ''Currently wired wrong''
|-
| 3
| CS
| SPI chip select
|-
| 4
| AGND
|
|-
| 5
| +5V
| Power pin
|-
| 6
| +5V
| Power pin
|-
| 7
| AD7928/REF_IN
| +2.5V reference, set by VR2
|-
| 8
| AGND
|
|-
| 9-16
| VIN[7:0]
| See [[#Channel Descriptions | ADC Channel Descriptions]]
|-
| 17
| AGND
|
|-
| 18
| DOUT
| SPI data out ''Currently wired incorrectly''
|-
| 19
| +3.3V
| VDRIVE, powers the SPI logic
|-
| 20
| AGND
|
|}

== Ethernet Controller ==
The board uses a Silicon Laboratories CP2201, 28-pin, ethernet controller. The CP2201 is located just above the FPGA, and is labelled U2.

=== Power Details ===
The CP2201 uses only +3.3V, which is supplied by the +3.3V power plane and regulated by VR1. Appropriate decoupling capacitors can be found near the CP2201.

=== Ethernet Jack ===
To the right of the CP2201 is a Pulse J0011D21NL ethernet jack, labelled J1. This jack has a built-in 1:1 inductive coupling. For best results, connect this jack to a nearby ethernet switch. The jack may also be connected directly to a computer using a crossover cable. Though auto-crossover is not supported by the CP2201, if the computer's NIC supports it, a crossover cable is not necessary to connect directly to a computer.

=== Crystal Oscillator ===
The CP2201 is responsible for driving the 20MHz crystal oscillator. This oscillator clocks both the CP2201 and the FPGA. The crystal oscillator can be found above the right corner of the FPGA. It can be identified by its four surface mount pads and roughly .3" length. It is labelled Y1, though this label is not visible after the oscillator is soldered on. The CP2201 uses an inverting driver to excite the crystal. The output of hte crystal is then sent to the CP2201 and the FPGA.

=== Bus Format and Multiplexing ===
The 28-pin CP2201 used on the board only supports multiplexed operation. This means that both address and data information is passed over the same set of 8 traces. Hence, these traces are referred to as the address/data (AD) bus. A separate address line enable (ALE) trace prevents collisions from occuring on these traces. The communication protocol used is the Intel format. See the CP2201's datasheet for more information about this.

=== Pinout Table ===

Digital control board documentation

2009-06-16T16:10:11Z

Underwood: /* ADC */ added pinout

Digital control board documentation

2009-06-16T15:56:57Z

Underwood: /* Channel Mapping */

Digital control board documentation

2009-06-16T15:55:52Z

Underwood: /* Channel Mapping */ clarified DACHEALTH

Digital control board documentation

2009-06-16T15:53:47Z

Underwood: /* Channel Descriptions */ added DACHealth