Running: C:\Xilinx\14.6\ISE_DS\ISE\bin\nt64\unwrapped\fuse.exe -intstyle ise -incremental -o C:/Users/Richard Jones/Documents/GlueX/Tagger/Electronics/FPGA/TotalTest/FPGA_test_isim_beh.exe -prj C:/Users/Richard Jones/Documents/GlueX/Tagger/Electronics/FPGA/TotalTest/FPGA_test_beh.prj work.FPGA_test 
ISim P.68d (signature 0x7708f090)
Number of CPUs detected in this system: 8
Turning on mult-threading, number of parallel sub-compilation jobs: 16 
Determining compilation order of HDL files
Parsing VHDL file "C:/Users/Richard Jones/Documents/GlueX/Tagger/Electronics/FPGA/TotalTest/../Includes.vhd" into library FPGA_BasicComp
Parsing VHDL file "C:/Users/Richard Jones/Documents/GlueX/Tagger/Electronics/FPGA/TotalTest/Eth_emulator/RxRegs.vhd" into library work
Parsing VHDL file "C:/Users/Richard Jones/Documents/GlueX/Tagger/Electronics/FPGA/TotalTest/Eth_emulator/FileWrite.vhd" into library work
Parsing VHDL file "C:/Users/Richard Jones/Documents/GlueX/Tagger/Electronics/FPGA/TotalTest/Eth_emulator/FileRead.vhd" into library work
Parsing VHDL file "C:/Users/Richard Jones/Documents/GlueX/Tagger/Electronics/FPGA/TotalTest/../Status/GetTempVal.vhd" into library FPGA_BasicComp
Parsing VHDL file "C:/Users/Richard Jones/Documents/GlueX/Tagger/Electronics/FPGA/TotalTest/../Status/GetADCval.vhd" into library FPGA_BasicComp
Parsing VHDL file "C:/Users/Richard Jones/Documents/GlueX/Tagger/Electronics/FPGA/TotalTest/../FPGA_config.vhd" into library FPGA_BasicComp
Parsing VHDL file "C:/Users/Richard Jones/Documents/GlueX/Tagger/Electronics/FPGA/TotalTest/../Ethernet/Transmitter/WriteSpacket.vhd" into library FPGA_BasicComp
Parsing VHDL file "C:/Users/Richard Jones/Documents/GlueX/Tagger/Electronics/FPGA/TotalTest/../Ethernet/Transmitter/WriteDpacket.vhd" into library FPGA_BasicComp
Parsing VHDL file "C:/Users/Richard Jones/Documents/GlueX/Tagger/Electronics/FPGA/TotalTest/../Ethernet/Reset/MACaddrLoad.vhd" into library FPGA_BasicComp
Parsing VHDL file "C:/Users/Richard Jones/Documents/GlueX/Tagger/Electronics/FPGA/TotalTest/../Ethernet/Receiver/ReadPpacket.vhd" into library FPGA_BasicComp
Parsing VHDL file "C:/Users/Richard Jones/Documents/GlueX/Tagger/Electronics/FPGA/TotalTest/Temp_emulator/Temp_shift.vhd" into library work
Parsing VHDL file "C:/Users/Richard Jones/Documents/GlueX/Tagger/Electronics/FPGA/TotalTest/Temp_emulator/Temp_error.vhd" into library work
Parsing VHDL file "C:/Users/Richard Jones/Documents/GlueX/Tagger/Electronics/FPGA/TotalTest/Eth_emulator/Regs.vhd" into library work
Parsing VHDL file "C:/Users/Richard Jones/Documents/GlueX/Tagger/Electronics/FPGA/TotalTest/DAC_emulator/DAC_shifter.vhd" into library work
Parsing VHDL file "C:/Users/Richard Jones/Documents/GlueX/Tagger/Electronics/FPGA/TotalTest/DAC_emulator/DAC_register.vhd" into library work
Parsing VHDL file "C:/Users/Richard Jones/Documents/GlueX/Tagger/Electronics/FPGA/TotalTest/DAC_emulator/DAC_follow.vhd" into library work
Parsing VHDL file "C:/Users/Richard Jones/Documents/GlueX/Tagger/Electronics/FPGA/TotalTest/DAC_emulator/DAC_demux.vhd" into library work
Parsing VHDL file "C:/Users/Richard Jones/Documents/GlueX/Tagger/Electronics/FPGA/TotalTest/ADC_emulator/ADC_shift_out16.vhd" into library work
Parsing VHDL file "C:/Users/Richard Jones/Documents/GlueX/Tagger/Electronics/FPGA/TotalTest/ADC_emulator/ADC_shift_in16.vhd" into library work
Parsing VHDL file "C:/Users/Richard Jones/Documents/GlueX/Tagger/Electronics/FPGA/TotalTest/ADC_emulator/ADC_error.vhd" into library work
Parsing VHDL file "C:/Users/Richard Jones/Documents/GlueX/Tagger/Electronics/FPGA/TotalTest/ADC_emulator/ADC_demux.vhd" into library work
Parsing VHDL file "C:/Users/Richard Jones/Documents/GlueX/Tagger/Electronics/FPGA/TotalTest/ADC_emulator/ADC_creg.vhd" into library work
Parsing VHDL file "C:/Users/Richard Jones/Documents/GlueX/Tagger/Electronics/FPGA/TotalTest/../Status/Querier.vhd" into library FPGA_BasicComp
Parsing VHDL file "C:/Users/Richard Jones/Documents/GlueX/Tagger/Electronics/FPGA/TotalTest/../SerialOut.vhd" into library FPGA_BasicComp
Parsing VHDL file "C:/Users/Richard Jones/Documents/GlueX/Tagger/Electronics/FPGA/TotalTest/../Ethernet/Transmitter/Transmitter.vhd" into library FPGA_BasicComp
Parsing VHDL file "C:/Users/Richard Jones/Documents/GlueX/Tagger/Electronics/FPGA/TotalTest/../Ethernet/Transceiver/Transceiver.vhd" into library FPGA_BasicComp
Parsing VHDL file "C:/Users/Richard Jones/Documents/GlueX/Tagger/Electronics/FPGA/TotalTest/../Ethernet/Reset/ResetSoft.vhd" into library FPGA_BasicComp
Parsing VHDL file "C:/Users/Richard Jones/Documents/GlueX/Tagger/Electronics/FPGA/TotalTest/../Ethernet/Reset/ResetHard.vhd" into library FPGA_BasicComp
Parsing VHDL file "C:/Users/Richard Jones/Documents/GlueX/Tagger/Electronics/FPGA/TotalTest/../Ethernet/Receiver/Receiver.vhd" into library FPGA_BasicComp
Parsing VHDL file "C:/Users/Richard Jones/Documents/GlueX/Tagger/Electronics/FPGA/TotalTest/../Ethernet/INTCatcher/INTCatcher.vhd" into library FPGA_BasicComp
Parsing VHDL file "C:/Users/Richard Jones/Documents/GlueX/Tagger/Electronics/FPGA/TotalTest/../DAC_v2/DAC_writer.vhd" into library FPGA_BasicComp
Parsing VHDL file "C:/Users/Richard Jones/Documents/GlueX/Tagger/Electronics/FPGA/TotalTest/../DAC_v2/DAC_controller.vhd" into library FPGA_BasicComp
Parsing VHDL file "C:/Users/Richard Jones/Documents/GlueX/Tagger/Electronics/FPGA/TotalTest/Temp_emulator/Temp_emulator.vhd" into library work
Parsing VHDL file "C:/Users/Richard Jones/Documents/GlueX/Tagger/Electronics/FPGA/TotalTest/Eth_emulator/Eth_emulator.vhd" into library work
Parsing VHDL file "C:/Users/Richard Jones/Documents/GlueX/Tagger/Electronics/FPGA/TotalTest/DAC_emulator/DAC_emulator.vhd" into library work
Parsing VHDL file "C:/Users/Richard Jones/Documents/GlueX/Tagger/Electronics/FPGA/TotalTest/ADC_emulator/ADC_emulator.vhd" into library work
Parsing VHDL file "C:/Users/Richard Jones/Documents/GlueX/Tagger/Electronics/FPGA/TotalTest/../FPGA_main.vhd" into library work
Parsing VHDL file "C:/Users/Richard Jones/Documents/GlueX/Tagger/Electronics/FPGA/TotalTest/FPGA_test.vhd" into library work
Starting static elaboration
Completed static elaboration
Compiling package standard
Compiling package std_logic_1164
Compiling package std_logic_arith
Compiling package std_logic_unsigned
Compiling package textio
Compiling package std_logic_textio
Compiling package vcomponents
Compiling package basiccomp
Compiling package maincomp
Compiling package fpga_config
Compiling package vital_timing
Compiling package vital_primitives
Compiling package vpkg
Compiling architecture ibufg_v of entity IBUFG [\IBUFG("DONT_CARE","0",true,"DEF...]
Compiling architecture dcm_sp_clock_divide_by_2_v of entity dcm_sp_clock_divide_by_2 [dcm_sp_clock_divide_by_2_default]
Compiling architecture dcm_sp_maximum_period_check_v of entity dcm_sp_maximum_period_check [\dcm_sp_maximum_period_check("*"...]
Compiling architecture dcm_sp_maximum_period_check_v of entity dcm_sp_maximum_period_check [\dcm_sp_maximum_period_check("*"...]
Compiling architecture dcm_sp_clock_lost_v of entity dcm_sp_clock_lost [dcm_sp_clock_lost_default]
Compiling architecture dcm_sp_v of entity DCM_SP [\DCM_SP(true,"*",true,false,2.0,...]
Compiling architecture bufg_v of entity BUFG [bufg_default]
Compiling architecture startup_spartan3a_v of entity STARTUP_SPARTAN3A [startup_spartan3a_default]
Compiling package std_logic_signed
Compiling architecture ramb16bwe_v of entity RAMB16BWE [\RAMB16BWE(18,18,"00000000000000...]
Compiling architecture ramb16bwe_s18_s18_v of entity RAMB16BWE_S18_S18 [\RAMB16BWE_S18_S18("000000000000...]
Compiling architecture behavioral of entity MACaddrLoad [macaddrload_default]
Compiling architecture behavioral of entity ResetHard [resethard_default]
Compiling architecture behavioral of entity ResetSoft [resetsoft_default]
Compiling architecture behavioral of entity WriteDpacket [writedpacket_default]
Compiling architecture behavioral of entity WriteSpacket [writespacket_default]
Compiling architecture behavioral of entity Transmitter [transmitter_default]
Compiling architecture behavioral of entity GetTempVal [gettempval_default]
Compiling architecture behavioral of entity GetADCval [getadcval_default]
Compiling architecture behavioral of entity Querier [querier_default]
Compiling architecture behavioral of entity ReadPpacket [readppacket_default]
Compiling architecture behavioral of entity Receiver [receiver_default]
Compiling architecture behavioral of entity DAC_writer [dac_writer_default]
Compiling architecture behavioral of entity DAC_controller [dac_controller_default]
Compiling architecture behavioral of entity INTCatcher [intcatcher_default]
Compiling architecture behavioral of entity Transceiver [transceiver_default]
Compiling architecture behavioral of entity SerialOut [serialout_default]
Compiling architecture ramb16bwe_v of entity RAMB16BWE [\RAMB16BWE(9,9,"0000000000000000...]
Compiling architecture behavioral of entity SerialOutFIFO [serialoutfifo_default]
Compiling architecture behavioral of entity FPGA_main [fpga_main_default]
Compiling package numeric_std
Compiling architecture response of entity write_file [write_file_default]
Compiling architecture stimulus of entity read_file [read_file_default]
Compiling architecture behavioral of entity RxRegs [rxregs_default]
Compiling architecture behavioral of entity Regs [regs_default]
Compiling architecture behavioral of entity Eth_emulator [eth_emulator_default]
Compiling architecture behavioral of entity Temp_error [temp_error_default]
Compiling architecture behavioral of entity Temp_shift [temp_shift_default]
Compiling architecture architectural of entity Temp_emulator [temp_emulator_default]
Compiling architecture behavioral of entity ADC_creg [adc_creg_default]
Compiling architecture behavioral of entity ADC_demux [adc_demux_default]
Compiling architecture behavioral of entity ADC_error [adc_error_default]
Compiling architecture behavioral of entity ADC_shift_in16 [adc_shift_in16_default]
Compiling architecture behavioral of entity ADC_shift_out16 [adc_shift_out16_default]
Compiling architecture architectural of entity ADC_emulator [adc_emulator_default]
Compiling architecture behavioral of entity DAC_demux [dac_demux_default]
Compiling architecture behavioral of entity DAC_follow [dac_follow_default]
Compiling architecture behavioral of entity DAC_shifter [dac_shifter_default]
Compiling architecture behavioral of entity DAC_register [dac_register_default]
Compiling architecture architectural of entity DAC_emulator [dac_emulator_default]
Compiling architecture behavioral of entity fpga_test
Time Resolution for simulation is 1ps.
Waiting for 1 sub-compilation(s) to finish...
Compiled 112 VHDL Units
Built simulation executable C:/Users/Richard Jones/Documents/GlueX/Tagger/Electronics/FPGA/TotalTest/FPGA_test_isim_beh.exe
Fuse Memory Usage: 76668 KB
Fuse CPU Usage: 1933 ms