| FPGA_test Project Status (01/01/2014 - 16:56:21) | |||
| Project File: | TotalTest.xise | Parser Errors: | No Errors |
| Module Name: | FPGA_test | Implementation State: | Synthesized |
| Target Device: | xc3s50a-4vq100 |
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X 27 Errors (0 new) |
| Product Version: | ISE 14.6 |
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No Warnings |
| Design Goal: | Balanced |
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| Design Strategy: | Xilinx Default (unlocked) |
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| Environment: | System Settings |
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| Detailed Reports | [-] | |||||
| Report Name | Status | Generated | Errors | Warnings | Infos | |
| Synthesis Report | Current | Wed Jan 1 16:56:20 2014 | X 27 Errors (0 new) | 0 | 0 | |
| Translation Report | ||||||
| Map Report | ||||||
| Place and Route Report | ||||||
| Power Report | ||||||
| Post-PAR Static Timing Report | ||||||
| Bitgen Report | ||||||
| Secondary Reports | [-] | ||
| Report Name | Status | Generated | |
| ISIM Simulator Log | Current | Thu Jan 2 01:00:26 2014 | |