----------------------------------------------------------------------------------
-- Company: University of Connecticut
-- Engineer: Igor Senderovich
-- 
-- Create Date:    14:48:00 09/24/2007 
-- Design Name: 
-- Module Name:    Querier_coord - Behavioral 
-- Description:    Queries the ADC and Temperature sensor
--		   and stores the results in RAM
----------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;

library FPGA_BasicComp;
use FPGA_BasicComp.BasicComp.all;

Entity Querier is
    Port ( Clk : in std_logic;
	   Go : in std_logic;
	   Done : out std_logic;
	   -- SPI bus (with ADC and Temp sensors) lines
	   SPI_SCLK : in std_logic;
	   SPI_T_CE : out std_logic;
	   SPI_A_CS_low : out std_logic;
	   SPI_SDI_tri : out std_logic;
	   SPI_SDO : in std_logic;
	   -- RAM control lines
	   RAM_EN : out std_logic;
	   RAM_ADDR_tri : out std_logic_vector (9 downto 0);
	   RAM_WE_tri : out std_logic_vector (1 downto 0);
	   RAM_DI_tri : out std_logic_vector (15 downto 0);
	   RAM_DO : in std_logic_vector (15 downto 0));
	   -- Serial port
	   --Ser_Go : out std_logic;
	   --Ser_Done : in std_logic;
	   --Ser_D_tri : out std_logic_vector (7 downto 0);
	   --Debug : out std_logic;
end Querier;

architecture behavioral of Querier is

	component GetTempVal is
	    Port ( Clk : in std_logic;
           	   Go : in std_logic;
           	   Done : out std_logic;
           	   Q : out std_logic_vector (9 downto 0);
		   --SPI bus
		   SCLK : in std_logic;
           	   T_CE : out std_logic;
           	   SDI_tri : out std_logic;
           	   SDO : in std_logic);
	end component;

	component GetADCval is
	    Port ( Clk : in std_logic;
        	   Go : in std_logic;
        	   Done : out std_logic;
        	   Addr : in std_logic_vector (4 downto 0);
        	   Q : out std_logic_vector (11 downto 0);
		   --SPI bus
		   SCLK : in std_logic;
           	   A_CS_low : out std_logic;
           	   SDI_tri : out std_logic;
           	   SDO : in std_logic);
	end component;

	type stage_t is (S0,S1,S2,S3);
	signal stage : stage_t := S0;

	signal Done_reg : std_logic := '0';
	signal Go_Temp : std_logic := '0';
	signal Done_Temp : std_logic := '0';
	signal ADC_address : std_logic_vector (4 downto 0);
	signal ADC_cycle_Go : std_logic := '0';
	signal ADC_cycle_Done : std_logic;
	signal ADC_DIN_tri : std_logic;
	signal Temp_value : std_logic_vector(9 downto 0);
	signal ADC_value : std_logic_vector(11 downto 0);
	signal RAM_EN_reg : std_logic := '0';
	signal RAM_ADDR_reg : std_logic_vector (9 downto 0) := (others => '0');
	signal RAM_WE_reg : std_logic_vector (1 downto 0) := (others => '0');
	signal RAM_DI_reg : std_logic_vector (15 downto 0) := (others => '0');
	--signal Ser_Go_reg : std_logic := '0';
	--signal Ser_D_reg : std_logic_vector (7 downto 0) := (others => '0');
	--signal Debug_reg : std_logic := '0';
begin
	GetTempVal_inst : GetTempVal
	port map ( Clk => Clk,
		   Go => Go_Temp,
		   Done => Done_Temp,
		   Q => Temp_value,
        	   SCLK => SPI_SCLK,
		   T_CE => SPI_T_CE,
        	   SDI_tri => SPI_SDI_tri,
		   SDO => SPI_SDO
	);

	GetADCval_inst : GetADCval
	port map ( Clk => Clk,
        	   Go => ADC_cycle_Go,
		   Done => ADC_cycle_Done,
		   Addr => ADC_address,
		   Q => ADC_value,
        	   SCLK => SPI_SCLK,
        	   A_CS_low => SPI_A_CS_low,
        	   SDI_tri => SPI_SDI_tri,
        	   SDO => SPI_SDO
	);

	RAM_EN <= RAM_EN_reg;
	RAM_ADDR_tri <= RAM_ADDR_reg when (RAM_EN_reg = '1') else (others => 'Z');
	RAM_WE_tri <= RAM_WE_reg when (RAM_EN_reg = '1') else (others => 'Z');
	RAM_DI_tri <= RAM_DI_reg when (RAM_EN_reg = '1') else (others => 'Z');

	Sequencer : process (Clk)
	begin
		if rising_edge(Clk) then
			stage <= stage;
			ADC_address <= (others => '0');
			ADC_cycle_Go <= '0';
			Go_Temp <= '0';
			Done_reg <= '0';
			-- Disable the RAM lines when not in use
			RAM_EN_reg <= '0';
			RAM_WE_reg <= RAM_WE_reg;
			RAM_ADDR_reg <= RAM_ADDR_reg;
			RAM_DI_reg <= RAM_DI_reg;
			-- Disable the serial lines when not in use
			--Ser_Go_reg <= '0';
			--Ser_D_reg <= (others => '0');
			--Debug_reg <= (others => '0');

			case stage is
			    when S0 =>
				if (Go = '1') then
					stage <= S1;
				end if;
			    when S1 =>
				RAM_EN_reg <= '1';
				RAM_WE_reg <= "11";
				RAM_ADDR_reg <= (others => '0');
				RAM_DI_reg <= "000000" & Temp_value;
				Go_Temp <= not Done_Temp;
				if (Done_Temp = '1') then
					ADC_address <= "00000";
					stage <= S2;
				end if;
			    when S2 =>
				ADC_address <= ADC_address;
				RAM_EN_reg <= '1';
				RAM_WE_reg <= "11";
				RAM_ADDR_reg <= "00001" & ADC_address;
				RAM_DI_reg <= X"0" & ADC_value;
				ADC_cycle_Go <= not ADC_cycle_Done;
				if (ADC_cycle_Go = '1' and ADC_cycle_Done = '1') then
					ADC_address <= ADC_address + 1;
					if (ADC_address = "01111") then
						stage <= S3;
					end if;
				end if;
			    when S3 =>
				if (Go = '1') then
					Done_reg <= '1';
				else
					stage <= S0;
				end if;
			end case;
		else
			stage <= stage;
			ADC_cycle_Go <= ADC_cycle_Go;
			ADC_address <= ADC_address;
			RAM_WE_reg <= RAM_WE_reg;
			RAM_ADDR_reg <= RAM_ADDR_reg;
			RAM_DI_reg <= RAM_DI_reg;
			RAM_EN_reg <= RAM_EN_reg;
			Go_Temp <= Go_Temp;
			Done_reg <= Done_reg;
			--Ser_Go_reg <= Ser_Go_reg;
			--Ser_D_reg <= Ser_D_reg;
			--Debug_reg <= Debug_reg;
		end if;
	end process;

	--Ser_Go <= Ser_Go_reg;
	--Ser_D_tri <= Ser_D_reg when (Ser_Go_reg = '1') else (others => 'Z');
	--Debug <= Debug_reg;

	Done <= Done_reg;

end behavioral;