----------------------------------------------------------------------------------
-- Company: University of Connecticut
-- Engineer: Igor Senderovich
-- 
-- Create Date:    10/2009 
-- Design Name:    GetTempVal
-- Target Devices: Xilinx Spartan-3A
-- Tool versions:  Xilinx ISE 11.1
-- Description:    Fetches the 10-bit value from the temperature sensor chip
----------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;

library FPGA_BasicComp;
use FPGA_BasicComp.BasicComp.all;

entity GetTempVal is
    Port ( Clk : in std_logic;
           Go : in std_logic;
           Done : out std_logic;
           Q : out std_logic_vector (9 downto 0);
	   --SPI bus
	   SCLK : in std_logic;
           T_CE : out std_logic;
           SDI_tri : out std_logic;
           SDO : in std_logic);
end GetTempVal;

architecture behavioral of GetTempVal is

	type stage_t is (S0,S1,S2,S3);
	signal stage : stage_t := S0;

	signal chip_select : std_logic := '0';
	signal counter_4b : std_logic_vector (3 downto 0) := (others => '0');
	signal result : std_logic_vector (15 downto 0) := (others => '0');
	signal Done_reg : std_logic := '0';
begin
	T_CE <= chip_select;
	SDI_tri <= '0' when (Go = '1') else 'Z';
	
	Sequencer : process (Clk)
		variable bit_var : integer range 0 to 15;
	begin
		if (falling_edge(Clk) and SCLK = '0') then
			result <= result;
			counter_4b <= (others => '0');
			chip_select <= '0';
			Done_reg <= '0';

			bit_var := conv_integer(counter_4b);

			case stage is
			    when S0 =>
				if (Go = '1') then
					stage <= S1;
				end if;
			    when S1 =>
				chip_select <= '1';
				counter_4b <= X"F";
				stage <= S2;
			    when S2 =>
				chip_select <= '1';
				counter_4b <= counter_4b - 1;
				result(bit_var) <= SDO;
				if (counter_4b = X"0") then
					stage <= S3;
				end if;
			    when S3 =>
				if (Go = '1') then
					Done_reg <= '1';
				else
					stage <= S0;
				end if;	
			end case;
		else
			result <= result;
			chip_select <= chip_select;
			counter_4b <= counter_4b;
			Done_reg <= Done_reg;
		end if;

	end process;

	Q <= result(14 downto 5);
	
	Done <= Done_reg;

end behavioral;