----------------------------------------------------------------------------------
-- Company: University of Connecticut
-- Engineer: Igor Senderovich
-- 
-- Create Date:    10/2009 
-- Design Name:    GetADCval
-- Target Devices: Xilinx Spartan-3A
-- Tool versions:  Xilinx ISE 11.1
-- Description:    Fetches the 12bit value from specified channel on ADC
----------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.ALL;
use IEEE.std_logic_arith.ALL;
use IEEE.std_logic_unsigned.ALL;

library FPGA_BasicComp;
use FPGA_BasicComp.BasicComp.all;

entity GetADCval is
    port ( Clk : in std_logic;
           Go : in std_logic;
	   Done : out std_logic;
           Addr : in std_logic_vector (4 downto 0);
           Q : out std_logic_vector (11 downto 0);
	   --SPI bus
	   SCLK : in std_logic;
           A_CS_low : out std_logic;
           SDI_tri : out std_logic;
           SDO : in std_logic);
end GetADCval;

architecture behavioral of GetADCval is

	type stage_t is (S0,S1,S2,S3,S4);
	signal stage : stage_t := S0;

	signal counter_8b : std_logic_vector (7 downto 0) := (others => '0');
	signal result : std_logic_vector (15 downto 0) := (others => '0');
	signal chip_select : std_logic := '0';
	signal Done_reg : std_logic := '0';
	signal SDI_reg : std_logic := '0';

	--control bits in the ADC chip control register
	constant write_bit : std_logic := '1';
	constant seq_bit : std_logic := '0';
	constant power_bits : std_logic_vector (1 downto 0) := "11";
	constant shadow_bit : std_logic := '0';
	constant weak_bit : std_logic := '0';
	constant range_bit : std_logic := '0';
	constant coding_bit : std_logic := '1';
	signal control_reg : std_logic_vector (15 downto 0) := (others => '0');
begin
	control_reg <= write_bit & seq_bit & Addr(3 downto 0) &
			power_bits & shadow_bit &
			weak_bit & range_bit &
			coding_bit & "0000";
	SDI_tri <= (SDI_reg or Addr(4)) when (Go = '1') else 'Z';
	A_CS_low <= not chip_select;

	Sequencer : process (Clk) is
		variable bit_var : integer range 0 to 15;
	begin
		if rising_edge(SCLK) then
			stage <= stage;
			counter_8b <= (others => '0');
			result <= result;
			Done_reg <= '0';
           		SDI_reg <= '0';
			chip_select <= '0';

			bit_var := conv_integer(counter_8b);

			case stage is
			    when S0 =>
				if (Go = '1') then
					counter_8b <= X"0F";
					stage <= S1;
				end if;
			    when S1 =>
				chip_select <= '1';
           			SDI_reg <= control_reg(bit_var);
				counter_8b <= counter_8b - 1;
				if (counter_8b = X"00") then
					counter_8b <= X"64";
					stage <= S2;
				end if;
			    when S2 =>	-- allow 10us for S/H to settle
				chip_select <= '0';
				counter_8b <= counter_8b - 1;
				if (counter_8b = X"00") then
					counter_8b <= X"0F";
					stage <= S3;
				end if;
			    when S3 =>
				chip_select <= '1';
				counter_8b <= counter_8b - 1;
				result(bit_var) <= SDO;
				if (counter_8b = X"00") then
					stage <= S4;
				end if;
			    when S4 =>
				if (Go = '1') then
					Done_reg <= '1';
				else
					stage <= S0;
				end if;
			end case;
		else
			stage <= stage;
			counter_8b <= counter_8b;
			result <= result;
			Done_reg <= Done_reg;
           		SDI_reg <= SDI_reg;
			chip_select <= chip_select;
			result <= result;
		end if;
	end process;

	Q <= result(11 downto 0);
	
	Done <= Done_reg;

end behavioral;