----------------------------------------------------------------------------------
-- Company: University of Connecticut
-- Engineer:  Igor Senderovich
-- 
-- Create Date:    15:57:51 08/07/2009 
-- Design Name: 
-- Module Name:    Includes
-- Description:    Define the packages of custom components for the project
----------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.All;

package MainComp is

	component ResetHard is
	    port ( Clk : in  std_logic;
		   Go : in std_logic;
		   Done : out std_logic;
		   Eth_Rst_low : inout std_logic;
		   Eth_INT_low : in std_logic;
		   DAC_Rst : out std_logic;

		   --RAM control lines
		   RAM_EN : out std_logic;
		   RAM_ADDR_tri : out std_logic_vector (9 downto 0);
		   RAM_WE_tri : out std_logic_vector (1 downto 0);
		   RAM_DI_tri : out std_logic_vector (15 downto 0);
		   RAM_DO : in std_logic_vector (15 downto 0);

		  --Transceiver control lines
		   TxRx_Go : out  std_logic;
           	   TxRx_A_tri : out  std_logic_vector (7 downto 0);
           	   TxRx_D_tri : out  std_logic_vector (7 downto 0);
           	   TxRx_Rd_tri : out  std_logic;
		   TxRx_Q : in  std_logic_vector (7 downto 0);
		   TxRx_Done : in  std_logic;

		  --Interrupt catcher control lines
		   INT_Go : out std_logic;
		   INT_Mask_tri : out std_logic_vector (15 downto 0);
		   INT_Found : in std_logic_vector (15 downto 0);
		   INT_Done : in std_logic);

		   -- Serial port control lines
 		   --Ser_Go : out std_logic;
		   --Ser_Done : in std_logic;
  		   --Ser_D_tri : out std_logic_vector (7 downto 0);
  		   --Debug : out std_logic);
	end component;

	component ResetSoft is
	    port ( Clk : in  std_logic;
		   Go : in std_logic;
		   Done : out std_logic;
		   DAC_Rst : out std_logic;

		   --RAM control lines
		   RAM_EN : out std_logic;
		   RAM_ADDR_tri : out std_logic_vector (9 downto 0);
		   RAM_WE_tri : out std_logic_vector (1 downto 0);
		   RAM_DI_tri : out std_logic_vector (15 downto 0);
		   RAM_DO : in std_logic_vector (15 downto 0);

		   --Transceiver control lines
		   TxRx_Go : out  std_logic;
           	   TxRx_Rd_tri : out  std_logic;
           	   TxRx_A_tri : out  std_logic_vector (7 downto 0);
           	   TxRx_D_tri : out  std_logic_vector (7 downto 0);
		   TxRx_Q : in  std_logic_vector (7 downto 0);
		   TxRx_Done : in  std_logic);

		   -- Serial port control lines
		   --Ser_Go : out std_logic;
		   --Ser_Done : in std_logic;
  		   --Ser_D_tri : out std_logic_vector (7 downto 0));
  		   --Debug : out std_logic);
	end component;

	component Transceiver is
    	    port ( Clk : in  std_logic;
		   Go : in  std_logic;
		   Done : out std_logic;
           	   Rd : in  std_logic;
           	   A : in  std_logic_vector (7 downto 0);
           	   D : in  std_logic_vector (7 downto 0);
		   Q : out std_logic_vector (7 downto 0);

		   -- MuxIntel lines ------------------------
		   ALE : out std_logic;
		   AD  : inout std_logic_vector (7 downto 0);
		   RD_low : out std_logic;
		   WR_low : out std_logic;
		   CS_low : out std_logic);
	end component;

	component Transmitter is
	    port ( Clk : in  std_logic;
		   Go : in std_logic;
		   Done : out std_logic;
		   LocStamp : in std_logic_vector (7 downto 0);
		   PktType : in std_logic_vector (7 downto 0);

		   --RAM control lines
		   RAM_EN : out std_logic;
		   RAM_ADDR_tri : out std_logic_vector (9 downto 0);
		   RAM_WE_tri : out std_logic_vector (1 downto 0);
		   RAM_DI_tri : out std_logic_vector (15 downto 0);
		   RAM_DO : in std_logic_vector (15 downto 0);

		   --Transceiver control lines
           	   TxRx_Go : out  std_logic;
           	   TxRx_Rd_tri : out  std_logic;
           	   TxRx_A_tri : out  std_logic_vector (7 downto 0);
           	   TxRx_D_tri : out  std_logic_vector (7 downto 0);
		   TxRx_Q : in std_logic_vector (7 downto 0);
           	   TxRx_Done : in  std_logic;

		   --Interrupt catcher control lines
		   INT_Go : out std_logic;
		   INT_Mask_tri : out std_logic_vector (15 downto 0);
		   INT_Found : in std_logic_vector (15 downto 0);
		   INT_Done : in std_logic);

		   -- Serial port control lines
 		   --Ser_Go : out std_logic;
		   --Ser_Done : in std_logic;
  		   --Ser_D_tri : out std_logic_vector (7 downto 0);
  		   --Debug : out std_logic);
	end component;

	component Receiver is
	    port ( Clk : in  std_logic;
		   Go : in std_logic;
		   Done : out std_logic;
		   LocStamp : in std_logic_vector (7 downto 0);
		   PktType : out std_logic_vector (7 downto 0);

		   --RAM control lines
		   RAM_EN : out std_logic;
		   RAM_ADDR_tri : out std_logic_vector (9 downto 0);
		   RAM_WE_tri : out std_logic_vector (1 downto 0);
		   RAM_DI_tri : out std_logic_vector (15 downto 0);
		   RAM_DO : in std_logic_vector (15 downto 0);

		   --Transceiver control lines
		   TxRx_Go : out  std_logic;
           	   TxRx_Rd_tri : out  std_logic;
           	   TxRx_A_tri : out  std_logic_vector (7 downto 0);
           	   TxRx_D_tri : out  std_logic_vector (7 downto 0);
		   TxRx_Q : in  std_logic_vector (7 downto 0);
		   TxRx_Done : in  std_logic);

		   -- Serial port control lines
		   --Ser_Go : out std_logic;
		   --Ser_Done : in std_logic;
  		   --Ser_D_tri : out std_logic_vector (7 downto 0));
  		   --Debug : out std_logic);
	end component;

	component Querier is
	    port ( Clk : in std_logic;
		   Go : in std_logic;
		   Done : out std_logic;

		   -- SPI bus (with ADC and Temp sensors) lines
		   SPI_SCLK : in std_logic;
		   SPI_T_CE : out std_logic;
		   SPI_A_CS_low	: out std_logic;
		   SPI_SDI_tri : out std_logic;
		   SPI_SDO : in std_logic;

		   --RAM control lines
		   RAM_EN : out std_logic;
		   RAM_ADDR_tri : out std_logic_vector (9 downto 0);
		   RAM_WE_tri : out std_logic_vector (1 downto 0);
		   RAM_DI_tri : out std_logic_vector (15 downto 0);
		   RAM_DO : in std_logic_vector (15 downto 0));

		   -- Serial port control lines
		   --Ser_Go : out std_logic;
		   --Ser_Done : in std_logic;
		   --Ser_D_tri : out std_logic_vector (7 downto 0));
  		   --Debug : out std_logic);
	end component;

	component DAC_writer is
	    port ( Clk : in  std_logic;
           	   Go : in  std_logic;
           	   Done : out  std_logic;

		   --RAM control lines
		   RAM_EN : out std_logic;
		   RAM_ADDR_tri : out std_logic_vector (9 downto 0);
		   RAM_WE_tri : out std_logic_vector (1 downto 0);
		   RAM_DI_tri : out std_logic_vector (15 downto 0);
		   RAM_DO : in std_logic_vector (15 downto 0);

		   --DAC_controller lines
		   DAC_control_Go : out std_logic;
		   DAC_control_Done : in std_logic;
		   DAC_Addr : out std_logic_vector (4 downto 0);
		   DAC_Code : out std_logic_vector (13 downto 0));

		   -- Serial port control lines
		   --Ser_Go : out std_logic;
		   --Ser_Done : in std_logic;
		   --Ser_D_tri : out std_logic_vector (7 downto 0));
  		   --Debug : out std_logic);
	end component;

	component DAC_controller
	    port ( Clk : in  std_logic;
		   Go : in  std_logic;
		   Done: out  std_logic;
		   Addr : in std_logic_vector (4 downto 0);
		   Code : in  std_logic_vector (13 downto 0);
		   SCLK : in std_logic;
		   SYNC_low : out  std_logic;
		   DIN : out  std_logic);
	end component;

	component INTCatcher is
	    port ( Clk : in  std_logic;
		   Go : in std_logic;
		   Done : out std_logic;
		   INT_low : in std_logic;
           	   Mask : in  std_logic_vector(15 downto 0);
		   Found : out  std_logic_vector(15 downto 0);

		   --Transceiver control lines
		   TxRx_Go : out std_logic;
           	   TxRx_A_tri : out std_logic_vector (7 downto 0);
           	   TxRx_Rd_tri : out std_logic;
		   TxRx_D_tri : out std_logic_vector (7 downto 0);
		   TxRx_Q : in  std_logic_vector (7 downto 0);
		   TxRx_Done : in  std_logic);

		   --Serial port control lines
 		   --Ser_Go : out std_logic;
		   --Ser_Done : in std_logic;
  		   --Ser_D_tri : out std_logic_vector (7 downto 0));
  		   --Debug : out std_logic);
	end component;

end package;

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.All;

package BasicComp is

	component SerialOut is
	    port ( Clk : in  std_logic;
		   Go : in std_logic;
		   Done : out std_logic;
        	   D : in  std_logic_vector (7 downto 0);
        	   Q : out  std_logic);
	end component;

	component SerialOutFIFO is
	    port ( Clk : in  std_logic;
		   Go  : in std_logic;
		   Done : out std_logic;
       		   D : in  std_logic_vector (7 downto 0);
       		   Q : out  std_logic);
	end component;

end package;