----------------------------------------------------------------------------------
-- Company: University of Connecticut
-- Engineer: Igor Senderovich
-- 
-- Create Date:    12:14:27 10/28/2009 
-- Module Name:    ConfigParam
-- Description:    FPGA firmware fixed parameter file
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;

package FPGA_config is

	type DAC_limit_table_t is array (0 to 31) of integer range 0 to 16383;
	type DAC_offset_table_t is array (0 to 31) of integer range -1023 to 1023;
	type DAC_channel_map_t is array (0 to 31) of integer range 0 to 31;

	-------------------------------------------------------
	-- IMPORTANT: the following sets the maximum allowed
	-- DAC output voltages. Conversion from voltage units:
	--   	DAC_limit = Vmax * 2^14/(Vref*50)
	-- original board design: Vref=3.3V
	-------------------------------------------------------
	--constant DAC_limit : integer := 7745;  -- = 78V @ Vref=3.3V
	--constant DAC_limit : integer := 4071;	 -- = 41V @ Vref=3.3V     
	--constant DAC_limit : integer := 13435; -- = 41V @ Vref=1.0V
	--constant DAC_limit : integer := 6554;	 -- = 20V @ Vref=1.0V
	--constant DAC_limit : integer := 8192;	 -- = 25V @ Vref=1.0V
	--constant DAC_limit : integer := 16383; -- = supply is the limit
	constant DAC_limit_table : DAC_limit_table_t
	   := (	7745, 7745, 7745, 7745, 7745, 7745, 7745, 7745, 7745, 7745,
		7745, 7745, 7745, 7745, 7745, 7745, 7745, 7745, 7745, 7745, 
		7745, 7745, 7745, 7745, 7745, 7745, 7745, 7745, 7745, 7745, 
	----------------------------------------------------------
	-- Here we set the DAC value that should be used to drive
	-- the GainMode level on the GainMode selector channel.
	-- As described above, this value depends on the Vref. 
	-- Also, due to systematics in the DAC at low voltages,
	-- greater than 5V values may be used, relying on the 
	-- Zener diode to limit the voltage at 5V
	-- (refer to the diode's spec sheet for maximum allowed)
	----------------------------------------------------------
		1092, 		-- = 11V @ Vref=3.3V
		-- 2294,	-- = 7V @ Vref=1.0V
		-- 695,		-- = 7V @ Vref=3.3V
		-- 2979,	-- = 30V @ Vref=3.3V
	----------------------------------------------------------
	-- This is a free unconnected DAC output that is connected
	-- to one of the inputs on the ADC, through a resistor
	-- divider network so that the full range of the DAC fits
	-- within the ADC full-scale count.  It is safe to let
	-- this output go to the full limit of the Vbias supply.
	----------------------------------------------------------
		16383 );

	-------------------------------------------------------
	-- Here we set the individual offsets that adjust for
	-- channel-dependent pedestals in each DAC channel.
	-- These must be customized for each board.
	-------------------------------------------------------
	constant DAC_offset_table : DAC_offset_table_t
	   := (	0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
		0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
		0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
		0, 0 );

	-------------------------------------------------------
	-- This is a wiring table that maps from the Vbias 
	-- channel number to the internal DAC channel id as
	-- marked in the DAC datasheet.  This scrambling was
	-- done to simplify the routing of traces on the pcb,
	-- with the requirement that the Vbias channel number
	-- ordering be sequential on the pinout of the
	-- external Eurocard connector.
	-------------------------------------------------------
	constant DAC_channel_map : DAC_channel_map_t
	    := (28, 24, 23, 22, 19, 20, 21, 13, 16,  7,
		12,  6,  2,  0,  4, 27, 30, 29, 26, 25,
		14, 17, 15, 11,  9,  8,  5, 10,  1,  3,
		18, 31);

	----------------------------------------------------------------
	-- setting dbShort shorts out the mandatory long waiting times
	-- e.g. during Eth. Ctrl physical layer startup
	-- Used only as a convenience for simulations.
	----------------------------------------------------------------
	constant dbShort : std_logic := '0';

end package FPGA_config;