----------------------------------------------------------------------------------
-- Company: University of Connecticut
-- Engineer: Igor Senderovich
-- 
-- Create Date:    04:14:41 10/01/2007 
-- Design Name: 
-- Module Name:    Transceiver - behavioral 
-- Description:	   Module for communicating with the Ethernet Controller across
--		   the Multiplexed Intel bus.
----------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;

entity Transceiver is
    port ( Clk : in std_logic;
           Go : in std_logic;
	   Done : out std_logic;
           Rd : in std_logic;
           A : in  std_logic_vector (7 downto 0);
           D : in  std_logic_vector (7 downto 0);
	   Q : out std_logic_vector (7 downto 0);
	   -- Transceiver lines ------------------------
	   ALE : out std_logic;
	   AD : inout std_logic_vector (7 downto 0);
	   RD_low : out std_logic;
	   WR_low : out std_logic;
	   CS_low : out std_logic);
end Transceiver;

architecture behavioral of Transceiver is

	type stage_t is (S0,S1,S2,S3,S4,S5,S6,S7,S8);
	signal stage : stage_t := S0;

	signal driving_AD : std_logic := '0';
	signal Done_reg : std_logic := '0';
	signal ALE_reg : std_logic := '0';
	signal AD_reg : std_logic_vector (7 downto 0) := (others => '0');
	signal RD_reg : std_logic := '0';
	signal WR_reg : std_logic := '0';
	signal Q_reg : std_logic_vector (7 downto 0) := (others => '0');
begin
	ALE <= ALE_reg;
	AD <= AD_reg when (driving_AD = '1') else (others => 'Z');
	RD_low <= not RD_reg;
	WR_low <= not WR_reg;
	CS_low <= '0';
	Q <= Q_reg;

	read_or_write_one_byte : process (Clk)
	begin
		if rising_edge(Clk) then
			stage <= stage;
			Done_reg <= '0';
			-- disable AD driver when not in use
			driving_AD <= '0';
			AD_reg <= AD_reg;
			ALE_reg <= '0';
			RD_reg <= '0';
			WR_reg <= '0';
			Q_reg <= Q_reg;

			case stage is
			    when S0 =>			-- idle
				if (Go = '1') then
					stage <= S1;
				end if;
			    when S1 =>			-- 0 ns
				driving_AD <= '1';
				ALE_reg <= '1';
				AD_reg <= A;
				stage <= S2;
			    when S2 =>			-- 50 ns
				driving_AD <= '1';
				ALE_reg <= '0';
				stage <= S3;
			    when S3 =>			-- 100 ns
				driving_AD <= not Rd;
				RD_reg <= Rd;
				WR_reg <= not Rd;
				AD_reg <= D;
				stage <= S4;
			    when S4 =>			-- 150 ns
				driving_AD <= not Rd;
				RD_reg <= Rd;
				WR_reg <= not Rd;
				AD_reg <= D;
				stage <= S5;
			    when S5 =>			-- 200 ns
				driving_AD <= not Rd;
				RD_reg <= Rd;
				WR_reg <= not Rd;
				AD_reg <= D;
				stage <= S6;
			    when S6 =>			-- 250 ns
				driving_AD <= not Rd;
				RD_reg <= Rd;
				WR_reg <= not Rd;
				AD_reg <= D;
				stage <= S7;
			    when S7 =>			-- 300 ns
				driving_AD <= not Rd;
				Q_reg <= AD;
				stage <= S8;
			    when S8 =>			-- 350 ns, done
				if (Go = '1') then
					Done_reg <= '1';
				else
					stage <= S0;
				end if;
			end case;
		else
			stage <= stage;
			Done_reg <= Done_reg;
			driving_AD <= driving_AD;
			AD_reg <= AD_reg;
			ALE_reg <= ALE_reg;
			RD_reg <= RD_reg;
			WR_reg <= WR_reg;
			Q_reg <= Q_reg;
		end if;
	end process;

	Done <= Done_reg;

end behavioral;