----------------------------------------------------------------------------------
-- Company: University of Connecticut
-- Engineer: Igor Senderovich
-- 
-- Create Date:    22:52:57 11/29/2007
-- Design Name: 
-- Module Name:    ResetSoft - behavioral 
-- Description:    Reset the DAC to its power-on condition, but do not reset
--		   the ethernet controller.  Currently does not perform any
--		   other functions, but can be augmented.  This function is
--		   entered after a "soft reset" packet is received, and the
--		   packet is still present in the current receive buffer upon
--		   entry below.  It must be discarded before exit.
----------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;

library FPGA_BasicComp;
use FPGA_BasicComp.BasicComp.all;

entity ResetSoft is
    Port ( Clk : in std_logic;
	   Go : in std_logic;
	   Done : out std_logic;
	   DAC_Rst : out std_logic;
	   -- RAM block access lines
	   RAM_EN : out std_logic;
	   RAM_ADDR_tri : out std_logic_vector (9 downto 0);
	   RAM_WE_tri : out std_logic_vector (1 downto 0);
	   RAM_DI_tri : out std_logic_vector (15 downto 0);
	   RAM_DO : in std_logic_vector (15 downto 0);
	   --Transceiver control lines
	   TxRx_Go : out  std_logic;
           TxRx_A_tri : out  std_logic_vector (7 downto 0);
           TxRx_D_tri : out  std_logic_vector (7 downto 0);
           TxRx_Rd_tri : out  std_logic;
	   TxRx_Q : in  std_logic_vector (7 downto 0);
	   TxRx_Done : in  std_logic);
	   --serial port lines
	   --Ser_Go : out std_logic;
	   --Ser_Done : in std_logic;
  	   --Ser_D_tri : out std_logic_vector (7 downto 0);
	   --Debug : out std_logic);
end ResetSoft;

architecture behavioral of ResetSoft is
	
	type stage_t is (S0,S1,S2); --,SS);
	signal stage : stage_t := S0;

	signal Done_reg : std_logic := '0';
	signal TxRx_Go_reg : std_logic := '0';
	signal TxRx_Rd_reg : std_logic := '0';
	signal TxRx_A_reg : std_logic_vector (7 downto 0) := (others => '0');
	signal TxRx_D_reg : std_logic_vector (7 downto 0) := (others => '0');
	--signal Ser_Go_reg : std_logic := '0';
	--signal Ser_D_reg : std_logic_vector (7 downto 0) := (others => '0');
	--signal Debug_reg : std_logic := '0';
begin
	DAC_Rst <= Go and not Done_reg;

	RAM_EN <= '0';
	RAM_ADDR_tri <= (others => 'Z');
	RAM_WE_tri <= (others => 'Z');
	RAM_DI_tri <= (others => 'Z');

	TxRx_Go <= TxRx_Go_reg;
        TxRx_A_tri <= TxRx_A_reg when (TxRx_Go_reg = '1') else (others => 'Z');
        TxRx_D_tri <= TxRx_D_reg when (TxRx_Go_reg = '1') else (others => 'Z');
        TxRx_Rd_tri <= TxRx_Rd_reg when (TxRx_Go_reg = '1') else 'Z';

	DiscardPacket : process (Clk)
		variable op_complete_var : std_logic;
	begin
		if rising_edge(Clk) then
			stage <= stage;
			Done_reg <= '0';
			-- disable the MuxIntel when not in use
	   	   	TxRx_Go_reg <= '0';
	   	   	TxRx_Rd_reg <= '0';
	   	   	TxRx_A_reg <= (others => '0');
	   	   	TxRx_D_reg <= (others => '0');
			-- disable the serial port when not in use
			--Ser_Go_reg <= '0';
			--Ser_D_reg <= (others => '0');
			--Debug_reg <= '0';

			op_complete_var := TxRx_Go_reg and TxRx_Done;

			case stage is
			    when S0 =>
				if (Go = '1') then
					stage <= S1;
				end if;
			    when S1 =>
				TxRx_A_reg <= X"11";
				TxRx_D_reg <= "00000010";  -- discard received packet
				TxRx_Rd_reg <= '0';
				TxRx_Go_reg <= not TxRx_Done;
				if (op_complete_var = '1') then
					stage <= S2;
				end if;
			--    when SS =>
			--	Ser_D_reg <= X"6D";
			--	Ser_Go_reg <= not Ser_Done;
			--	op_complete_var := Ser_Go_reg and Ser_Done;
			--	if (op_complete_var = '1') then
			--		stage <= S3;
			--	end if;
			    when S2 =>
				if (Go = '1') then
					Done_reg <= '1';
				else
					stage <= S0;
				end if;
			end case;

		else
			stage <= stage;
			Done_reg <= Done_reg;
			TxRx_A_reg <= TxRx_A_reg;
			TxRx_D_reg <= TxRx_D_reg;
			TxRx_Rd_reg <= TxRx_Rd_reg;
			TxRx_Go_reg <= TxRx_Go_reg;
			--Ser_D_reg <= Ser_D_reg;
			--Ser_Go_reg <= Ser_Go_reg;
			--Debug_reg <= Debug_reg;
		end if;
	end process;

	--Ser_Go <= Ser_Go_reg;
  	--Ser_D_tri <= Ser_D_reg when (Ser_Go_reg = '1') else (others => 'Z');
	--Debug <= Debug_reg;

	Done <= Done_reg;

end behavioral;