Release 14.6 Map P.68d (nt64) Xilinx Mapping Report File for Design 'FPGA_main' Design Information ------------------ Command Line : map -intstyle ise -p xc3s50a-vq100-4 -cm area -detail -ir off -pr off -c 100 -o FPGA_main_map.ncd FPGA_main.ngd FPGA_main.pcf Target Device : xc3s50a Target Package : vq100 Target Speed : -4 Mapper Version : spartan3a -- $Revision: 1.55 $ Mapped Date : Mon Jan 20 11:40:31 2014 Design Summary -------------- Number of errors: 0 Number of warnings: 1 Logic Utilization: Number of Slice Flip Flops: 630 out of 1,408 44% Number of 4 input LUTs: 1,146 out of 1,408 81% Logic Distribution: Number of occupied Slices: 702 out of 704 99% Number of Slices containing only related logic: 702 out of 702 100% Number of Slices containing unrelated logic: 0 out of 702 0% *See NOTES below for an explanation of the effects of unrelated logic. Total Number of 4 input LUTs: 1,195 out of 1,408 84% Number used as logic: 1,146 Number used as a route-thru: 49 The Slice Logic Distribution report is not meaningful if the design is over-mapped for a non-slice resource or if Placement fails. Number of bonded IOBs: 37 out of 68 54% Number of BUFGMUXs: 2 out of 24 8% Number of DCMs: 1 out of 2 50% Number of STARTUPs: 1 out of 1 100% Number of STARTUP_SPARTAN3As: 1 out of 1 100% Number of RAMB16BWEs: 1 out of 3 33% Number of STARTUP_SPARTAN3Es: 1 out of 1 100% Average Fanout of Non-Clock Nets: 3.57 Peak Memory Usage: 294 MB Total REAL time to MAP completion: 2 secs Total CPU time to MAP completion: 2 secs NOTES: Related logic is defined as being logic that shares connectivity - e.g. two LUTs are "related" if they share common inputs. When assembling slices, Map gives priority to combine logic that is related. Doing so results in the best timing performance. Unrelated logic shares no connectivity. Map will only begin packing unrelated logic into a slice once 99% of the slices are occupied through related logic packing. Note that once logic distribution reaches the 99% level through related logic packing, this does not mean the device is completely utilized. Unrelated logic packing will then begin, continuing until all usable LUTs and FFs are occupied. Depending on your timing budget, increased levels of unrelated logic packing may adversely affect the overall timing performance of your design. Table of Contents ----------------- Section 1 - Errors Section 2 - Warnings Section 3 - Informational Section 4 - Removed Logic Summary Section 5 - Removed Logic Section 6 - IOB Properties Section 7 - RPMs Section 8 - Guide Report Section 9 - Area Group and Partition Summary Section 10 - Timing Report Section 11 - Configuration String Information Section 12 - Control Set Information Section 13 - Utilization by Hierarchy Section 1 - Errors ------------------ Section 2 - Warnings -------------------- WARNING:LIT:175 - Clock buffer is designated to drive clock loads. BUFGMUX symbol "physical_group_SPI_SCLK_OBUF/BUFG_inst_2" (output signal=SPI_SCLK_OBUF) has a mix of clock and non-clock loads. Some of the non-clock loads are (maximum of 5 listed): Pin CE of Querier_inst/GetTempVal_inst/counter_4b_0 Pin CE of Querier_inst/GetTempVal_inst/counter_4b_1 Pin CE of Querier_inst/GetTempVal_inst/counter_4b_2 Pin CE of Querier_inst/GetTempVal_inst/counter_4b_3 Pin CE of Querier_inst/GetTempVal_inst/Done_reg Section 3 - Informational ------------------------- INFO:LIT:243 - Logical network STARTUP_SPARTAN3A_inst/GSR_INT has no load. INFO:LIT:243 - Logical network STARTUP_SPARTAN3A_inst/GTS_INT has no load. INFO:MapLib:562 - No environment variables are currently set. INFO:LIT:244 - All of the single ended outputs in this design are using slew rate limited output drivers. The delay on speed critical single ended outputs can be dramatically reduced by designating them as fast outputs. Section 4 - Removed Logic Summary --------------------------------- 2 block(s) optimized away 87 Block(s) redundant Section 5 - Removed Logic ------------------------- Optimized Block(s): TYPE BLOCK GND XST_GND VCC XST_VCC Redundant Block(s): TYPE BLOCK LOCALBUF Transmitter_inst/WriteSpacket_inst/buffer_addr_and00001/LUT2_D_BUF LOCALBUF TxRx_A_tri<0>LogicTrst31/LUT3_D_BUF LOCALBUF Transceiver_inst/AD_reg_mux0001<1>253/LUT4_L_BUF LOCALBUF Receiver_inst/PktType_reg_mux0001<0>11/LUT3_D_BUF LOCALBUF Receiver_inst/PktType_reg_mux0001<2>1/LUT4_D_BUF LOCALBUF DAC_writer_inst/Mrom_DAC_Code_reg_rom0000_SW0/LUT2_L_BUF LOCALBUF DAC_writer_inst/Mrom_DAC_margin_vec_rom000110_SW0/LUT2_L_BUF LOCALBUF DAC_writer_inst/DAC_Code_reg_mux0003<7>5/LUT3_L_BUF LOCALBUF DAC_writer_inst/DAC_Code_reg_mux0003<3>5/LUT3_L_BUF LOCALBUF DAC_writer_inst/Mrom_DAC_margin_vec_rom00011_SW0/LUT2_L_BUF LOCALBUF Receiver_inst/match_bits_0_mux00012117/LUT4_L_BUF LOCALBUF Transceiver_inst/AD_reg_mux0001<4>28/LUT4_L_BUF LOCALBUF Transceiver_inst/AD_reg_mux0001<1>28/LUT4_L_BUF LOCALBUF Transceiver_inst/AD_reg_mux0001<0>28/LUT4_L_BUF LOCALBUF Receiver_inst/match_bits_6_mux000137_SW0/LUT4_L_BUF LOCALBUF Receiver_inst/match_bits_4_mux000136_SW0/LUT4_L_BUF LOCALBUF Receiver_inst/match_bits_2_mux000136_SW0/LUT4_L_BUF LOCALBUF Receiver_inst/match_bits_1_mux000136_SW0/LUT4_L_BUF LOCALBUF Receiver_inst/match_bits_0_mux000131_SW0/LUT4_L_BUF LOCALBUF Transceiver_inst/AD_reg_mux0001<5>49/LUT4_D_BUF LOCALBUF DAC_writer_inst/DAC_Code_reg_mux0003<0>2_SW1/LUT2_L_BUF LOCALBUF DAC_writer_inst/DAC_Code_reg_mux0003<11>11_SW0/LUT2_L_BUF LOCALBUF DAC_writer_inst/DAC_Code_reg_mux0003<11>11_SW1/LUT2_L_BUF LOCALBUF DAC_writer_inst/DAC_Code_reg_mux0003<11>11_SW2/LUT2_L_BUF LOCALBUF DAC_writer_inst/DAC_Code_reg_mux0003<11>11_SW3/LUT2_L_BUF LOCALBUF DAC_writer_inst/DAC_Code_reg_mux0003<11>11_SW4/LUT2_L_BUF LOCALBUF DAC_writer_inst/DAC_Code_reg_mux0003<11>11_SW5/LUT3_L_BUF LOCALBUF DAC_writer_inst/DAC_Code_reg_mux0003<11>11_SW6/LUT3_L_BUF LOCALBUF DAC_writer_inst/DAC_Code_reg_mux0003<11>11_SW7/LUT3_L_BUF LOCALBUF DAC_writer_inst/DAC_Code_reg_mux0003<11>11_SW8/LUT3_L_BUF LOCALBUF DAC_writer_inst/DAC_Code_reg_mux0003<11>11_SW9/LUT3_L_BUF LOCALBUF DAC_writer_inst/DAC_Code_reg_mux0003<11>11_SW10/LUT3_L_BUF LOCALBUF DAC_writer_inst/DAC_Code_reg_mux0003<11>11_SW11/LUT3_L_BUF LOCALBUF INTCatcher_inst/Maddsub_Pending_rec_share0000_cy<1>1/LUT3_D_BUF LOCALBUF INTCatcher_inst/Maddsub_Pending_rec_share0000_xor<7>11/LUT4_L_BUF LOCALBUF INTCatcher_inst/Maddsub_Pending_rec_share0000_cy<5>1/LUT4_D_BUF LOCALBUF Receiver_inst/stage_FSM_FFd3-In1114_SW0/LUT3_L_BUF LUT1 ResetHard_inst/Madd_counter_32b_addsub0000_cy<25>_rt LUT1 ResetHard_inst/Madd_counter_32b_addsub0000_cy<24>_rt LUT1 ResetHard_inst/Madd_counter_32b_addsub0000_cy<23>_rt LUT1 ResetHard_inst/Madd_counter_32b_addsub0000_cy<22>_rt LUT1 ResetHard_inst/Madd_counter_32b_addsub0000_cy<21>_rt LUT1 ResetHard_inst/Madd_counter_32b_addsub0000_cy<20>_rt LUT1 ResetHard_inst/Madd_counter_32b_addsub0000_cy<19>_rt LUT1 ResetHard_inst/Madd_counter_32b_addsub0000_cy<18>_rt LUT1 ResetHard_inst/Madd_counter_32b_addsub0000_cy<17>_rt LUT1 ResetHard_inst/Madd_counter_32b_addsub0000_cy<16>_rt LUT1 ResetHard_inst/Madd_counter_32b_addsub0000_cy<15>_rt LUT1 ResetHard_inst/Madd_counter_32b_addsub0000_cy<14>_rt LUT1 ResetHard_inst/Madd_counter_32b_addsub0000_cy<13>_rt LUT1 ResetHard_inst/Madd_counter_32b_addsub0000_cy<12>_rt LUT1 ResetHard_inst/Madd_counter_32b_addsub0000_cy<11>_rt LUT1 ResetHard_inst/Madd_counter_32b_addsub0000_cy<10>_rt LUT1 ResetHard_inst/Madd_counter_32b_addsub0000_cy<9>_rt LUT1 ResetHard_inst/Madd_counter_32b_addsub0000_cy<8>_rt LUT1 ResetHard_inst/Madd_counter_32b_addsub0000_cy<7>_rt LUT1 ResetHard_inst/Madd_counter_32b_addsub0000_cy<6>_rt LUT1 ResetHard_inst/Madd_counter_32b_addsub0000_cy<5>_rt LUT1 ResetHard_inst/Madd_counter_32b_addsub0000_cy<4>_rt LUT1 ResetHard_inst/Madd_counter_32b_addsub0000_cy<3>_rt LUT1 ResetHard_inst/Madd_counter_32b_addsub0000_cy<2>_rt LUT1 ResetHard_inst/Madd_counter_32b_addsub0000_cy<1>_rt LUT1 DAC_writer_inst/Msub_DAC_margin_vec_sub0000_cy<10>_rt LUT1 DAC_writer_inst/Msub_DAC_margin_vec_sub0000_cy<6>_rt LUT1 DAC_writer_inst/Madd_RAM_ADDR_reg_addsub0000_cy<8>_rt LUT1 DAC_writer_inst/Madd_RAM_ADDR_reg_addsub0000_cy<7>_rt LUT1 DAC_writer_inst/Madd_RAM_ADDR_reg_addsub0000_cy<6>_rt LUT1 DAC_writer_inst/Madd_RAM_ADDR_reg_addsub0000_cy<5>_rt LUT1 DAC_writer_inst/Madd_RAM_ADDR_reg_addsub0000_cy<4>_rt LUT1 DAC_writer_inst/Madd_RAM_ADDR_reg_addsub0000_cy<3>_rt LUT1 DAC_writer_inst/Madd_RAM_ADDR_reg_addsub0000_cy<2>_rt LUT1 DAC_writer_inst/Madd_RAM_ADDR_reg_addsub0000_cy<1>_rt LUT1 ResetHard_inst/Madd_counter_32b_addsub0000_xor<26>_rt LUT1 DAC_writer_inst/Madd_RAM_ADDR_reg_addsub0000_xor<9>_rt INV Querier_inst/GetTempVal_inst/SCLK_inv1_INV_0 INV Rst1_INV_0 INV Transceiver_inst/WR_low1_INV_0 INV Transceiver_inst/RD_low1_INV_0 INV Querier_inst/GetADCval_inst/A_CS_low1_INV_0 INV DAC_controller_inst/SYNC_low1_INV_0 INV Transmitter_inst/Go_WPS_reg_not00031_INV_0 INV Transmitter_inst/Go_WPD_reg_not00031_INV_0 INV Transceiver_inst/driving_AD_inv1_INV_0 INV ResetHard_inst/Go_MAC_not00011_INV_0 INV ResetHard_inst/DAC_Rst_reg_inv1_INV_0 INV DAC_controller_inst/stage_FSM_Out2211_INV_0 INV INTCatcher_inst/stage_FSM_Out911_INV_0 Section 6 - IOB Properties -------------------------- +-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ | IOB Name | Type | Direction | IO Standard | Diff | Drive | Slew | Reg (s) | Resistor | IBUF/IFD | SUSPEND | | | | | | Term | Strength | Rate | | | Delay | | +-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ | DAC_DIN | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | 0 / 0 | 3STATE | | DAC_RESET_low | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | 0 / 0 | 3STATE | | DAC_SCLK | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | 0 / 0 | 3STATE | | DAC_SYNC_low | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | 0 / 0 | 3STATE | | DCM_stable | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | 0 / 0 | 3STATE | | Debug_port | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | 0 / 0 | 3STATE | | Eth_AD<0> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | | | 0 / 0 | 3STATE | | Eth_AD<1> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | | | 0 / 0 | 3STATE | | Eth_AD<2> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | | | 0 / 0 | 3STATE | | Eth_AD<3> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | | | 0 / 0 | 3STATE | | Eth_AD<4> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | | | 0 / 0 | 3STATE | | Eth_AD<5> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | | | 0 / 0 | 3STATE | | Eth_AD<6> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | | | 0 / 0 | 3STATE | | Eth_AD<7> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | | | 0 / 0 | 3STATE | | Eth_ALE | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | 0 / 0 | 3STATE | | Eth_CLK | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | 0 / 0 | 3STATE | | Eth_CS_low | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | 0 / 0 | 3STATE | | Eth_INT_low | IBUF | INPUT | LVCMOS33 | | | | | | 0 / 0 | | | Eth_RD_low | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | 0 / 0 | 3STATE | | Eth_RST_low | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | | | 0 / 0 | 3STATE | | Eth_WR_low | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | 0 / 0 | 3STATE | | ExtClk | IBUF | INPUT | LVCMOS33 | | | | | | 0 / 0 | | | ExtRst_low | IBUF | INPUT | LVCMOS33 | | | | | PULLUP | 0 / 0 | | | LocStamp<0> | IBUF | INPUT | LVCMOS33 | | | | | PULLUP | 0 / 0 | | | LocStamp<1> | IBUF | INPUT | LVCMOS33 | | | | | PULLUP | 0 / 0 | | | LocStamp<2> | IBUF | INPUT | LVCMOS33 | | | | | PULLUP | 0 / 0 | | | LocStamp<3> | IBUF | INPUT | LVCMOS33 | | | | | PULLUP | 0 / 0 | | | LocStamp<4> | IBUF | INPUT | LVCMOS33 | | | | | PULLUP | 0 / 0 | | | SPI_A_CS_low | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | 0 / 0 | 3STATE | | SPI_SCLK | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | 0 / 0 | 3STATE | | SPI_SDI_tri | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | 0 / 0 | 3STATE | | SPI_SDO | IBUF | INPUT | LVCMOS33 | | | | | | 0 / 0 | | | SPI_T_CE | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | 0 / 0 | 3STATE | | Serial_port | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | 0 / 0 | 3STATE | | StateCode<0> | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | 0 / 0 | 3STATE | | StateCode<1> | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | 0 / 0 | 3STATE | | StateCode<2> | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | 0 / 0 | 3STATE | +-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ Section 7 - RPMs ---------------- Section 8 - Guide Report ------------------------ Guide not run on this design. Section 9 - Area Group and Partition Summary -------------------------------------------- Partition Implementation Status ------------------------------- No Partitions were found in this design. ------------------------------- Area Group Information ---------------------- No area groups were found in this design. ---------------------- Section 10 - Timing Report -------------------------- This design was not run using timing mode. Section 11 - Configuration String Details ----------------------------------------- BUFGMUX "BUFG_inst_1": DISABLE_ATTR:LOW BUFGMUX "BUFG_inst_2": DISABLE_ATTR:LOW DCM "DCM_SP_inst": CLKDV_DIVIDE:2 CLKOUT_PHASE_SHIFT:NONE CLK_FEEDBACK:1X DESKEW_ADJUST:9 DFS_FREQUENCY_MODE:LOW DLL_FREQUENCY_MODE:LOW DUTY_CYCLE_CORRECTION:TRUE FACTORY_JF1:0XC0 FACTORY_JF2:0X80 CLKFX_DIVIDE = 8 CLKFX_MULTIPLY = 2 PHASE_SHIFT = 0 X_CLKIN_PERIOD = 50.0000000000000000 RAMB16BWE "RAMB16BWE_S18_S18_inst": DATA_WIDTH_A:18 DATA_WIDTH_B:18 WRITE_MODE_A:WRITE_FIRST WRITE_MODE_B:WRITE_FIRST INITP_00 = 0000000000000000000000000000000000000000000000000000000000000000 INITP_01 = 0000000000000000000000000000000000000000000000000000000000000000 INITP_02 = 0000000000000000000000000000000000000000000000000000000000000000 INITP_03 = 0000000000000000000000000000000000000000000000000000000000000000 INITP_04 = 0000000000000000000000000000000000000000000000000000000000000000 INITP_05 = 0000000000000000000000000000000000000000000000000000000000000000 INITP_06 = 0000000000000000000000000000000000000000000000000000000000000000 INITP_07 = 0000000000000000000000000000000000000000000000000000000000000000 INIT_00 = 0000000000000000000000000000000000000000000000000000000000000000 INIT_01 = 0000000000000000000000000000000000000000000000000000000000000000 INIT_02 = 0000000000000000000000000000000000000000000000000000000000000000 INIT_03 = 0000000000000000000000000000000000000000000000000000000000000000 INIT_04 = 0000000000000000000000000000000000000000000000000000000000000000 INIT_05 = 0000000000000000000000000000000000000000000000000000000000000000 INIT_06 = 0000000000000000000000000000000000000000000000000000000000000000 INIT_07 = 0000000000000000000000000000000000000000000000000000000000000000 INIT_08 = 0000000000000000000000000000000000000000000000000000000000000000 INIT_09 = 0000000000000000000000000000000000000000000000000000000000000000 INIT_0A = 0000000000000000000000000000000000000000000000000000000000000000 INIT_0B = 0000000000000000000000000000000000000000000000000000000000000000 INIT_0C = 0000000000000000000000000000000000000000000000000000000000000000 INIT_0D = 0000000000000000000000000000000000000000000000000000000000000000 INIT_0E = 0000000000000000000000000000000000000000000000000000000000000000 INIT_0F = 0000000000000000000000000000000000000000000000000000000000000000 INIT_10 = 0000000000000000000000000000000000000000000000000000000000000000 INIT_11 = 0000000000000000000000000000000000000000000000000000000000000000 INIT_12 = 0000000000000000000000000000000000000000000000000000000000000000 INIT_13 = 0000000000000000000000000000000000000000000000000000000000000000 INIT_14 = 0000000000000000000000000000000000000000000000000000000000000000 INIT_15 = 0000000000000000000000000000000000000000000000000000000000000000 INIT_16 = 0000000000000000000000000000000000000000000000000000000000000000 INIT_17 = 0000000000000000000000000000000000000000000000000000000000000000 INIT_18 = 0000000000000000000000000000000000000000000000000000000000000000 INIT_19 = 0000000000000000000000000000000000000000000000000000000000000000 INIT_1A = 0000000000000000000000000000000000000000000000000000000000000000 INIT_1B = 0000000000000000000000000000000000000000000000000000000000000000 INIT_1C = 0000000000000000000000000000000000000000000000000000000000000000 INIT_1D = 0000000000000000000000000000000000000000000000000000000000000000 INIT_1E = 0000000000000000000000000000000000000000000000000000000000000000 INIT_1F = 0000000000000000000000000000000000000000000000000000000000000000 INIT_20 = 0000000000000000000000000000000000000000000000000000000000000000 INIT_21 = 0000000000000000000000000000000000000000000000000000000000000000 INIT_22 = 0000000000000000000000000000000000000000000000000000000000000000 INIT_23 = 0000000000000000000000000000000000000000000000000000000000000000 INIT_24 = 0000000000000000000000000000000000000000000000000000000000000000 INIT_25 = 0000000000000000000000000000000000000000000000000000000000000000 INIT_26 = 0000000000000000000000000000000000000000000000000000000000000000 INIT_27 = 0000000000000000000000000000000000000000000000000000000000000000 INIT_28 = 0000000000000000000000000000000000000000000000000000000000000000 INIT_29 = 0000000000000000000000000000000000000000000000000000000000000000 INIT_2A = 0000000000000000000000000000000000000000000000000000000000000000 INIT_2B = 0000000000000000000000000000000000000000000000000000000000000000 INIT_2C = 0000000000000000000000000000000000000000000000000000000000000000 INIT_2D = 0000000000000000000000000000000000000000000000000000000000000000 INIT_2E = 0000000000000000000000000000000000000000000000000000000000000000 INIT_2F = 0000000000000000000000000000000000000000000000000000000000000000 INIT_30 = 0000000000000000000000000000000000000000000000000000000000000000 INIT_31 = 0000000000000000000000000000000000000000000000000000000000000000 INIT_32 = 0000000000000000000000000000000000000000000000000000000000000000 INIT_33 = 0000000000000000000000000000000000000000000000000000000000000000 INIT_34 = 0000000000000000000000000000000000000000000000000000000000000000 INIT_35 = 0000000000000000000000000000000000000000000000000000000000000000 INIT_36 = 0000000000000000000000000000000000000000000000000000000000000000 INIT_37 = 0000000000000000000000000000000000000000000000000000000000000000 INIT_38 = 0000000000000000000000000000000000000000000000000000000000000000 INIT_39 = 0000000000000000000000000000000000000000000000000000000000000000 INIT_3A = 0000000000000000000000000000000000000000000000000000000000000000 INIT_3B = 0000000000000000000000000000000000000000000000000000000000000000 INIT_3C = 0000000000000000000000000000000000000000000000000000000000000000 INIT_3D = 0000000000000000000000000000000000000000000000000000000000000000 INIT_3E = 0000000000000000000000000000000000000000000000000000000000000000 INIT_3F = 0000000000000000000000000000000000000000000000000000000000000000 INIT_A = 000000000 INIT_B = 000000000 SRVAL_A = 000000000 SRVAL_B = 000000000 Section 12 - Control Set Information ------------------------------------ No control set information for this architecture. Section 13 - Utilization by Hierarchy ------------------------------------- +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ | Module | Partition | Slices | Slice Reg | LUTs | LUTRAM | BRAM | MULT18X18 | BUFG | DCM | Full Hierarchical Name | +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ | FPGA_main/ | | 82/764 | 15/630 | 142/1176 | 0/0 | 1/1 | 0/0 | 2/2 | 1/1 | FPGA_main | | +DAC_controller_inst | | 17/17 | 25/25 | 12/12 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | FPGA_main/DAC_controller_inst | | +DAC_writer_inst | | 84/84 | 39/39 | 159/159 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | FPGA_main/DAC_writer_inst | | +INTCatcher_inst | | 38/38 | 34/34 | 59/59 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | FPGA_main/INTCatcher_inst | | +Querier_inst | | 27/87 | 31/75 | 44/112 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | FPGA_main/Querier_inst | | ++GetADCval_inst | | 38/38 | 26/26 | 47/47 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | FPGA_main/Querier_inst/GetADCval_inst | | ++GetTempVal_inst | | 22/22 | 18/18 | 21/21 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | FPGA_main/Querier_inst/GetTempVal_inst | | +Receiver_inst | | 80/135 | 71/141 | 125/185 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | FPGA_main/Receiver_inst | | ++PpacketReader | | 55/55 | 70/70 | 60/60 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | FPGA_main/Receiver_inst/PpacketReader | | +ResetHard_inst | | 63/103 | 79/128 | 104/165 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | FPGA_main/ResetHard_inst | | ++MACaddrLoad_inst | | 40/40 | 49/49 | 61/61 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | FPGA_main/ResetHard_inst/MACaddrLoad_inst | | +ResetSoft_inst | | 5/5 | 5/5 | 3/3 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | FPGA_main/ResetSoft_inst | | +Transceiver_inst | | 62/62 | 29/29 | 94/94 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | FPGA_main/Transceiver_inst | | +Transmitter_inst | | 38/151 | 40/139 | 54/245 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | FPGA_main/Transmitter_inst | | ++WriteDpacket_inst | | 53/53 | 48/48 | 90/90 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | FPGA_main/Transmitter_inst/WriteDpacket_inst | | ++WriteSpacket_inst | | 60/60 | 51/51 | 101/101 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | FPGA_main/Transmitter_inst/WriteSpacket_inst | +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ * Slices can be packed with basic elements from multiple hierarchies. Therefore, a slice will be counted in every hierarchical module that each of its packed basic elements belong to. ** For each column, there are two numbers reported /. is the number of elements that belong to that specific hierarchical module. is the total number of elements from that hierarchical module and any lower level hierarchical modules below. *** The LUTRAM column counts all LUTs used as memory including RAM, ROM, and shift registers.