Release 14.6 Map P.68d (nt64)
Xilinx Map Application Log File for Design 'FPGA_main'

Design Information
------------------
Command Line   : map -intstyle ise -p xc3s50a-vq100-4 -cm area -detail -ir off
-pr off -c 100 -o FPGA_main_map.ncd FPGA_main.ngd FPGA_main.pcf 
Target Device  : xc3s50a
Target Package : vq100
Target Speed   : -4
Mapper Version : spartan3a -- $Revision: 1.55 $
Mapped Date    : Mon Jan 20 11:40:31 2014

Mapping design into LUTs...
WARNING:LIT:175 - Clock buffer is designated to drive clock loads. BUFGMUX
   symbol "physical_group_SPI_SCLK_OBUF/BUFG_inst_2" (output
   signal=SPI_SCLK_OBUF) has a mix of clock and non-clock loads. Some of the
   non-clock loads are (maximum of 5 listed):
   Pin CE of Querier_inst/GetTempVal_inst/counter_4b_0
   Pin CE of Querier_inst/GetTempVal_inst/counter_4b_1
   Pin CE of Querier_inst/GetTempVal_inst/counter_4b_2
   Pin CE of Querier_inst/GetTempVal_inst/counter_4b_3
   Pin CE of Querier_inst/GetTempVal_inst/Done_reg
Running directed packing...
Running delay-based LUT packing...
Running related packing...
Running unrelated packing...
Updating timing models...

Design Summary
--------------

Design Summary:
Number of errors:      0
Number of warnings:    1
Logic Utilization:
  Number of Slice Flip Flops:           630 out of   1,408   44%
  Number of 4 input LUTs:             1,146 out of   1,408   81%
Logic Distribution:
  Number of occupied Slices:            702 out of     704   99%
    Number of Slices containing only related logic:     702 out of     702 100%
    Number of Slices containing unrelated logic:          0 out of     702   0%
      *See NOTES below for an explanation of the effects of unrelated logic.
  Total Number of 4 input LUTs:       1,195 out of   1,408   84%
    Number used as logic:             1,146
    Number used as a route-thru:         49

  The Slice Logic Distribution report is not meaningful if the design is
  over-mapped for a non-slice resource or if Placement fails.

  Number of bonded IOBs:                 37 out of      68   54%
  Number of BUFGMUXs:                     2 out of      24    8%
  Number of DCMs:                         1 out of       2   50%
  Number of STARTUPs:                     1 out of       1  100%
  Number of STARTUP_SPARTAN3As:           1 out of       1  100%
  Number of RAMB16BWEs:                   1 out of       3   33%
  Number of STARTUP_SPARTAN3Es:           1 out of       1  100%

Average Fanout of Non-Clock Nets:                3.57

Peak Memory Usage:  294 MB
Total REAL time to MAP completion:  2 secs 
Total CPU time to MAP completion:   2 secs 

NOTES:

   Related logic is defined as being logic that shares connectivity - e.g. two
   LUTs are "related" if they share common inputs.  When assembling slices,
   Map gives priority to combine logic that is related.  Doing so results in
   the best timing performance.

   Unrelated logic shares no connectivity.  Map will only begin packing
   unrelated logic into a slice once 99% of the slices are occupied through
   related logic packing.

   Note that once logic distribution reaches the 99% level through related
   logic packing, this does not mean the device is completely utilized.
   Unrelated logic packing will then begin, continuing until all usable LUTs
   and FFs are occupied.  Depending on your timing budget, increased levels of
   unrelated logic packing may adversely affect the overall timing performance
   of your design.

Mapping completed.
See MAP report file "FPGA_main_map.mrp" for details.