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Release 14.6 Trace  (nt64)
Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved.

C:\Xilinx\14.6\ISE_DS\ISE\bin\nt64\unwrapped\trce.exe -intstyle ise -v 3 -s 4
-n 3 -fastpaths -xml FPGA_main.twx FPGA_main.ncd -o FPGA_main.twr FPGA_main.pcf

Design file:              FPGA_main.ncd
Physical constraint file: FPGA_main.pcf
Device,package,speed:     xc3s50a,vq100,-4 (PRODUCTION 1.42 2013-06-08)
Report level:             verbose report

Environment Variable      Effect 
--------------------      ------ 
NONE                      No environment variables were set
--------------------------------------------------------------------------------

INFO:Timing:2698 - No timing constraints found, doing default enumeration.
INFO:Timing:3412 - To improve timing, see the Timing Closure User Guide (UG612).
INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths 
   option. All paths that are not constrained will be reported in the 
   unconstrained paths section(s) of the report.
INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on 
   a 50 Ohm transmission line loading model.  For the details of this model, 
   and for more information on accounting for different loading conditions, 
   please see the device datasheet.
INFO:Timing:3390 - This architecture does not support a default System Jitter 
   value, please add SYSTEM_JITTER constraint to the UCF to modify the Clock 
   Uncertainty calculation.
INFO:Timing:3389 - This architecture does not support 'Discrete Jitter' and 
   'Phase Error' calculations, these terms will be zero in the Clock 
   Uncertainty calculation.  Please make appropriate modification to 
   SYSTEM_JITTER to account for the unsupported Discrete Jitter and Phase 
   Error.



Data Sheet report:
-----------------
All values displayed in nanoseconds (ns)

Setup/Hold to clock ExtClk
------------+------------+------------+------------------+--------+
            |Max Setup to|Max Hold to |                  | Clock  |
Source      | clk (edge) | clk (edge) |Internal Clock(s) | Phase  |
------------+------------+------------+------------------+--------+
Eth_AD<0>   |    2.063(R)|    0.057(R)|Eth_CLK_OBUF      |   0.000|
Eth_AD<1>   |    1.999(R)|    0.109(R)|Eth_CLK_OBUF      |   0.000|
Eth_AD<2>   |    2.304(R)|   -0.087(R)|Eth_CLK_OBUF      |   0.000|
Eth_AD<3>   |    2.004(R)|    0.154(R)|Eth_CLK_OBUF      |   0.000|
Eth_AD<4>   |    2.144(R)|    0.043(R)|Eth_CLK_OBUF      |   0.000|
Eth_AD<5>   |    2.279(R)|   -0.064(R)|Eth_CLK_OBUF      |   0.000|
Eth_AD<6>   |    2.232(R)|   -0.060(R)|Eth_CLK_OBUF      |   0.000|
Eth_AD<7>   |    2.209(R)|   -0.042(R)|Eth_CLK_OBUF      |   0.000|
Eth_INT_low |    3.381(R)|   -0.460(R)|Eth_CLK_OBUF      |   0.000|
Eth_RST_low |    3.543(R)|   -0.738(R)|Eth_CLK_OBUF      |   0.000|
LocStamp<0> |    6.080(R)|   -1.335(R)|Eth_CLK_OBUF      |   0.000|
LocStamp<1> |    8.385(R)|   -1.838(R)|Eth_CLK_OBUF      |   0.000|
LocStamp<2> |    7.870(R)|   -1.445(R)|Eth_CLK_OBUF      |   0.000|
LocStamp<3> |    8.455(R)|   -1.679(R)|Eth_CLK_OBUF      |   0.000|
LocStamp<4> |    6.543(R)|   -1.706(R)|Eth_CLK_OBUF      |   0.000|
SPI_SDO     |    5.188(R)|    0.274(R)|SPI_SCLK_OBUF     |   0.000|
            |    5.562(F)|   -0.486(F)|Eth_CLK_OBUF      |   0.000|
------------+------------+------------+------------------+--------+

Clock ExtClk to Pad
-------------+------------+------------------+--------+
             | clk (edge) |                  | Clock  |
Destination  |   to PAD   |Internal Clock(s) | Phase  |
-------------+------------+------------------+--------+
DAC_DIN      |    8.328(R)|Eth_CLK_OBUF      |   0.000|
DAC_RESET_low|   10.073(R)|Eth_CLK_OBUF      |   0.000|
DAC_SYNC_low |    8.537(R)|Eth_CLK_OBUF      |   0.000|
Eth_AD<0>    |    8.485(R)|Eth_CLK_OBUF      |   0.000|
Eth_AD<1>    |    8.467(R)|Eth_CLK_OBUF      |   0.000|
Eth_AD<2>    |    8.484(R)|Eth_CLK_OBUF      |   0.000|
Eth_AD<3>    |    8.869(R)|Eth_CLK_OBUF      |   0.000|
Eth_AD<4>    |    8.598(R)|Eth_CLK_OBUF      |   0.000|
Eth_AD<5>    |    8.274(R)|Eth_CLK_OBUF      |   0.000|
Eth_AD<6>    |    8.793(R)|Eth_CLK_OBUF      |   0.000|
Eth_AD<7>    |    7.903(R)|Eth_CLK_OBUF      |   0.000|
Eth_ALE      |    8.064(R)|Eth_CLK_OBUF      |   0.000|
Eth_RD_low   |    7.445(R)|Eth_CLK_OBUF      |   0.000|
Eth_RST_low  |    9.035(R)|Eth_CLK_OBUF      |   0.000|
Eth_WR_low   |    8.037(R)|Eth_CLK_OBUF      |   0.000|
SPI_A_CS_low |    8.144(R)|SPI_SCLK_OBUF     |   0.000|
SPI_SDI_tri  |    9.619(R)|Eth_CLK_OBUF      |   0.000|
             |    9.152(R)|SPI_SCLK_OBUF     |   0.000|
SPI_T_CE     |    7.927(F)|Eth_CLK_OBUF      |   0.000|
StateCode<0> |   10.261(R)|Eth_CLK_OBUF      |   0.000|
StateCode<1> |   10.757(R)|Eth_CLK_OBUF      |   0.000|
StateCode<2> |    9.297(R)|Eth_CLK_OBUF      |   0.000|
-------------+------------+------------------+--------+

Clock to Setup on destination clock ExtClk
---------------+---------+---------+---------+---------+
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
ExtClk         |   12.017|    2.996|    7.270|    7.270|
---------------+---------+---------+---------+---------+

Pad to Pad
---------------+---------------+---------+
Source Pad     |Destination Pad|  Delay  |
---------------+---------------+---------+
ExtClk         |DAC_SCLK       |    7.378|
ExtClk         |Eth_CLK        |    7.834|
ExtClk         |SPI_SCLK       |    7.658|
---------------+---------------+---------+


Analysis completed Mon Jan 20 11:40:49 2014 
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Trace Settings:
-------------------------
Trace Settings 

Peak Memory Usage: 185 MB