Release 14.6 par P.68d (nt64) Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. HERMES:: Mon Jan 20 11:40:35 2014 par -w -intstyle ise -ol high -t 1 FPGA_main_map.ncd FPGA_main.ncd FPGA_main.pcf Constraints file: FPGA_main.pcf. Loading device for application Rf_Device from file '3s50a.nph' in environment C:\Xilinx\14.6\ISE_DS\ISE\. "FPGA_main" is an NCD, version 3.2, device xc3s50a, package vq100, speed -4 Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000 Celsius) Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.260 Volts) INFO:Par:282 - No user timing constraints were detected or you have set the option to ignore timing constraints ("par -x"). Place and Route will run in "Performance Evaluation Mode" to automatically improve the performance of all internal clocks in this design. Because there are not defined timing requirements, a timing score will not be reported in the PAR report in this mode. The PAR timing summary will list the performance achieved for each clock. Note: For the fastest runtime, set the effort level to "std". For best performance, set the effort level to "high". Device speed data version: "PRODUCTION 1.42 2013-06-08". Design Summary Report: Number of External IOBs 37 out of 68 54% Number of External Input IOBs 9 Number of External Input IBUFs 9 Number of LOCed External Input IBUFs 9 out of 9 100% Number of External Output IOBs 19 Number of External Output IOBs 19 Number of LOCed External Output IOBs 19 out of 19 100% Number of External Bidir IOBs 9 Number of External Bidir IOBs 9 Number of LOCed External Bidir IOBs 9 out of 9 100% Number of BUFGMUXs 2 out of 24 8% Number of DCMs 1 out of 2 50% Number of RAMB16BWEs 1 out of 3 33% Number of Slices 702 out of 704 99% Number of SLICEMs 4 out of 352 1% Number of STARTUPs 1 out of 1 100% Overall effort level (-ol): High Placer effort level (-pl): High Placer cost table entry (-t): 1 Router effort level (-rl): High Starting initial Timing Analysis. REAL time: 1 secs Finished initial Timing Analysis. REAL time: 1 secs Starting Placer Total REAL time at the beginning of Placer: 1 secs Total CPU time at the beginning of Placer: 1 secs Phase 1.1 Initial Placement Analysis Phase 1.1 Initial Placement Analysis (Checksum:7a072f) REAL time: 1 secs Phase 2.7 Design Feasibility Check Phase 2.7 Design Feasibility Check (Checksum:7a072f) REAL time: 1 secs Phase 3.31 Local Placement Optimization Phase 3.31 Local Placement Optimization (Checksum:3e843186) REAL time: 1 secs Phase 4.2 Initial Clock and IO Placement ............ WARNING:Place:1013 - A clock IOB / DCM component pair have been found that are not placed at an optimal clock IOB / DCM site pair. The clock component is placed at site . The clock IO/DCM site can be paired if they are placed/locked in the same quadrant. The IO component is placed at site . This will not allow the use of the fast path between the IO and the Clock buffer. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint was applied on COMP.PIN allowing your design to continue. This constraint disables all clock placer rules related to the specified COMP.PIN. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. Phase 4.2 Initial Clock and IO Placement (Checksum:84fb9935) REAL time: 2 secs Phase 5.30 Global Clock Region Assignment Phase 5.30 Global Clock Region Assignment (Checksum:84fb9935) REAL time: 2 secs Phase 6.36 Local Placement Optimization Phase 6.36 Local Placement Optimization (Checksum:84fb9935) REAL time: 2 secs Phase 7.8 Global Placement ..... ................................................... .......................................... ........................................................ ................................................................................. ................................................................................................. Phase 7.8 Global Placement (Checksum:bdea24aa) REAL time: 3 secs Phase 8.5 Local Placement Optimization Phase 8.5 Local Placement Optimization (Checksum:bdea24aa) REAL time: 3 secs Phase 9.18 Placement Optimization Phase 9.18 Placement Optimization (Checksum:ae8a1c2b) REAL time: 5 secs Phase 10.5 Local Placement Optimization Phase 10.5 Local Placement Optimization (Checksum:ae8a1c2b) REAL time: 5 secs Total REAL time to Placer completion: 5 secs Total CPU time to Placer completion: 5 secs Writing design to file FPGA_main.ncd Starting Router Phase 1 : 5211 unrouted; REAL time: 6 secs Phase 2 : 4687 unrouted; REAL time: 6 secs Phase 3 : 1437 unrouted; REAL time: 6 secs Phase 4 : 1534 unrouted; (Par is working to improve performance) REAL time: 6 secs Phase 5 : 0 unrouted; (Par is working to improve performance) REAL time: 7 secs Updating file: FPGA_main.ncd with current fully routed design. Phase 6 : 0 unrouted; (Par is working to improve performance) REAL time: 7 secs Phase 7 : 0 unrouted; (Par is working to improve performance) REAL time: 9 secs Phase 8 : 0 unrouted; (Par is working to improve performance) REAL time: 9 secs Phase 9 : 0 unrouted; (Par is working to improve performance) REAL time: 9 secs Phase 10 : 0 unrouted; (Par is working to improve performance) REAL time: 9 secs Phase 11 : 0 unrouted; (Par is working to improve performance) REAL time: 10 secs WARNING:Route:455 - CLK Net:Eth_CLK_OBUF may have excessive skew because 0 CLK pins and 2 NON_CLK pins failed to route using a CLK template. WARNING:Route:455 - CLK Net:SPI_SCLK_OBUF may have excessive skew because 0 CLK pins and 8 NON_CLK pins failed to route using a CLK template. Total REAL time to Router completion: 10 secs Total CPU time to Router completion: 9 secs Partition Implementation Status ------------------------------- No Partitions were found in this design. ------------------------------- Generating "PAR" statistics. ************************** Generating Clock Report ************************** +---------------------+--------------+------+------+------------+-------------+ | Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)| +---------------------+--------------+------+------+------------+-------------+ | Eth_CLK_OBUF | BUFGMUX_X2Y10| No | 476 | 0.236 | 0.696 | +---------------------+--------------+------+------+------------+-------------+ | SPI_SCLK_OBUF | BUFGMUX_X1Y10| No | 33 | 0.124 | 0.589 | +---------------------+--------------+------+------+------------+-------------+ * Net Skew is the difference between the minimum and maximum routing only delays for the net. Note this is different from Clock Skew which is reported in TRCE timing report. Clock Skew is the difference between the minimum and maximum path delays which includes logic delays. * The fanout is the number of component pins not the individual BEL loads, for example SLICE loads not FF loads. Timing Score: 0 (Setup: 0, Hold: 0) Asterisk (*) preceding a constraint indicates it was not met. This may be due to a setup or hold violation. ---------------------------------------------------------------------------------------------------------- Constraint | Check | Worst Case | Best Case | Timing | Timing | | Slack | Achievable | Errors | Score ---------------------------------------------------------------------------------------------------------- Autotimespec constraint for clock net Eth | SETUP | N/A| 12.017ns| N/A| 0 _CLK_OBUF | HOLD | 0.853ns| | 0| 0 ---------------------------------------------------------------------------------------------------------- Autotimespec constraint for clock net SPI | SETUP | N/A| 6.867ns| N/A| 0 _SCLK_OBUF | HOLD | 1.122ns| | 0| 0 ---------------------------------------------------------------------------------------------------------- All constraints were met. INFO:Timing:2761 - N/A entries in the Constraints List may indicate that the constraint is not analyzed due to the following: No paths covered by this constraint; Other constraints intersect with this constraint; or This constraint was disabled by a Path Tracing Control. Please run the Timespec Interaction Report (TSI) via command line (trce tsi) or Timing Analyzer GUI. Generating Pad Report. All signals are completely routed. Total REAL time to PAR completion: 10 secs Total CPU time to PAR completion: 10 secs Peak Memory Usage: 306 MB Placement: Completed - No errors found. Routing: Completed - No errors found. Number of error messages: 0 Number of warning messages: 3 Number of info messages: 1 Writing design to file FPGA_main.ncd PAR done!