----------------------------------------------------------------------------------
-- Company: University of Connecticut
-- Engineer: Igor Senderovich
-- 
-- Create Date:    10:35:58 10/24/2007 
-- Design Name: 
-- Module Name:    DAC_writer - behavioral 
-- Description:    Reads voltage values from RAM and writes them to the DAC
----------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;

library FPGA_BasicComp;
use FPGA_BasicComp.BasicComp.all;
use FPGA_BasicComp.FPGA_config.all;

entity DAC_writer is
    port ( Clk : in std_logic;
           Go : in std_logic;
           Done : out std_logic;
	   RAM_EN : out std_logic;
	   RAM_ADDR_tri : out std_logic_vector (9 downto 0);
	   RAM_WE_tri : out std_logic_vector (1 downto 0);
	   RAM_DI_tri : out std_logic_vector (15 downto 0);
	   RAM_DO : in std_logic_vector (15 downto 0);
	   DAC_control_Go : out std_logic;
	   DAC_control_Done : in std_logic;
	   DAC_Addr : out std_logic_vector (4 downto 0);
	   DAC_Code : out std_logic_vector (13 downto 0));
	   --Ser_Go : out std_logic;
	   --Ser_Done : in std_logic;
	   --Ser_D_tri : out std_logic_vector (7 downto 0);
	   --Debug : out std_logic);
end DAC_writer;

architecture behavioral of DAC_writer is

	type stage_t is (S0,S1,S2,S3,S4,S5); --,SS);
	signal stage : stage_t := S0;

	signal Done_reg : std_logic := '0';

	signal RAM_EN_reg : std_logic := '0';
	signal RAM_ADDR_reg : std_logic_vector (9 downto 0) := (others => '0');
	signal RAM_WE_reg : std_logic_vector (1 downto 0) := (others => '0');
	signal RAM_DI_reg : std_logic_vector (15 downto 0) := (others => '0');

	signal DAC_control_Go_reg : std_logic := '0';
	signal DAC_Addr_reg : std_logic_vector (4 downto 0) := (others => '0');
	signal DAC_Code_reg : std_logic_vector (13 downto 0) := (others => '0');

	--signal Ser_Go_reg : std_logic := '0';
	--signal Ser_D_reg : std_logic_vector (7 downto 0) := (others => '0');
	--signal Debug_reg : std_logic := '0';
begin
	RAM_EN <= RAM_EN_reg;
	RAM_ADDR_tri <= RAM_ADDR_reg when (RAM_EN_reg = '1') else (others => 'Z');
	RAM_WE_tri <= RAM_WE_reg when (RAM_EN_reg = '1') else (others => 'Z');
	RAM_DI_tri <= RAM_DI_reg when (RAM_EN_reg = '1') else (others => 'Z');

	-- Sequence through the 32 RAM addresses from 0 to 31
	Sequencer : process (Clk)
		variable address_var : integer range 0 to 31;
		variable channel_var : integer range 0 to 31;
		variable DAC_offset_var : integer range -1023 to +1023;
		variable DAC_limit_var : integer range 0 to 16383;
		variable DAC_value_var : integer range -1023 to 17406;
		variable DAC_margin_var : integer range -17406 to 17406;
		variable DAC_value_vec : std_logic_vector (15 downto 0);
		variable DAC_margin_vec : std_logic_vector (15 downto 0);
		variable op_complete_var : std_logic;
	begin
		if rising_edge(Clk) then
			stage <= stage;
			Done_reg <= '0';
			DAC_Addr_reg <= (others => '0');
			DAC_Code_reg <= (others => '0');
			DAC_control_Go_reg <= '0';
			-- disable the RAM lines when not in use
			RAM_En_reg <= '0';
			RAM_WE_reg <= (others => '0');
			RAM_DI_reg <= (others => '0');
			RAM_ADDR_reg <= (others => '0');
			-- disable the serial lines when not in use
			--Ser_Go_reg <= '0';
			--Ser_D_reg <= (others => '0');
			--Debug_reg <= '0';

			op_complete_var := DAC_control_Go_reg and DAC_control_Done;

			case stage is
			    when S0 =>
				if (Go = '1') then
					RAM_En_reg <= '1';
					RAM_ADDR_reg <= "0001000000";
					stage <= S1;
				end if;
			    when S1 =>
				RAM_En_reg <= '1';
				RAM_ADDR_reg <= RAM_ADDR_reg;
				stage <= S2;
			    when S2 =>
				RAM_En_reg <= '1';
				RAM_ADDR_reg <= RAM_ADDR_reg;
				address_var := conv_integer(RAM_ADDR_reg(4 downto 0));
				channel_var := DAC_channel_map(address_var);
				DAC_offset_var := DAC_offset_table(address_var);
				DAC_limit_var := DAC_limit_table(address_var);
				DAC_value_var := conv_integer(RAM_DO) + DAC_offset_var;
				DAC_margin_var := DAC_limit_var - DAC_value_var;
				DAC_margin_vec := conv_std_logic_vector(DAC_margin_var, 16);
				DAC_value_vec := conv_std_logic_vector(DAC_value_var, 16);
				DAC_Addr_reg <= conv_std_logic_vector(channel_var,5);
				if (DAC_margin_vec(15) = '1') then
					DAC_Code_reg <= conv_std_logic_vector(DAC_limit_var,14);
				elsif (DAC_value_vec(15) = '1') then
					DAC_Code_reg <= (others => '0');
				elsif (DAC_value_vec(14) = '1') then
					DAC_Code_reg <= (others => '1');
				else
					DAC_Code_reg <= DAC_value_vec(13 downto 0);
				end if;
				DAC_control_Go_reg <= '1';
				stage <= S3;
			    when S3 =>
				RAM_EN_reg <= '1';
				RAM_ADDR_reg <= RAM_ADDR_reg;
				DAC_Code_reg <= DAC_Code_reg;
				DAC_Addr_reg <= DAC_Addr_reg;
				DAC_control_Go_reg <= not DAC_control_Done;
				if (op_complete_var = '1') then
					RAM_ADDR_reg <= RAM_ADDR_reg + 1;
					stage <= S4;
				end if;
			    when S4 =>
				RAM_EN_reg <= '1';
				RAM_ADDR_reg <= RAM_ADDR_reg;
				if (RAM_ADDR_reg(5) = '0') then
					stage <= S2;
				else
					stage <= S5;
				end if;
			--    when SS =>
			--	Ser_Go_reg <= not Ser_Done;
			--	Ser_D_reg <= X"44";
			--	if (Ser_Done = '1') then
			--		stage <= S6;
			--	end if;
			    when S5 =>
				if (Go = '1') then
					Done_reg <= '1';
				else
					stage <= S0;
				end if;
			end case;
		else
			stage <= stage;
			Done_reg <= Done_reg;
			RAM_En_reg <= RAM_En_reg;
			RAM_WE_reg <= RAM_WE_reg;
			RAM_DI_reg <= RAM_DI_reg;
			RAM_ADDR_reg <= RAM_ADDR_reg;
			DAC_Addr_reg <= DAC_Addr_reg;
			DAC_Code_reg <= DAC_Code_reg;
			DAC_control_Go_reg <= DAC_control_Go_reg;
			--Ser_Go_reg <= Ser_Go_reg;
			--Ser_D_reg <= Ser_D_reg;
			--Debug_reg <= Debug_reg;
		end if;
	end process;

	DAC_control_Go <= DAC_control_Go_reg;
	DAC_Addr <= DAC_Addr_reg;
	DAC_Code <= DAC_Code_reg;

	--Ser_Go <= Ser_Go_reg;
	--Ser_D_tri <= Ser_D_reg when (Ser_Go_reg = '1') else (others => 'Z');
	--Debug <= Debug_reg;

	Done <= Done_reg;

end behavioral;