TotalTest Project Status
Project File: TotalTest.ise Implementation State: New
Module Name: wr2BtoAddr_good
  • Errors:
 
Target Device: xc3s50a-4vq100
  • Warnings:
 
Product Version:ISE 11.3
  • Routing Results:
 
Design Goal: Balanced
  • Timing Constraints:
 
Design Strategy: Xilinx Default (unlocked)
  • Final Timing Score:
  
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis Report     
Translation Report     
Map Report     
Place and Route Report     
Power Report     
Post-PAR Static Timing Report     
Bitgen Report     
 
Secondary Reports [-]
Report NameStatusGenerated
ISIM Simulator LogCurrentWed Aug 19 00:14:20 2009

Date Generated: 10/06/2009 - 20:22:42