DESIGN RULE CHECK VIOLATION REPORT Build: PlanAhead v11.2 by hdbuild on Tue Jun 2 13:30:28 PDT 2009 Report: by M on host TOSHIBA-Laptop, pid 1312 on Wed Jul 15 14:07:44 2009 REPORT SUMMARY Netlist: netlist_1 Floorplan: floorplan_1 Design limits: Checks: Longest carry chain height Clock region primary secondary IBUFG to DCM connectivity DCM to BUFG connectivity Number of BUFGs allowed for DCM DCM and BUFG connectivity BufR & BufIO Locations Pblock overlap Pblock partition Bank IO standard Vcc Bank IO standard Support Bank IO standard Termination Bank IO standard Vref Bank IO standard Vref Occupied Bank IO standard limits Bank IO standard VRN/VRP Occupied Inconsistent Diff pair IOStandards Inconsistent Diff pair IOStandards Inconsistent Diff pair IOStandards Vccaux voltage requirement for LVCMOS25 Vccaux voltage requirement for LVPECL_33 and TMDS_33 Resource utilization IOB clock sharing IOB set reset sharing Differential IO pads DSP output registers DSP input registers DSP output pipelining DSP multiplier output pipelining DSP input pipelining RAMB16 output registers IOStandard Type Number of IOs IOs placed on disallowed sites Part compatibility implied prohibits not respected MGT not allowed for part compatibility Driverless Nets Black Box Instances Area group tile alignment Max vios: Vios found: 2 REPORT DETAILS IOPL#1 IOs placed on disallowed sites - Clock terminal Rst is placed at a non clock capable site P36 Related Vios: IOPL#2 IOs placed on disallowed sites - Clock terminal fClk is placed at a non clock capable site P27 Related Vios: