Project Navigator session log file for project TotalTest Created October 1 2010 Launching Design Summary/Report Viewer... Reading design: FPGA_ctrl.prj ========================================================================= * HDL Compilation * ========================================================================= WARNING:HDLParsers:3607 - Unit FPGA_BasicComp/Reg16x8bit_wPrim is now defined in a different file. It was defined in "C:/work/GlueX/Tagger/Electronics/FPGA/MiscComp/Reg64x8bit_wPrim.vhd", and is now defined in "C:/work/GlueX/Tagger/Electronics/FPGA/MiscComp/Reg256x8bit_wPrim.vhd". WARNING:HDLParsers:3607 - Unit FPGA_BasicComp/Reg16x8bit_wPrim/Behavioral is now defined in a different file. It was defined in "C:/work/GlueX/Tagger/Electronics/FPGA/MiscComp/Reg64x8bit_wPrim.vhd", and is now defined in "C:/work/GlueX/Tagger/Electronics/FPGA/MiscComp/Reg256x8bit_wPrim.vhd". WARNING:HDLParsers:3607 - Unit FPGA_BasicComp/Reg16x8bit_wPrim is now defined in a different file. It was defined in "C:/work/GlueX/Tagger/Electronics/FPGA/MiscComp/Reg256x8bit_wPrim.vhd", and is now defined in "C:/work/GlueX/Tagger/Electronics/FPGA/MiscComp/Reg64x8bit_wPrim.vhd". WARNING:HDLParsers:3607 - Unit FPGA_BasicComp/Reg16x8bit_wPrim/Behavioral is now defined in a different file. It was defined in "C:/work/GlueX/Tagger/Electronics/FPGA/MiscComp/Reg256x8bit_wPrim.vhd", and is now defined in "C:/work/GlueX/Tagger/Electronics/FPGA/MiscComp/Reg64x8bit_wPrim.vhd". Compiling vhdl file "C:/work/GlueX/Tagger/Electronics/FPGA/MiscComp/delay.vhd" in Library FPGA_BasicComp. Architecture delay_behavioral of Entity c_delay is up to date. Architecture dbldelay_behavioral of Entity c_dbldelay is up to date. Compiling vhdl file "C:/work/GlueX/Tagger/Electronics/FPGA/MiscComp/Pulser/Pulser.vhd" in Library FPGA_BasicComp. Architecture behavioral of Entity pulser is up to date. Compiling vhdl file "C:/work/GlueX/Tagger/Electronics/FPGA/MiscComp/Reg64x8bit_wPrim.vhd" in Library FPGA_BasicComp. Architecture behavioral of Entity reg64x8bit_wprim is up to date. Architecture behavioral of Entity reg16x8bit_wprim is up to date. Compiling vhdl file "C:/work/GlueX/Tagger/Electronics/FPGA/Includes.vhd" in Library FPGA_BasicComp. Architecture behavioral of Entity pulse_delay is up to date. Architecture behavioral of Entity trigger is up to date. Architecture behavioral of Entity droponsig is up to date. Architecture behavioral of Entity countevents is up to date. Compiling vhdl file "C:/work/GlueX/Tagger/Electronics/FPGA/MiscComp/Reg8bit.vhd" in Library FPGA_BasicComp. Architecture behavioral of Entity reg8bit is up to date. Compiling vhdl file "C:/work/GlueX/Tagger/Electronics/FPGA/EthCtrl/MiscComp/wrToAddr/wrToAddr.vhd" in Library FPGA_BasicComp. Architecture behavioral_arch of Entity wrtoaddr is up to date. Compiling vhdl file "C:/work/GlueX/Tagger/Electronics/FPGA/MiscComp/Counter4bit.vhd" in Library FPGA_BasicComp. Architecture behavioral of Entity counter4bit is up to date. Compiling vhdl file "C:/work/GlueX/Tagger/Electronics/FPGA/EthCtrl/MiscComp/wr2BToAddr/wr2BToAddr_good.vhd" in Library FPGA_BasicComp. Architecture behavioral of Entity wr2btoaddr is up to date. Compiling vhdl file "C:/work/GlueX/Tagger/Electronics/FPGA/EthCtrl/MiscComp/MACwrToAddr.vhd" in Library FPGA_BasicComp. Architecture behavioral_arch of Entity macwrtoaddr is up to date. Compiling vhdl file "C:/work/GlueX/Tagger/Electronics/FPGA/EthCtrl/MiscComp/getByte/getByte.vhd" in Library FPGA_BasicComp. Architecture behavioral of Entity getbyte is up to date. Compiling vhdl file "C:/work/GlueX/Tagger/Electronics/FPGA/MiscComp/StepCounter16bit.vhd" in Library FPGA_BasicComp. Architecture behavioral of Entity stepcounter16bit is up to date. Compiling vhdl file "C:/work/GlueX/Tagger/Electronics/FPGA/MiscComp/Reg32x14bit_wPrim.vhd" in Library FPGA_BasicComp. Architecture behavioral of Entity reg32x14bit_wprim is up to date. Architecture behavioral of Entity reg16x14bit_wprim is up to date. Compiling vhdl file "C:/work/GlueX/Tagger/Electronics/FPGA/MiscComp/EdgeCounter4bit.vhd" in Library FPGA_BasicComp. Architecture behavioral of Entity edgecounter4bit is up to date. Compiling vhdl file "C:/work/GlueX/Tagger/Electronics/FPGA/MiscComp/Counter7bit.vhd" in Library FPGA_BasicComp. Architecture behavioral of Entity counter7bit is up to date. Compiling vhdl file "C:/work/GlueX/Tagger/Electronics/FPGA/MiscComp/Counter12bit.vhd" in Library FPGA_BasicComp. Architecture behavioral of Entity counter12bit is up to date. Compiling vhdl file "C:/work/GlueX/Tagger/Electronics/FPGA/EthCtrl/Querier/GetTempVal.vhd" in Library FPGA_BasicComp. Architecture contr_arch of Entity gettempval is up to date. Compiling vhdl file "C:/work/GlueX/Tagger/Electronics/FPGA/SerialOut.vhd" in Library FPGA_BasicComp. Architecture behavioral of Entity serialout is up to date. Architecture behavioral of Entity serialoutfifo is up to date. Compiling vhdl file "C:/work/GlueX/Tagger/Electronics/FPGA/DAC_v2/DAC_controller.vhd" in Library FPGA_BasicComp. Architecture dac_control_arch of Entity dac_controller is up to date. Compiling vhdl file "C:/work/GlueX/Tagger/Electronics/FPGA/MiscComp/Reg256x8bit_wPrim.vhd" in Library FPGA_BasicComp. Architecture behavioral of Entity reg256x8bit_wprim is up to date. Architecture behavioral of Entity reg16x8bit_wprim is up to date. Compiling vhdl file "C:/work/GlueX/Tagger/Electronics/FPGA/EthCtrl/MiscComp/RAwr2BtoAddr.vhd" in Library work. Architecture behavioral of Entity rawr2btoaddr is up to date. Compiling vhdl file "C:/work/GlueX/Tagger/Electronics/FPGA/EthCtrl/MiscComp/AutoRd.vhd" in Library work. Architecture behavioral of Entity autord is up to date. Compiling vhdl file "C:/work/GlueX/Tagger/Electronics/FPGA/EthCtrl/Querier/GetADCval.vhd" in Library work. Architecture contr_arch of Entity getadcval is up to date. Compiling vhdl file "C:/work/GlueX/Tagger/Electronics/FPGA/EthCtrl/Transmitter/wrMACaddrs.vhd" in Library work. Architecture behavioral of Entity wrmacaddrs is up to date. Compiling vhdl file "C:/work/GlueX/Tagger/Electronics/FPGA/EthCtrl/Transmitter/D-Packet.vhd" in Library work. Architecture behavioral of Entity dpacket is up to date. Compiling vhdl file "C:/work/GlueX/Tagger/Electronics/FPGA/EthCtrl/Transmitter/S-Packet.vhd" in Library work. Architecture behavioral of Entity spacket is up to date. Compiling vhdl file "C:/work/GlueX/Tagger/Electronics/FPGA/EthCtrl/Reset/MACaddrLoad.vhd" in Library work. Architecture behavioral of Entity macaddrload is up to date. Compiling vhdl file "C:/work/GlueX/Tagger/Electronics/FPGA/Config.vhd" in Library work. Architecture behavioral of Entity configparam is up to date. Compiling vhdl file "C:/work/GlueX/Tagger/Electronics/FPGA/EthCtrl/Register/statereg.vhd" in Library work. Architecture behavioral of Entity statereg is up to date. Compiling vhdl file "C:/work/GlueX/Tagger/Electronics/FPGA/EthCtrl/Register/MACregs.vhd" in Library work. Architecture behavioral of Entity macregs is up to date. Compiling vhdl file "C:/work/GlueX/Tagger/Electronics/FPGA/EthCtrl/Register/DACregs.vhd" in Library work. Architecture behavioral of Entity dacregs is up to date. Compiling vhdl file "C:/work/GlueX/Tagger/Electronics/FPGA/EthCtrl/Register/TempReg.vhd" in Library work. Architecture behavioral of Entity tempreg is up to date. Compiling vhdl file "C:/work/GlueX/Tagger/Electronics/FPGA/EthCtrl/Register/ADCregs.vhd" in Library work. Architecture behavioral of Entity adcregs is up to date. Compiling vhdl file "C:/work/GlueX/Tagger/Electronics/FPGA/EthCtrl/MiscComp/INTCatcher/INTCatcher.vhd" in Library work. Architecture behavioral of Entity intcatcher is up to date. Compiling vhdl file "C:/work/GlueX/Tagger/Electronics/FPGA/EthCtrl/Transceiver/Transceiver_ctrl.vhd" in Library work. Architecture behavioral of Entity transceiver is up to date. Compiling vhdl file "C:/work/GlueX/Tagger/Electronics/FPGA/EthCtrl/Reset/Reset_hard.vhd" in Library work. Architecture behavioral of Entity reset_hard is up to date. Compiling vhdl file "C:/work/GlueX/Tagger/Electronics/FPGA/EthCtrl/Reset/Reset_soft.vhd" in Library work. Architecture behavioral of Entity reset_soft is up to date. Compiling vhdl file "C:/work/GlueX/Tagger/Electronics/FPGA/EthCtrl/Transmitter/Transmitter_ctrl.vhd" in Library work. Architecture behavioral of Entity transmitter is up to date. Compiling vhdl file "C:/work/GlueX/Tagger/Electronics/FPGA/EthCtrl/Idler/Idler_ctrl.vhd" in Library work. Architecture behavioral of Entity idler_ctrl is up to date. Compiling vhdl file "C:/work/GlueX/Tagger/Electronics/FPGA/EthCtrl/Querier/Query_coord.vhd" in Library work. Architecture behavioral of Entity querier is up to date. Compiling vhdl file "C:/work/GlueX/Tagger/Electronics/FPGA/EthCtrl/Reader/Reader_ctrl.vhd" in Library work. Architecture behavioral of Entity reader is up to date. Compiling vhdl file "C:/work/GlueX/Tagger/Electronics/FPGA/EthCtrl/Programmer/Programmer_ctrl.vhd" in Library work. Architecture behavioral of Entity programmer_ctrl is up to date. Compiling vhdl file "C:/work/GlueX/Tagger/Electronics/FPGA/FPGA_ctrl.vhd" in Library work. Architecture behavioral of Entity fpga_ctrl is up to date. ========================================================================= * Design Hierarchy Analysis * ========================================================================= Analyzing hierarchy for entity in library (architecture ). Analyzing hierarchy for entity in library (architecture ). Analyzing hierarchy for entity in library (architecture ). Analyzing hierarchy for entity in library (architecture ). Analyzing hierarchy for entity in library (architecture ). Analyzing hierarchy for entity in library (architecture ). Analyzing hierarchy for entity in library (architecture ). Analyzing hierarchy for entity in library (architecture ). Analyzing hierarchy for entity in library (architecture ). Analyzing hierarchy for entity in library (architecture ). Analyzing hierarchy for entity in library (architecture ). Analyzing hierarchy for entity in library (architecture ). Analyzing hierarchy for entity in library (architecture ). Analyzing hierarchy for entity in library (architecture ). Analyzing hierarchy for entity in library (architecture ). Analyzing hierarchy for entity in library (architecture ). Analyzing hierarchy for entity in library (architecture ). Analyzing hierarchy for entity in library (architecture ). Analyzing hierarchy for entity in library (architecture ). Analyzing hierarchy for entity in library (architecture ). Analyzing hierarchy for entity in library (architecture ). Analyzing hierarchy for entity in library (architecture ). Analyzing hierarchy for entity in library (architecture ). Analyzing hierarchy for entity in library (architecture ). Analyzing hierarchy for entity in library (architecture ). Analyzing hierarchy for entity in library (architecture ). Analyzing hierarchy for entity in library (architecture ). Analyzing hierarchy for entity in library (architecture ). Analyzing hierarchy for entity in library (architecture ). Analyzing hierarchy for entity in library (architecture ). Analyzing hierarchy for entity in library (architecture ). Analyzing hierarchy for entity in library (architecture ). Analyzing hierarchy for entity in library (architecture ). Analyzing hierarchy for entity in library (architecture ). Analyzing hierarchy for entity in library (architecture ). Analyzing hierarchy for entity in library (architecture ). Analyzing hierarchy for entity in library (architecture ). Analyzing hierarchy for entity in library (architecture ). Analyzing hierarchy for entity in library (architecture ). Analyzing hierarchy for entity in library (architecture ). Analyzing hierarchy for entity in library (architecture ). Analyzing hierarchy for entity in library (architecture ). Analyzing hierarchy for entity in library (architecture ). Analyzing hierarchy for entity in library (architecture ). Analyzing hierarchy for entity in library (architecture ). Analyzing hierarchy for entity in library (architecture ). Analyzing hierarchy for entity in library (architecture ). Analyzing hierarchy for entity in library (architecture ). Analyzing hierarchy for entity in library (architecture ). Analyzing hierarchy for entity in library (architecture ). Analyzing hierarchy for entity in library (architecture ). Analyzing hierarchy for entity in library (architecture ). Analyzing hierarchy for entity in library (architecture ). Analyzing hierarchy for entity in library (architecture ). Analyzing hierarchy for entity in library (architecture ). Analyzing hierarchy for entity in library (architecture ). Analyzing hierarchy for entity in library (architecture ). Analyzing hierarchy for entity in library (architecture ). Analyzing hierarchy for entity in library (architecture ). Analyzing hierarchy for entity in library (architecture ). ========================================================================= * HDL Analysis * ========================================================================= Analyzing Entity in library (Architecture ). WARNING:Xst:753 - "C:/work/GlueX/Tagger/Electronics/FPGA/FPGA_ctrl.vhd" line 193: Unconnected output port 'db' of component 'INTCatcher'. WARNING:Xst:753 - "C:/work/GlueX/Tagger/Electronics/FPGA/FPGA_ctrl.vhd" line 197: Unconnected output port 'TxRx_db' of component 'Transceiver'. WARNING:Xst:753 - "C:/work/GlueX/Tagger/Electronics/FPGA/FPGA_ctrl.vhd" line 212: Unconnected output port 'db' of component 'SerialOutFIFO'. WARNING:Xst:753 - "C:/work/GlueX/Tagger/Electronics/FPGA/FPGA_ctrl.vhd" line 235: Unconnected output port 'db' of component 'Transmitter'. WARNING:Xst:753 - "C:/work/GlueX/Tagger/Electronics/FPGA/FPGA_ctrl.vhd" line 243: Unconnected output port 'db' of component 'Idler_ctrl'. WARNING:Xst:753 - "C:/work/GlueX/Tagger/Electronics/FPGA/FPGA_ctrl.vhd" line 253: Unconnected output port 'db' of component 'Reader'. WARNING:Xst:753 - "C:/work/GlueX/Tagger/Electronics/FPGA/FPGA_ctrl.vhd" line 257: Unconnected output port 'db1' of component 'Programmer_ctrl'. WARNING:Xst:753 - "C:/work/GlueX/Tagger/Electronics/FPGA/FPGA_ctrl.vhd" line 257: Unconnected output port 'db2' of component 'Programmer_ctrl'. Entity analyzed. Unit generated. Analyzing Entity in library (Architecture ). Entity analyzed. Unit generated. Analyzing Entity in library (Architecture ). Entity analyzed. Unit generated. Analyzing Entity in library (Architecture ). Entity analyzed. Unit generated. Analyzing Entity in library (Architecture ). Entity analyzed. Unit generated. Analyzing Entity in library (Architecture ). Entity analyzed. Unit generated. Analyzing Entity in library (Architecture ). Set user-defined property "INIT = 0000" for instance in unit . Set user-defined property "INIT = 0000" for instance in unit . Set user-defined property "INIT = 0000" for instance in unit . Set user-defined property "INIT = 0000" for instance in unit . Set user-defined property "INIT = 0000" for instance in unit . Set user-defined property "INIT = 0000" for instance in unit . Set user-defined property "INIT = 0000" for instance in unit . Set user-defined property "INIT = 0000" for instance in unit . Set user-defined property "INIT = 0000" for instance in unit . Set user-defined property "INIT = 0000" for instance in unit . Set user-defined property "INIT = 0000" for instance in unit . Set user-defined property "INIT = 0000" for instance in unit . Set user-defined property "INIT = 0000" for instance in unit . Set user-defined property "INIT = 0000" for instance in unit . Entity analyzed. Unit generated. Analyzing Entity in library (Architecture ). Entity analyzed. Unit generated. Analyzing Entity in library (Architecture ). Entity analyzed. Unit generated. Analyzing Entity in library (Architecture ). Entity analyzed. Unit generated. Analyzing Entity in library (Architecture ). Entity analyzed. Unit generated. Analyzing Entity in library (Architecture ). Entity analyzed. Unit generated. Analyzing Entity in library (Architecture ). Entity analyzed. Unit generated. Analyzing Entity in library (Architecture ). Entity analyzed. Unit generated. Analyzing Entity in library (Architecture ). Entity analyzed. Unit generated. Analyzing Entity in library (Architecture ). Set user-defined property "CLKDV_DIVIDE = 4.0000000000000000" for instance in unit . Set user-defined property "CLKFX_DIVIDE = 1" for instance in unit . Set user-defined property "CLKFX_MULTIPLY = 4" for instance in unit . Set user-defined property "CLKIN_DIVIDE_BY_2 = FALSE" for instance in unit . Set user-defined property "CLKIN_PERIOD = 10.0000000000000000" for instance in unit . Set user-defined property "CLKOUT_PHASE_SHIFT = NONE" for instance in unit . Set user-defined property "CLK_FEEDBACK = 1X" for instance in unit . Set user-defined property "DESKEW_ADJUST = SYSTEM_SYNCHRONOUS" for instance in unit . Set user-defined property "DFS_FREQUENCY_MODE = LOW" for instance in unit . Set user-defined property "DLL_FREQUENCY_MODE = LOW" for instance in unit . Set user-defined property "DSS_MODE = NONE" for instance in unit . Set user-defined property "DUTY_CYCLE_CORRECTION = TRUE" for instance in unit . Set user-defined property "FACTORY_JF = C080" for instance in unit . Set user-defined property "PHASE_SHIFT = 0" for instance in unit . Set user-defined property "STARTUP_WAIT = FALSE" for instance in unit . Entity analyzed. Unit generated. Analyzing Entity in library (Architecture ). WARNING:Xst:819 - "C:/work/GlueX/Tagger/Electronics/FPGA/MiscComp/EdgeCounter4bit.vhd" line 33: One or more signals are missing in the process sensitivity list. To enable synthesis of FPGA/CPLD hardware, XST will assume that all necessary signals are present in the sensitivity list. Please note that the result of the synthesis may differ from the initial design specification. The missing signals are: Entity analyzed. Unit generated. Analyzing Entity in library (Architecture ). Entity analyzed. Unit generated. Analyzing Entity in library (Architecture ). Entity analyzed. Unit generated. Analyzing Entity in library (Architecture ). Set user-defined property "INIT = 0000" for instance in unit . Set user-defined property "INIT = 0000" for instance in unit . Set user-defined property "INIT = 0000" for instance in unit . Set user-defined property "INIT = 0000" for instance in unit . Set user-defined property "INIT = 0000" for instance in unit . Set user-defined property "INIT = 0000" for instance in unit . Set user-defined property "INIT = 0000" for instance in unit . Set user-defined property "INIT = 0000" for instance in unit . Entity analyzed. Unit generated. Analyzing Entity in library (Architecture ). WARNING:Xst:819 - "C:/work/GlueX/Tagger/Electronics/FPGA/SerialOut.vhd" line 57: One or more signals are missing in the process sensitivity list. To enable synthesis of FPGA/CPLD hardware, XST will assume that all necessary signals are present in the sensitivity list. Please note that the result of the synthesis may differ from the initial design specification. The missing signals are: Entity analyzed. Unit generated. Analyzing Entity in library (Architecture ). WARNING:Xst:819 - "C:/work/GlueX/Tagger/Electronics/FPGA/EthCtrl/Reset/Reset_hard.vhd" line 130: One or more signals are missing in the process sensitivity list. To enable synthesis of FPGA/CPLD hardware, XST will assume that all necessary signals are present in the sensitivity list. Please note that the result of the synthesis may differ from the initial design specification. The missing signals are: WARNING:Xst:753 - "C:/work/GlueX/Tagger/Electronics/FPGA/EthCtrl/Reset/Reset_hard.vhd" line 262: Unconnected output port 'db' of component 'MACwrToAddr'. WARNING:Xst:753 - "C:/work/GlueX/Tagger/Electronics/FPGA/EthCtrl/Reset/Reset_hard.vhd" line 268: Unconnected output port 'db' of component 'MACwrToAddr'. WARNING:Xst:753 - "C:/work/GlueX/Tagger/Electronics/FPGA/EthCtrl/Reset/Reset_hard.vhd" line 272: Unconnected output port 'db' of component 'MACwrToAddr'. WARNING:Xst:753 - "C:/work/GlueX/Tagger/Electronics/FPGA/EthCtrl/Reset/Reset_hard.vhd" line 287: Unconnected output port 'db' of component 'MACwrToAddr'. Entity analyzed. Unit generated. Analyzing Entity in library (Architecture ). Entity analyzed. Unit generated. Analyzing Entity in library (Architecture ). Entity analyzed. Unit generated. Analyzing Entity in library (Architecture ). Entity analyzed. Unit generated. Analyzing Entity in library (Architecture ). Entity analyzed. Unit generated. Analyzing Entity in library (Architecture ). Entity analyzed. Unit generated. Analyzing Entity in library (Architecture ). WARNING:Xst:753 - "C:/work/GlueX/Tagger/Electronics/FPGA/EthCtrl/Reset/MACaddrLoad.vhd" line 137: Unconnected output port 'db' of component 'MACwrToAddr'. WARNING:Xst:819 - "C:/work/GlueX/Tagger/Electronics/FPGA/EthCtrl/Reset/MACaddrLoad.vhd" line 152: One or more signals are missing in the process sensitivity list. To enable synthesis of FPGA/CPLD hardware, XST will assume that all necessary signals are present in the sensitivity list. Please note that the result of the synthesis may differ from the initial design specification. The missing signals are: WARNING:Xst:819 - "C:/work/GlueX/Tagger/Electronics/FPGA/EthCtrl/Reset/MACaddrLoad.vhd" line 168: One or more signals are missing in the process sensitivity list. To enable synthesis of FPGA/CPLD hardware, XST will assume that all necessary signals are present in the sensitivity list. Please note that the result of the synthesis may differ from the initial design specification. The missing signals are: Entity analyzed. Unit generated. Analyzing Entity in library (Architecture ). Entity analyzed. Unit generated. Analyzing Entity in library (Architecture ). Entity analyzed. Unit generated. Analyzing Entity in library (Architecture ). Entity analyzed. Unit generated. Analyzing Entity in library (Architecture ). Entity analyzed. Unit generated. Analyzing Entity in library (Architecture ). WARNING:Xst:819 - "C:/work/GlueX/Tagger/Electronics/FPGA/EthCtrl/Transmitter/Transmitter_ctrl.vhd" line 268: One or more signals are missing in the process sensitivity list. To enable synthesis of FPGA/CPLD hardware, XST will assume that all necessary signals are present in the sensitivity list. Please note that the result of the synthesis may differ from the initial design specification. The missing signals are: , Entity analyzed. Unit generated. Analyzing Entity in library (Architecture ). Entity analyzed. Unit generated. Analyzing Entity in library (Architecture ). Entity analyzed. Unit generated. Analyzing Entity in library (Architecture ). Entity analyzed. Unit generated. Analyzing Entity in library (Architecture ). WARNING:Xst:819 - "C:/work/GlueX/Tagger/Electronics/FPGA/EthCtrl/MiscComp/RAwr2BtoAddr.vhd" line 75: One or more signals are missing in the process sensitivity list. To enable synthesis of FPGA/CPLD hardware, XST will assume that all necessary signals are present in the sensitivity list. Please note that the result of the synthesis may differ from the initial design specification. The missing signals are: , , Entity analyzed. Unit generated. Analyzing Entity in library (Architecture ). WARNING:Xst:819 - "C:/work/GlueX/Tagger/Electronics/FPGA/EthCtrl/Transmitter/S-Packet.vhd" line 96: One or more signals are missing in the process sensitivity list. To enable synthesis of FPGA/CPLD hardware, XST will assume that all necessary signals are present in the sensitivity list. Please note that the result of the synthesis may differ from the initial design specification. The missing signals are: , Entity analyzed. Unit generated. Analyzing Entity in library (Architecture ). Entity analyzed. Unit generated. Analyzing Entity in library (Architecture ). Entity analyzed. Unit generated. Analyzing Entity in library (Architecture ). WARNING:Xst:753 - "C:/work/GlueX/Tagger/Electronics/FPGA/EthCtrl/Querier/Query_coord.vhd" line 102: Unconnected output port 'ser_Go' of component 'GetTempVal'. WARNING:Xst:753 - "C:/work/GlueX/Tagger/Electronics/FPGA/EthCtrl/Querier/Query_coord.vhd" line 102: Unconnected output port 'ser_D' of component 'GetTempVal'. WARNING:Xst:753 - "C:/work/GlueX/Tagger/Electronics/FPGA/EthCtrl/Querier/Query_coord.vhd" line 102: Unconnected output port 'db' of component 'GetTempVal'. WARNING:Xst:819 - "C:/work/GlueX/Tagger/Electronics/FPGA/EthCtrl/Querier/Query_coord.vhd" line 139: One or more signals are missing in the process sensitivity list. To enable synthesis of FPGA/CPLD hardware, XST will assume that all necessary signals are present in the sensitivity list. Please note that the result of the synthesis may differ from the initial design specification. The missing signals are: Entity analyzed. Unit generated. Analyzing Entity in library (Architecture ). Entity analyzed. Unit generated. Analyzing Entity in library (Architecture ). WARNING:Xst:819 - "C:/work/GlueX/Tagger/Electronics/FPGA/EthCtrl/Querier/GetADCval.vhd" line 59: One or more signals are missing in the process sensitivity list. To enable synthesis of FPGA/CPLD hardware, XST will assume that all necessary signals are present in the sensitivity list. Please note that the result of the synthesis may differ from the initial design specification. The missing signals are: , , Entity analyzed. Unit generated. Analyzing Entity in library (Architecture ). WARNING:Xst:819 - "C:/work/GlueX/Tagger/Electronics/FPGA/EthCtrl/Reader/Reader_ctrl.vhd" line 75: One or more signals are missing in the process sensitivity list. To enable synthesis of FPGA/CPLD hardware, XST will assume that all necessary signals are present in the sensitivity list. Please note that the result of the synthesis may differ from the initial design specification. The missing signals are: WARNING:Xst:753 - "C:/work/GlueX/Tagger/Electronics/FPGA/EthCtrl/Reader/Reader_ctrl.vhd" line 95: Unconnected output port 'Done' of component 'wrToAddr'. WARNING:Xst:819 - "C:/work/GlueX/Tagger/Electronics/FPGA/EthCtrl/Reader/Reader_ctrl.vhd" line 105: One or more signals are missing in the process sensitivity list. To enable synthesis of FPGA/CPLD hardware, XST will assume that all necessary signals are present in the sensitivity list. Please note that the result of the synthesis may differ from the initial design specification. The missing signals are: WARNING:Xst:819 - "C:/work/GlueX/Tagger/Electronics/FPGA/EthCtrl/Reader/Reader_ctrl.vhd" line 100: One or more signals are missing in the process sensitivity list. To enable synthesis of FPGA/CPLD hardware, XST will assume that all necessary signals are present in the sensitivity list. Please note that the result of the synthesis may differ from the initial design specification. The missing signals are: Entity analyzed. Unit generated. Analyzing Entity in library (Architecture ). WARNING:Xst:819 - "C:/work/GlueX/Tagger/Electronics/FPGA/EthCtrl/Programmer/Programmer_ctrl.vhd" line 110: One or more signals are missing in the process sensitivity list. To enable synthesis of FPGA/CPLD hardware, XST will assume that all necessary signals are present in the sensitivity list. Please note that the result of the synthesis may differ from the initial design specification. The missing signals are: WARNING:Xst:819 - "C:/work/GlueX/Tagger/Electronics/FPGA/EthCtrl/Programmer/Programmer_ctrl.vhd" line 187: One or more signals are missing in the process sensitivity list. To enable synthesis of FPGA/CPLD hardware, XST will assume that all necessary signals are present in the sensitivity list. Please note that the result of the synthesis may differ from the initial design specification. The missing signals are: , Entity analyzed. Unit generated. Analyzing Entity in library (Architecture ). Entity analyzed. Unit generated. ========================================================================= * HDL Synthesis * ========================================================================= Performing bidirectional port resolution... Synthesizing Unit . Related source file is "C:/work/GlueX/Tagger/Electronics/FPGA/Config.vhd". Unit synthesized. Synthesizing Unit . Related source file is "C:/work/GlueX/Tagger/Electronics/FPGA/EthCtrl/Register/statereg.vhd". Found 3-bit register for signal . Found 3-bit register for signal . Summary: inferred 6 D-type flip-flop(s). Unit synthesized. Synthesizing Unit . Related source file is "C:/work/GlueX/Tagger/Electronics/FPGA/EthCtrl/Register/MACregs.vhd". Found 8-bit 12-to-1 multiplexer for signal . Found 96-bit register for signal . Summary: inferred 96 D-type flip-flop(s). inferred 8 Multiplexer(s). Unit synthesized. Synthesizing Unit . Related source file is "C:/work/GlueX/Tagger/Electronics/FPGA/EthCtrl/Register/TempReg.vhd". Found 10-bit register for signal . Summary: inferred 10 D-type flip-flop(s). Unit synthesized. Synthesizing Unit . Related source file is "C:/work/GlueX/Tagger/Electronics/FPGA/EthCtrl/Register/ADCregs.vhd". Found 12-bit 8-to-1 multiplexer for signal created at line 68. Found 96-bit register for signal . Summary: inferred 96 D-type flip-flop(s). inferred 12 Multiplexer(s). Unit synthesized. Synthesizing Unit . Related source file is "C:/work/GlueX/Tagger/Electronics/FPGA/MiscComp/delay.vhd". Found 1-bit register for signal . Found 1-bit register for signal . Summary: inferred 2 D-type flip-flop(s). Unit synthesized. Synthesizing Unit . Related source file is "C:/work/GlueX/Tagger/Electronics/FPGA/MiscComp/Pulser/Pulser.vhd". Found 1-bit register for signal . Found 1-bit register for signal . Summary: inferred 2 D-type flip-flop(s). Unit synthesized. Synthesizing Unit . Related source file is "C:/work/GlueX/Tagger/Electronics/FPGA/EthCtrl/MiscComp/getByte/getByte.vhd". WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. Found 1-bit tristate buffer for signal . Found 8-bit tristate buffer for signal . Found 8-bit tristate buffer for signal . Found 1-bit register for signal . Found 1-bit register for signal . Summary: inferred 2 D-type flip-flop(s). inferred 17 Tristate(s). Unit synthesized. Synthesizing Unit . Related source file is "C:/work/GlueX/Tagger/Electronics/FPGA/MiscComp/Reg8bit.vhd". Found 8-bit register for signal . Summary: inferred 8 D-type flip-flop(s). Unit synthesized. Synthesizing Unit . Related source file is "C:/work/GlueX/Tagger/Electronics/FPGA/MiscComp/EdgeCounter4bit.vhd". Found 3-bit register for signal >. Found 1-bit register for signal . Found 1-bit xor2 for signal created at line 62. Found 3-bit adder for signal created at line 44. Found 1-bit register for signal . Summary: inferred 5 D-type flip-flop(s). inferred 1 Adder/Subtractor(s). Unit synthesized. Synthesizing Unit . Related source file is "C:/work/GlueX/Tagger/Electronics/FPGA/MiscComp/Counter7bit.vhd". Found 7-bit up counter for signal . Found 1-bit register for signal . Summary: inferred 1 Counter(s). inferred 1 D-type flip-flop(s). Unit synthesized. Synthesizing Unit . Related source file is "C:/work/GlueX/Tagger/Electronics/FPGA/Includes.vhd". Found 1-bit register for signal . Summary: inferred 1 D-type flip-flop(s). Unit synthesized. Synthesizing Unit . Related source file is "C:/work/GlueX/Tagger/Electronics/FPGA/EthCtrl/MiscComp/wrToAddr/wrToAddr.vhd". Found 1-bit tristate buffer for signal . Found 8-bit tristate buffer for signal . Found 8-bit tristate buffer for signal . Found 1-bit register for signal . Found 1-bit register for signal . Summary: inferred 2 D-type flip-flop(s). inferred 17 Tristate(s). Unit synthesized. Synthesizing Unit . Related source file is "C:/work/GlueX/Tagger/Electronics/FPGA/MiscComp/Counter12bit.vhd". Found 12-bit up counter for signal . Summary: inferred 1 Counter(s). Unit synthesized. Synthesizing Unit . Related source file is "C:/work/GlueX/Tagger/Electronics/FPGA/MiscComp/StepCounter16bit.vhd". Found 16-bit up counter for signal . Found 1-bit register for signal . Summary: inferred 1 Counter(s). inferred 1 D-type flip-flop(s). Unit synthesized. Synthesizing Unit . Related source file is "C:/work/GlueX/Tagger/Electronics/FPGA/MiscComp/Counter4bit.vhd". Found 4-bit up counter for signal . Found 1-bit register for signal . Summary: inferred 1 Counter(s). inferred 1 D-type flip-flop(s). Unit synthesized. Synthesizing Unit . Related source file is "C:/work/GlueX/Tagger/Electronics/FPGA/EthCtrl/Transceiver/Transceiver_ctrl.vhd". WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. WARNING:Xst:737 - Found 1-bit latch for signal . Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems. Found 16x1-bit ROM for signal created at line 122. Found 8-bit tristate buffer for signal . Found 8-bit register for signal . Found 8-bit register for signal . Found 8-bit register for signal . Found 1-bit register for signal . Summary: inferred 1 ROM(s). inferred 25 D-type flip-flop(s). inferred 8 Tristate(s). Unit synthesized. Synthesizing Unit . Related source file is "C:/work/GlueX/Tagger/Electronics/FPGA/DAC_v2/DAC_controller.vhd". Found 1-bit register for signal . Found 1-bit register for signal . Found 5-bit down counter for signal . Found 19-bit register for signal . Summary: inferred 1 Counter(s). inferred 21 D-type flip-flop(s). Unit synthesized. Synthesizing Unit . Related source file is "C:/work/GlueX/Tagger/Electronics/FPGA/MiscComp/Reg32x14bit_wPrim.vhd". Unit synthesized. Synthesizing Unit . Related source file is "C:/work/GlueX/Tagger/Electronics/FPGA/MiscComp/delay.vhd". Unit synthesized. Synthesizing Unit . Related source file is "C:/work/GlueX/Tagger/Electronics/FPGA/SerialOut.vhd". WARNING:Xst:737 - Found 1-bit latch for signal . Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems. Found 5-bit up counter for signal . Found 1-bit register for signal . Found 4-bit down counter for signal . Summary: inferred 2 Counter(s). inferred 1 D-type flip-flop(s). Unit synthesized. Synthesizing Unit . Related source file is "C:/work/GlueX/Tagger/Electronics/FPGA/MiscComp/Reg256x8bit_wPrim.vhd". Unit synthesized. Synthesizing Unit . Related source file is "C:/work/GlueX/Tagger/Electronics/FPGA/EthCtrl/MiscComp/MACwrToAddr.vhd". WARNING:Xst:1305 - Output is never assigned. Tied to value 0. Unit synthesized. Synthesizing Unit . Related source file is "C:/work/GlueX/Tagger/Electronics/FPGA/EthCtrl/MiscComp/wr2BToAddr/wr2BToAddr_good.vhd". WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. Found 8-bit register for signal . Found 8-bit adder for signal created at line 90. Found 8-bit register for signal . Summary: inferred 16 D-type flip-flop(s). inferred 1 Adder/Subtractor(s). Unit synthesized. Synthesizing Unit . Related source file is "C:/work/GlueX/Tagger/Electronics/FPGA/Includes.vhd". Unit synthesized. Synthesizing Unit . Related source file is "C:/work/GlueX/Tagger/Electronics/FPGA/EthCtrl/MiscComp/AutoRd.vhd". Unit synthesized. Synthesizing Unit . Related source file is "C:/work/GlueX/Tagger/Electronics/FPGA/EthCtrl/Transmitter/wrMACaddrs.vhd". WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. Found 8-bit tristate buffer for signal . Found 1-bit tristate buffer for signal . Found 4-bit tristate buffer for signal . Found 4-bit up counter for signal . Found 1-bit register for signal . Summary: inferred 1 Counter(s). inferred 1 D-type flip-flop(s). inferred 13 Tristate(s). Unit synthesized. Synthesizing Unit . Related source file is "C:/work/GlueX/Tagger/Electronics/FPGA/EthCtrl/MiscComp/RAwr2BtoAddr.vhd". Found 8-bit tristate buffer for signal . Found 16-bit tristate buffer for signal . Found 2-bit up counter for signal . Found 1-bit xor2 for signal created at line 65. Summary: inferred 1 Counter(s). inferred 24 Tristate(s). Unit synthesized. Synthesizing Unit . Related source file is "C:/work/GlueX/Tagger/Electronics/FPGA/EthCtrl/Querier/GetTempVal.vhd". WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. Found 1-bit tristate buffer for signal . Found 8-bit tristate buffer for signal . Found 4-bit up counter for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 10-bit register for signal . Summary: inferred 1 Counter(s). inferred 12 D-type flip-flop(s). inferred 9 Tristate(s). Unit synthesized. Synthesizing Unit . Related source file is "C:/work/GlueX/Tagger/Electronics/FPGA/EthCtrl/Querier/GetADCval.vhd". WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. Found 1-bit tristate buffer for signal . Found 8-bit tristate buffer for signal . Found 3-bit register for signal . Found 5-bit up counter for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 12-bit register for signal . Summary: inferred 1 Counter(s). inferred 18 D-type flip-flop(s). inferred 9 Tristate(s). Unit synthesized. Synthesizing Unit . Related source file is "C:/work/GlueX/Tagger/Electronics/FPGA/EthCtrl/MiscComp/INTCatcher/INTCatcher.vhd". WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value 0. WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value 0. WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. WARNING:Xst:646 - Signal > is assigned but never used. This unconnected signal will be trimmed during the optimization process. WARNING:Xst:646 - Signal > is assigned but never used. This unconnected signal will be trimmed during the optimization process. WARNING:Xst:646 - Signal > is assigned but never used. This unconnected signal will be trimmed during the optimization process. WARNING:Xst:646 - Signal > is assigned but never used. This unconnected signal will be trimmed during the optimization process. WARNING:Xst:646 - Signal > is assigned but never used. This unconnected signal will be trimmed during the optimization process. Found 8-bit tristate buffer for signal . Found 1-bit register for signal . Summary: inferred 1 D-type flip-flop(s). inferred 8 Tristate(s). Unit synthesized. Synthesizing Unit . Related source file is "C:/work/GlueX/Tagger/Electronics/FPGA/EthCtrl/Reset/Reset_soft.vhd". WARNING:Xst:1305 - Output is never assigned. Tied to value 00000000. WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. Found 3-bit tristate buffer for signal . Found 4-bit tristate buffer for signal . Found 8-bit tristate buffer for signal . Found 8-bit tristate buffer for signal . Found 4-bit up counter for signal . Summary: inferred 1 Counter(s). inferred 23 Tristate(s). Unit synthesized. Synthesizing Unit . Related source file is "C:/work/GlueX/Tagger/Electronics/FPGA/EthCtrl/Idler/Idler_ctrl.vhd". WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. Found 8-bit tristate buffer for signal . Found 3-bit tristate buffer for signal . Summary: inferred 11 Tristate(s). Unit synthesized. Synthesizing Unit . Related source file is "C:/work/GlueX/Tagger/Electronics/FPGA/EthCtrl/Querier/Query_coord.vhd". WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. Found 3-bit tristate buffer for signal . Found 3-bit tristate buffer for signal . Found 8-bit tristate buffer for signal . Found 4-bit down counter for signal . Found 8-bit up counter for signal . Summary: inferred 2 Counter(s). inferred 14 Tristate(s). Unit synthesized. Synthesizing Unit . Related source file is "C:/work/GlueX/Tagger/Electronics/FPGA/EthCtrl/Reader/Reader_ctrl.vhd". WARNING:Xst:1305 - Output is never assigned. Tied to value 0. Found 3-bit tristate buffer for signal . Found 8-bit tristate buffer for signal . Found 4-bit up counter for signal . Found 1-bit register for signal . Found 3-bit register for signal . Found 8-bit comparator equal for signal created at line 108. Found 1-bit register for signal . Summary: inferred 1 Counter(s). inferred 5 D-type flip-flop(s). inferred 1 Comparator(s). inferred 11 Tristate(s). Unit synthesized. Synthesizing Unit . Related source file is "C:/work/GlueX/Tagger/Electronics/FPGA/EthCtrl/Programmer/Programmer_ctrl.vhd". WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. WARNING:Xst:1305 - Output is never assigned. Tied to value 0. WARNING:Xst:1305 - Output is never assigned. Tied to value 0. WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. WARNING:Xst:646 - Signal > is assigned but never used. This unconnected signal will be trimmed during the optimization process. WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. Found 3-bit tristate buffer for signal . Found 5-bit tristate buffer for signal . Found 1-bit 32-to-1 multiplexer for signal <$varindex0000> created at line 161. Found 14-bit comparator less for signal created at line 172. Found 6-bit up counter for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 14-bit comparator less for signal created at line 178. Found 8-bit comparator less for signal created at line 88. Found 32-bit register for signal . Found 2-bit up counter for signal . Found 1-bit register for signal . Summary: inferred 2 Counter(s). inferred 35 D-type flip-flop(s). inferred 3 Comparator(s). inferred 1 Multiplexer(s). inferred 8 Tristate(s). Unit synthesized. Synthesizing Unit . Related source file is "C:/work/GlueX/Tagger/Electronics/FPGA/MiscComp/Reg32x14bit_wPrim.vhd". WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. Unit synthesized. Synthesizing Unit . Related source file is "C:/work/GlueX/Tagger/Electronics/FPGA/MiscComp/Reg64x8bit_wPrim.vhd". WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. Found 8-bit 4-to-1 multiplexer for signal . Summary: inferred 8 Multiplexer(s). Unit synthesized. Synthesizing Unit . Related source file is "C:/work/GlueX/Tagger/Electronics/FPGA/EthCtrl/Reset/MACaddrLoad.vhd". WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. Found 4-bit tristate buffer for signal . Found 8-bit tristate buffer for signal . Found 1-bit register for signal . Found 1-bit xor2 for signal . Found 2-bit up counter for signal . Found 3-bit register for signal >. Found 3-bit adder for signal created at line 155. Summary: inferred 1 Counter(s). inferred 4 D-type flip-flop(s). inferred 1 Adder/Subtractor(s). inferred 12 Tristate(s). Unit synthesized. Synthesizing Unit . Related source file is "C:/work/GlueX/Tagger/Electronics/FPGA/EthCtrl/Transmitter/D-Packet.vhd". WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. Found 5-bit tristate buffer for signal . Found 5-bit up counter for signal . Found 16-bit tristate buffer for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Summary: inferred 1 Counter(s). inferred 3 D-type flip-flop(s). inferred 21 Tristate(s). Unit synthesized. Synthesizing Unit . Related source file is "C:/work/GlueX/Tagger/Electronics/FPGA/EthCtrl/Transmitter/S-Packet.vhd". WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. Found 3-bit tristate buffer for signal . Found 8-bit tristate buffer for signal . Found 6-bit down counter for signal . Found 1-bit register for signal . Summary: inferred 1 Counter(s). inferred 1 D-type flip-flop(s). inferred 11 Tristate(s). Unit synthesized. Synthesizing Unit . Related source file is "C:/work/GlueX/Tagger/Electronics/FPGA/EthCtrl/Register/DACregs.vhd". Unit synthesized. Synthesizing Unit . Related source file is "C:/work/GlueX/Tagger/Electronics/FPGA/SerialOut.vhd". Found 6-bit up counter for signal . Found 6-bit up counter for signal . Found 6-bit register for signal . Found 6-bit addsub for signal . Summary: inferred 2 Counter(s). inferred 6 D-type flip-flop(s). inferred 1 Adder/Subtractor(s). Unit synthesized. Synthesizing Unit . Related source file is "C:/work/GlueX/Tagger/Electronics/FPGA/EthCtrl/Reset/Reset_hard.vhd". WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. WARNING:Xst:1305 - Output is never assigned. Tied to value 0. WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value 0. WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value 0. WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value 0. WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value 0. WARNING:Xst:646 - Signal > is assigned but never used. This unconnected signal will be trimmed during the optimization process. WARNING:Xst:646 - Signal > is assigned but never used. This unconnected signal will be trimmed during the optimization process. WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. WARNING:Xst:737 - Found 1-bit latch for signal . Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems. Found 1-bit tristate buffer for signal . Found 8-bit tristate buffer for signal . Found 3-bit tristate buffer for signal . Found 4-bit tristate buffer for signal . Found 8-bit tristate buffer for signal . Found 2-bit up counter for signal . Summary: inferred 1 Counter(s). inferred 32 Tristate(s). Unit synthesized. Synthesizing Unit . Related source file is "C:/work/GlueX/Tagger/Electronics/FPGA/EthCtrl/Transmitter/Transmitter_ctrl.vhd". WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. WARNING:Xst:1305 - Output is never assigned. Tied to value 0. WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value 0. WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value 0. WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value 0. WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value 0. WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value 0. WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value 0. WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value 0. WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value 0. WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. Found 8-bit tristate buffer for signal . Found 3-bit tristate buffer for signal . Found 3-bit tristate buffer for signal . Found 8-bit tristate buffer for signal . Found 16-bit up counter for signal . Summary: inferred 1 Counter(s). inferred 22 Tristate(s). Unit synthesized. Synthesizing Unit . Related source file is "C:/work/GlueX/Tagger/Electronics/FPGA/FPGA_ctrl.vhd". WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value 0. WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value 0. WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. Found 2-bit up counter for signal . Found 8-bit tristate buffer for signal . Found 1-bit tristate buffer for signal . Summary: inferred 1 Counter(s). inferred 9 Tristate(s). Unit synthesized. INFO:Xst:1767 - HDL ADVISOR - Resource sharing has identified that some arithmetic operations in this design can share the same physical resources for reduced device utilization. For improved clock frequency you may try to disable resource sharing. ========================================================================= HDL Synthesis Report Macro Statistics # ROMs : 1 16x1-bit ROM : 1 # Adders/Subtractors : 9 3-bit adder : 2 6-bit addsub : 1 8-bit adder : 6 # Counters : 28 12-bit up counter : 2 16-bit up counter : 2 2-bit up counter : 6 4-bit down counter : 2 4-bit up counter : 7 5-bit down counter : 1 5-bit up counter : 3 6-bit down counter : 1 6-bit up counter : 3 7-bit up counter : 1 # Registers : 330 1-bit register : 275 10-bit register : 1 12-bit register : 8 19-bit register : 1 3-bit register : 3 6-bit register : 1 8-bit register : 41 # Latches : 3 1-bit latch : 3 # Comparators : 4 14-bit comparator less : 2 8-bit comparator equal : 1 8-bit comparator less : 1 # Multiplexers : 4 1-bit 32-to-1 multiplexer : 1 12-bit 8-to-1 multiplexer : 1 8-bit 12-to-1 multiplexer : 1 8-bit 4-to-1 multiplexer : 1 # Tristates : 272 1-bit tristate buffer : 115 16-bit tristate buffer : 3 3-bit tristate buffer : 10 4-bit tristate buffer : 4 5-bit tristate buffer : 2 8-bit tristate buffer : 138 # Xors : 4 1-bit xor2 : 4 ========================================================================= ========================================================================= * Advanced HDL Synthesis * ========================================================================= WARNING:Xst:1290 - Hierarchical block is unconnected in block . It will be removed from the design. WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:2677 - Node of sequential type is unconnected in block . WARNING:Xst:2677 - Node of sequential type is unconnected in block . WARNING:Xst:2677 - Node of sequential type is unconnected in block . WARNING:Xst:2677 - Node of sequential type is unconnected in block . WARNING:Xst:2677 - Node of sequential type is unconnected in block . WARNING:Xst:2677 - Node of sequential type is unconnected in block . WARNING:Xst:2677 - Node of sequential type is unconnected in block . WARNING:Xst:2677 - Node of sequential type is unconnected in block . WARNING:Xst:2677 - Node of sequential type is unconnected in block . WARNING:Xst:2677 - Node of sequential type is unconnected in block . WARNING:Xst:2677 - Node of sequential type is unconnected in block . WARNING:Xst:2677 - Node of sequential type is unconnected in block . WARNING:Xst:2677 - Node of sequential type is unconnected in block . WARNING:Xst:2677 - Node of sequential type is unconnected in block . WARNING:Xst:2677 - Node of sequential type is unconnected in block . WARNING:Xst:2677 - Node of sequential type is unconnected in block . WARNING:Xst:2677 - Node of sequential type is unconnected in block . WARNING:Xst:2677 - Node of sequential type is unconnected in block . ========================================================================= Advanced HDL Synthesis Report Macro Statistics # ROMs : 1 16x1-bit ROM : 1 # Adders/Subtractors : 9 3-bit adder : 2 6-bit addsub : 1 8-bit adder : 6 # Counters : 28 12-bit up counter : 2 16-bit up counter : 2 2-bit up counter : 6 4-bit down counter : 2 4-bit up counter : 7 5-bit down counter : 1 5-bit up counter : 3 6-bit down counter : 1 6-bit up counter : 3 7-bit up counter : 1 # Registers : 743 Flip-Flops : 743 # Latches : 3 1-bit latch : 3 # Comparators : 4 14-bit comparator less : 2 8-bit comparator equal : 1 8-bit comparator less : 1 # Multiplexers : 4 1-bit 32-to-1 multiplexer : 1 12-bit 8-to-1 multiplexer : 1 8-bit 12-to-1 multiplexer : 1 8-bit 4-to-1 multiplexer : 1 # Xors : 4 1-bit xor2 : 4 ========================================================================= ========================================================================= * Low Level Synthesis * ========================================================================= WARNING:Xst:2677 - Node of sequential type is unconnected in block . WARNING:Xst:2040 - Unit FPGA_ctrl: 23 multi-source signals are replaced by logic (pull-up yes): INT_Mask<0>, INT_Mask<1>, INT_Mask<2>, INT_Mask<3>, INT_Mask<4>, INT_Mask<5>, INT_Mask<6>, INT_Mask<7>, MACregs_A<0>, MACregs_A<1>, MACregs_A<2>, MACregs_A<3>, ser_D<0>, ser_D<1>, ser_D<2>, ser_D<3>, ser_D<4>, ser_D<5>, ser_D<6>, ser_D<7>, state_D<0>, state_D<1>, state_D<2>. WARNING:Xst:2042 - Unit INTCatcher: 8 internal tristates are replaced by logic (pull-up yes): ser_D<0>, ser_D<1>, ser_D<2>, ser_D<3>, ser_D<4>, ser_D<5>, ser_D<6>, ser_D<7>. WARNING:Xst:2042 - Unit Reset_soft: 23 internal tristates are replaced by logic (pull-up yes): MACregs_A<0>, MACregs_A<1>, MACregs_A<2>, MACregs_A<3>, MACregs_D<0>, MACregs_D<1>, MACregs_D<2>, MACregs_D<3>, MACregs_D<4>, MACregs_D<5>, MACregs_D<6>, MACregs_D<7>, ser_D<0>, ser_D<1>, ser_D<2>, ser_D<3>, ser_D<4>, ser_D<5>, ser_D<6>, ser_D<7>, state_D<0>, state_D<1>, state_D<2>. WARNING:Xst:2042 - Unit Transmitter: 11 internal tristates are replaced by logic (pull-up yes): INT_Mask<0>, INT_Mask<1>, INT_Mask<2>, INT_Mask<3>, INT_Mask<4>, INT_Mask<5>, INT_Mask<6>, INT_Mask<7>, state_D<0>, state_D<1>, state_D<2>. WARNING:Xst:2040 - Unit Transmitter: 3 multi-source signals are replaced by logic (pull-up yes): ADCReg_Addr<0>, ADCReg_Addr<1>, ADCReg_Addr<2>. WARNING:Xst:2042 - Unit MACaddrLoad: 12 internal tristates are replaced by logic (pull-up yes): MACregs_A<0>, MACregs_A<1>, MACregs_A<2>, MACregs_A<3>, MACregs_D<0>, MACregs_D<1>, MACregs_D<2>, MACregs_D<3>, MACregs_D<4>, MACregs_D<5>, MACregs_D<6>, MACregs_D<7>. WARNING:Xst:2042 - Unit Programmer_ctrl: 8 internal tristates are replaced by logic (pull-up yes): DAC_Addr<0>, DAC_Addr<1>, DAC_Addr<2>, DAC_Addr<3>, DAC_Addr<4>, state_D<0>, state_D<1>, state_D<2>. WARNING:Xst:2042 - Unit Reader: 11 internal tristates are replaced by logic (pull-up yes): ser_D<0>, ser_D<1>, ser_D<2>, ser_D<3>, ser_D<4>, ser_D<5>, ser_D<6>, ser_D<7>, state_D<0>, state_D<1>, state_D<2>. WARNING:Xst:2042 - Unit Querier: 6 internal tristates are replaced by logic (pull-up yes): ADCreg_A<0>, ADCreg_A<1>, ADCreg_A<2>, stateD<0>, stateD<1>, stateD<2>. WARNING:Xst:2040 - Unit Querier: 8 multi-source signals are replaced by logic (pull-up yes): ser_D<0>, ser_D<1>, ser_D<2>, ser_D<3>, ser_D<4>, ser_D<5>, ser_D<6>, ser_D<7>. WARNING:Xst:2042 - Unit Idler_ctrl: 11 internal tristates are replaced by logic (pull-up yes): INT_Mask<0>, INT_Mask<1>, INT_Mask<2>, INT_Mask<3>, INT_Mask<4>, INT_Mask<5>, INT_Mask<6>, INT_Mask<7>, state_D<0>, state_D<1>, state_D<2>. WARNING:Xst:2042 - Unit GetTempVal: 9 internal tristates are replaced by logic (pull-up yes): ser_D<0>, ser_D<1>, ser_D<2>, ser_D<3>, ser_D<4>, ser_D<5>, ser_D<6>, ser_D<7>, ser_Go. WARNING:Xst:2042 - Unit WrMACaddrs: 13 internal tristates are replaced by logic (pull-up yes): MACregs_A<0>, MACregs_A<1>, MACregs_A<2>, MACregs_A<3>, RAwrAinc, RAwrD<0>, RAwrD<1>, RAwrD<2>, RAwrD<3>, RAwrD<4>, RAwrD<5>, RAwrD<6>, RAwrD<7>. WARNING:Xst:2042 - Unit GetADCval: 8 internal tristates are replaced by logic (pull-up yes): ser_D<0>, ser_D<1>, ser_D<2>, ser_D<3>, ser_D<4>, ser_D<5>, ser_D<6>, ser_D<7>. WARNING:Xst:2183 - Unit GetADCval: the following tristate(s) are NOT replaced by logic (Please refer to Answer Record 20048 for more information): ser_Go. WARNING:Xst:2042 - Unit getByte: 17 internal tristates are replaced by logic (pull-up yes): Q<0>, Q<1>, Q<2>, Q<3>, Q<4>, Q<5>, Q<6>, Q<7>, TxRx_A<0>, TxRx_A<1>, TxRx_A<2>, TxRx_A<3>, TxRx_A<4>, TxRx_A<5>, TxRx_A<6>, TxRx_A<7>, TxRx_RiW. WARNING:Xst:2042 - Unit DPacket: 21 internal tristates are replaced by logic (pull-up yes): DACReg_Addr<0>, DACReg_Addr<1>, DACReg_Addr<2>, DACReg_Addr<3>, DACReg_Addr<4>, Data<0>, Data<10>, Data<11>, Data<12>, Data<13>, Data<14>, Data<15>, Data<1>, Data<2>, Data<3>, Data<4>, Data<5>, Data<6>, Data<7>, Data<8>, Data<9>. WARNING:Xst:2042 - Unit SPacket: 11 internal tristates are replaced by logic (pull-up yes): ADCReg_Addr<0>, ADCReg_Addr<1>, ADCReg_Addr<2>, ser_D<0>, ser_D<1>, ser_D<2>, ser_D<3>, ser_D<4>, ser_D<5>, ser_D<6>, ser_D<7>. WARNING:Xst:2042 - Unit RAwr2BtoAddr: 24 internal tristates are replaced by logic (pull-up yes): RAwrAddr<0>, RAwrAddr<10>, RAwrAddr<11>, RAwrAddr<12>, RAwrAddr<13>, RAwrAddr<14>, RAwrAddr<15>, RAwrAddr<1>, RAwrAddr<2>, RAwrAddr<3>, RAwrAddr<4>, RAwrAddr<5>, RAwrAddr<6>, RAwrAddr<7>, RAwrAddr<8>, RAwrAddr<9>, RAwrD<0>, RAwrD<1>, RAwrD<2>, RAwrD<3>, RAwrD<4>, RAwrD<5>, RAwrD<6>, RAwrD<7>. WARNING:Xst:2042 - Unit wrToAddr: 17 internal tristates are replaced by logic (pull-up yes): TxRx_A<0>, TxRx_A<1>, TxRx_A<2>, TxRx_A<3>, TxRx_A<4>, TxRx_A<5>, TxRx_A<6>, TxRx_A<7>, TxRx_D<0>, TxRx_D<1>, TxRx_D<2>, TxRx_D<3>, TxRx_D<4>, TxRx_D<5>, TxRx_D<6>, TxRx_D<7>, TxRx_RiW. WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:2677 - Node of sequential type is unconnected in block . WARNING:Xst:2677 - Node of sequential type is unconnected in block . WARNING:Xst:2677 - Node of sequential type is unconnected in block . WARNING:Xst:2677 - Node of sequential type is unconnected in block . WARNING:Xst:2677 - Node of sequential type is unconnected in block . WARNING:Xst:2677 - Node of sequential type is unconnected in block . WARNING:Xst:2677 - Node of sequential type is unconnected in block . WARNING:Xst:2677 - Node of sequential type is unconnected in block . WARNING:Xst:2677 - Node of sequential type is unconnected in block . WARNING:Xst:2677 - Node of sequential type is unconnected in block . WARNING:Xst:2677 - Node of sequential type is unconnected in block . WARNING:Xst:2677 - Node of sequential type is unconnected in block . WARNING:Xst:2677 - Node of sequential type is unconnected in block . WARNING:Xst:2677 - Node of sequential type is unconnected in block . WARNING:Xst:2677 - Node of sequential type is unconnected in block . WARNING:Xst:2677 - Node of sequential type is unconnected in block . WARNING:Xst:2677 - Node of sequential type is unconnected in block . WARNING:Xst:2677 - Node of sequential type is unconnected in block . WARNING:Xst:2677 - Node of sequential type is unconnected in block . Optimizing unit ... Optimizing unit ... Optimizing unit ... Optimizing unit ... Optimizing unit ... Optimizing unit ... Optimizing unit ... Optimizing unit ... Optimizing unit ... Optimizing unit ... Optimizing unit ... Optimizing unit ... Optimizing unit ... WARNING:Xst:2677 - Node of sequential type is unconnected in block . WARNING:Xst:2677 - Node of sequential type is unconnected in block . WARNING:Xst:2677 - Node of sequential type is unconnected in block . WARNING:Xst:2677 - Node of sequential type is unconnected in block . WARNING:Xst:2677 - Node of sequential type is unconnected in block . WARNING:Xst:2677 - Node of sequential type is unconnected in block . WARNING:Xst:2677 - Node of sequential type is unconnected in block . WARNING:Xst:2677 - Node of sequential type is unconnected in block . WARNING:Xst:2677 - Node of sequential type is unconnected in block . WARNING:Xst:2677 - Node of sequential type is unconnected in block . WARNING:Xst:2677 - Node of sequential type is unconnected in block . WARNING:Xst:2677 - Node of sequential type is unconnected in block . WARNING:Xst:2677 - Node of sequential type is unconnected in block . WARNING:Xst:2677 - Node of sequential type is unconnected in block . WARNING:Xst:2677 - Node of sequential type is unconnected in block . WARNING:Xst:2677 - Node of sequential type is unconnected in block . WARNING:Xst:2677 - Node of sequential type is unconnected in block . WARNING:Xst:2677 - Node of sequential type is unconnected in block . Mapping all equations... Building and optimizing final netlist ... Found area constraint ratio of 100 (+ 5) on block FPGA_ctrl, actual ratio is 109. Optimizing block to meet ratio 100 (+ 5) of 704 slices : WARNING:Xst:2254 - Area constraint could not be met for block , final ratio is 108. Final Macro Processing ... ========================================================================= Final Register Report Macro Statistics # Registers : 773 Flip-Flops : 773 ========================================================================= ========================================================================= * Partition Report * ========================================================================= Partition Implementation Status ------------------------------- No Partitions were found in this design. ------------------------------- ========================================================================= * Final Report * ========================================================================= WARNING:Xst:1336 - (*) More than 100% of Device resources are used Clock Information: ------------------ -------------------------------------------------------------+-------------------------------+-------+ Clock Signal | Clock buffer(FF name) | Load | -------------------------------------------------------------+-------------------------------+-------+ fClk | u1/DCM_SP_inst:CLKDV | 760 | fClk | IBUFG+BUFG | 34 | Rst_int(Rst_int_or00001:O) | NONE(*)(u1/RWflag) | 1 | uINT/u4/u2/Q | NONE(uResH/g3/waiting) | 4 | ser_Go_uINT(uINT/u3/Done_int1:O) | NONE(*)(uINT/En) | 1 | uResS/Done_Byte(uResS/uAutoRd/u1/Done_int1:O) | NONE(*)(uResS/ReadCount_3) | 4 | uQuer/u3/u1/Q | NONE(uQuer/ChanCnt_2) | 4 | uXmit/uSpack/Done_Word(uXmit/uSpack/Go_TxEnd11:O) | NONE(*)(uXmit/uSpack/En) | 7 | uXmit/uDpack/w/C_0_0_not0000(uXmit/uDpack/w/C_0_0_not00001:O)| NONE(*)(uXmit/uSpack/w/C_0) | 4 | uXmit/uDpack/u1/Q | NONE(uXmit/uDpack/preDACstage)| 6 | uXmit/uDpack/Done_Word(uXmit/uDpack/PermitNextWord11:O) | NONE(*)(uXmit/uDpack/DataEn) | 1 | uXmit/uTxMAC/u1/Q | NONE(uXmit/uTxMAC/ByteCount_0)| 4 | db0/u2/Q | NONE(db0/u0/Q) | 1 | db0/u0/serClk | NONE(db0/u0/SerCnt_0) | 4 | -------------------------------------------------------------+-------------------------------+-------+ (*) These 6 clock signal(s) are generated by combinatorial logic, and XST is not able to identify which are the primary clock signals. Please use the CLOCK_SIGNAL constraint to specify the clock signal(s) generated by combinatorial logic. INFO:Xst:2169 - HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems. Asynchronous Control Signals Information: ---------------------------------------- ---------------------------------------------------------------+-------------------------------+-------+ Control Signal | Buffer(FF name) | Load | ---------------------------------------------------------------+-------------------------------+-------+ Rst_int(Rst_int_or00001:O) | NONE(r1/state_0) | 354 | MACregsRst(MACregsRst1:O) | NONE(r2/reg_0_0) | 96 | Rst | IBUF | 49 | uProg/MaskByte_0_or0000(uProg/MaskByte_0_or00001:O) | NONE(uProg/Cnt_0) | 43 | uXmit/RAwrAddr_reg_or0000(uXmit/RAwrAddr_reg_or00001:O) | NONE(uXmit/RAwrAddr_reg_0) | 16 | Rst_Quer(Rst_Quer1:O) | NONE(uQuer/u2/cnt_0) | 14 | uXmit/Go_TxD(uXmit/Go_TxD1:O) | NONE(uXmit/uDpack/ChanCount_0)| 8 | uXmit/Go_TxS(uXmit/Go_TxS1:O) | NONE(uXmit/uSpack/ChanCount_0)| 7 | uRd/count_or0000(uRd/count_or00001:O) | NONE(uRd/Discard) | 6 | uResH/Done_IPGR(uResH/m4/m3/Done1:O) | NONE(uResH/m6/En) | 6 | uQuer/ChanCnt_or0000(uQuer/ChanCnt_or00001:O) | NONE(uQuer/ChanCnt_0) | 4 | uResS/ReadCount_or0000(uResS/ReadCount_or00001:O) | NONE(uResS/ReadCount_0) | 4 | uXmit/uTxMAC/ByteCount_or0000(uXmit/uTxMAC/ByteCount_or00001:O)| NONE(uXmit/uTxMAC/ByteCount_0)| 4 | db0/u0/SerCnt_cst(db0/u0/SerCnt_cst1:O) | NONE(db0/u0/SerCnt_0) | 3 | iCS_OBUF(XST_GND:G) | NONE(uXmit/uDpack/w/C_1) | 2 | INT_Go(INT_Go20:O) | NONE(uINT/En) | 1 | INT_Go11(uResH/p7/Done1:O) | NONE(uResH/p6/waiting) | 1 | INT_Go_Idl(uIdl/Go1:O) | NONE(uIdl/g4/waiting) | 1 | db0/u0/Mcount_SerCnt_val(db0/u0/Mcount_SerCnt_val1:O) | NONE(db0/u0/SerCnt_2) | 1 | uQuer/u3/ReadTime_or0000(uQuer/u3/ReadTime_or00001:O) | NONE(uQuer/u3/ReadTime) | 1 | uResH/Done_EthiRST(uResH/g2/Done1:O) | NONE(uResH/g3/waiting) | 1 | uResH/Go_SelfInitINT(uResH/g3/Trig1:O) | NONE(uResH/g4/waiting) | 1 | uXmit/uDpack/w/C_0__and0000(uXmit/uDpack/w/C_0__and00001:O) | NONE(uXmit/uDpack/w/C_0) | 1 | uXmit/uDpack/w/C_0__and0001(uXmit/uDpack/w/C_0__and00011:O) | NONE(uXmit/uDpack/w/C_0) | 1 | uXmit/uDpack/w/C_1__and0000(uXmit/uDpack/w/C_1__and00001:O) | NONE(uXmit/uDpack/w/C_1) | 1 | uXmit/uSpack/Go_Wr(uXmit/uSpack/Go_Wr:O) | NONE(uXmit/uSpack/w/C_0) | 1 | uXmit/uSpack/w/C_0__and0000(uXmit/uSpack/w/C_0__and00001:O) | NONE(uXmit/uSpack/w/C_0) | 1 | uXmit/uSpack/w/C_1__and0000(uXmit/uSpack/w/C_1__and00001:O) | NONE(uXmit/uSpack/w/C_1) | 1 | uXmit/uTxSt1/u1/Q(uXmit/uTxSt1/u1/Q:Q) | NONE(uXmit/uTxMAC/En) | 1 | ---------------------------------------------------------------+-------------------------------+-------+ Timing Summary: --------------- Speed Grade: -4 Minimum period: 20.352ns (Maximum Frequency: 49.134MHz) Minimum input arrival time before clock: 8.937ns Maximum output required time after clock: 10.755ns Maximum combinational path delay: 11.200ns ========================================================================= Process "Synthesis" completed successfully Command Line: E:\Xilinx\11.1\ISE\bin\nt\unwrapped\ngdbuild.exe -ise TotalTest.ise -intstyle ise -dd _ngo -nt timestamp -i -p xc3s50a-vq100-4 FPGA_ctrl.ngc FPGA_ctrl.ngd Reading NGO file "C:/work/GlueX/Tagger/Electronics/FPGA/TotalTest/FPGA_ctrl.ngc" ... Reading in constraint information from 'FPGA_ctrl.ucf'... Gathering constraint information from source properties... Done. Resolving constraint associations... Checking Constraint Associations... Done... Checking Partitions ... Checking expanded design ... Partition Implementation Status ------------------------------- No Partitions were found in this design. ------------------------------- NGDBUILD Design Results Summary: Number of errors: 0 Number of warnings: 0 Writing NGD file "FPGA_ctrl.ngd" ... Total REAL time to NGDBUILD completion: 4 sec Total CPU time to NGDBUILD completion: 3 sec Writing NGDBUILD log file "FPGA_ctrl.bld"... NGDBUILD done. Process "Translate" completed successfully Using target part "3s50avq100-4". WARNING:Map:246 - The MAP option "No logic replication" (-l) is being deprecated in the next major software release. Loading device for application Rf_Device from file '3s50a.nph' in environment E:\Xilinx\11.1\ISE. "FPGA_ctrl" is an NCD, version 3.2, device xc3s50a, package vq100, speed -4 WARNING:Map:267 - There will be a smaller percentage of guiding when using SmartGuide with the some of the physical synthesis options. These options include: "Combinatorial Logic Optimization"(-logic_opt),"Global Optimization"(-global_opt), and "Register Duplication"(-register_duplication). The command line used to create the guide file is: -ise TotalTest.ise -intstyle ise -p xc3s50a-vq100-4 -timing -logic_opt on -ol std -t 1 -register_duplication off -cm speed -detail -ir all -ignore_keep_hierarchy -pr b -l -ntd -bp -smartguide FPGA_ctrl_guide.ncd -power off -o FPGA_ctrl_map.ncd FPGA_ctrl.ngd FPGA_ctrl.pcf The command line used for this run is: -ise TotalTest.ise -intstyle ise -p xc3s50a-vq100-4 -timing -logic_opt on -ol std -t 1 -register_duplication off -cm speed -detail -ir all -ignore_keep_hierarchy -pr b -l -ntd -bp -smartguide FPGA_ctrl_guide.ncd -power off -o FPGA_ctrl_map.ncd FPGA_ctrl.ngd FPGA_ctrl.pcf If one or more of the above physical synthesis options is being used, SmartGuide will have a lower guide percentage, possibly longer runtimes and possibly worse timing scores. If the physical synthesis option is required to meet timing, it is suggested that SmartGuide is not used. If the physical synthesis option is not required, it is suggested to re-create the guide without the physical synthesis option and re-run SmartGuide vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv INFO:Security:54 - 'xc3s50a' is a WebPack part. WARNING:Security:42 - Your software subscription period has lapsed. Your current version of Xilinx tools will continue to function, but you no longer qualify for Xilinx software updates or new releases. ---------------------------------------------------------------------- WARNING:LIT:243 - Logical network STARTUP_SPARTAN3A_inst/GSR_INT has no load. WARNING:LIT:243 - Logical network STARTUP_SPARTAN3A_inst/GTS_INT has no load. WARNING:LIT:243 - Logical network r6/u1/r0/reg1bit_0/SPO has no load. WARNING:LIT:243 - Logical network r6/u1/r0/reg1bit_1/SPO has no load. WARNING:LIT:243 - Logical network r6/u1/r0/reg1bit_2/SPO has no load. WARNING:LIT:243 - Logical network r6/u1/r0/reg1bit_3/SPO has no load. WARNING:LIT:243 - Logical network r6/u1/r0/reg1bit_4/SPO has no load. WARNING:LIT:243 - Logical network r6/u1/r0/reg1bit_5/SPO has no load. WARNING:LIT:243 - Logical network r6/u1/r0/reg1bit_6/SPO has no load. WARNING:LIT:243 - Logical network r6/u1/r0/reg1bit_7/SPO has no load. WARNING:LIT:243 - Logical network r6/u1/r0/reg1bit_8/SPO has no load. WARNING:LIT:243 - Logical network r6/u1/r0/reg1bit_9/SPO has no load. WARNING:LIT:243 - Logical network r6/u1/r0/reg1bit_10/SPO has no load. WARNING:LIT:243 - Logical network r6/u1/r0/reg1bit_11/SPO has no load. WARNING:LIT:243 - Logical network r6/u1/r0/reg1bit_12/SPO has no load. WARNING:LIT:243 - Logical network r6/u1/r0/reg1bit_13/SPO has no load. WARNING:LIT:243 - Logical network r6/u1/r1/reg1bit_0/SPO has no load. WARNING:LIT:243 - Logical network r6/u1/r1/reg1bit_1/SPO has no load. WARNING:LIT:243 - Logical network r6/u1/r1/reg1bit_2/SPO has no load. WARNING:LIT:243 - Logical network r6/u1/r1/reg1bit_3/SPO has no load. WARNING:LIT:243 - Logical network r6/u1/r1/reg1bit_4/SPO has no load. WARNING:LIT:243 - Logical network r6/u1/r1/reg1bit_5/SPO has no load. WARNING:LIT:243 - Logical network r6/u1/r1/reg1bit_6/SPO has no load. WARNING:LIT:243 - Logical network r6/u1/r1/reg1bit_7/SPO has no load. WARNING:LIT:243 - Logical network r6/u1/r1/reg1bit_8/SPO has no load. WARNING:LIT:243 - Logical network r6/u1/r1/reg1bit_9/SPO has no load. WARNING:LIT:243 - Logical network r6/u1/r1/reg1bit_10/SPO has no load. WARNING:LIT:243 - Logical network r6/u1/r1/reg1bit_11/SPO has no load. WARNING:LIT:243 - Logical network r6/u1/r1/reg1bit_12/SPO has no load. WARNING:LIT:243 - Logical network r6/u1/r1/reg1bit_13/SPO has no load. WARNING:LIT:243 - Logical network db0/r1/r3/reg1bit_7/SPO has no load. WARNING:LIT:243 - Logical network db0/r1/r3/reg1bit_6/SPO has no load. WARNING:LIT:243 - Logical network db0/r1/r3/reg1bit_5/SPO has no load. WARNING:LIT:243 - Logical network db0/r1/r3/reg1bit_4/SPO has no load. WARNING:LIT:243 - Logical network db0/r1/r3/reg1bit_3/SPO has no load. WARNING:LIT:243 - Logical network db0/r1/r3/reg1bit_2/SPO has no load. WARNING:LIT:243 - Logical network db0/r1/r3/reg1bit_1/SPO has no load. WARNING:LIT:243 - Logical network db0/r1/r3/reg1bit_0/SPO has no load. WARNING:LIT:243 - Logical network db0/r1/r2/reg1bit_7/SPO has no load. WARNING:LIT:243 - Logical network db0/r1/r2/reg1bit_6/SPO has no load. WARNING:LIT:243 - Logical network db0/r1/r2/reg1bit_5/SPO has no load. WARNING:LIT:243 - Logical network db0/r1/r2/reg1bit_4/SPO has no load. WARNING:LIT:243 - Logical network db0/r1/r2/reg1bit_3/SPO has no load. WARNING:LIT:243 - Logical network db0/r1/r2/reg1bit_2/SPO has no load. WARNING:LIT:243 - Logical network db0/r1/r2/reg1bit_1/SPO has no load. WARNING:LIT:243 - Logical network db0/r1/r2/reg1bit_0/SPO has no load. WARNING:LIT:243 - Logical network db0/r1/r1/reg1bit_7/SPO has no load. WARNING:LIT:243 - Logical network db0/r1/r1/reg1bit_6/SPO has no load. WARNING:LIT:243 - Logical network db0/r1/r1/reg1bit_5/SPO has no load. WARNING:LIT:243 - Logical network db0/r1/r1/reg1bit_4/SPO has no load. WARNING:LIT:243 - Logical network db0/r1/r1/reg1bit_3/SPO has no load. WARNING:LIT:243 - Logical network db0/r1/r1/reg1bit_2/SPO has no load. WARNING:LIT:243 - Logical network db0/r1/r1/reg1bit_1/SPO has no load. WARNING:LIT:243 - Logical network db0/r1/r1/reg1bit_0/SPO has no load. WARNING:LIT:243 - Logical network db0/r1/r0/reg1bit_7/SPO has no load. WARNING:LIT:243 - Logical network db0/r1/r0/reg1bit_6/SPO has no load. WARNING:LIT:243 - Logical network db0/r1/r0/reg1bit_5/SPO has no load. WARNING:LIT:243 - Logical network db0/r1/r0/reg1bit_4/SPO has no load. WARNING:LIT:243 - Logical network db0/r1/r0/reg1bit_3/SPO has no load. WARNING:LIT:243 - Logical network db0/r1/r0/reg1bit_2/SPO has no load. WARNING:LIT:243 - Logical network db0/r1/r0/reg1bit_1/SPO has no load. WARNING:LIT:243 - Logical network db0/r1/r0/reg1bit_0/SPO has no load. Mapping design into LUTs... Running directed packing... WARNING:Pack:266 - The function generator TxRx_D<7>LogicTrst62_SW0_SW0 failed to merge with F5 multiplexer TxRx_A<7>LogicTrst1_SW4. There is a conflict for the FXMUX. The design will exhibit suboptimal timing. Constraining slice packing based on guide NCD. Running delay-based LUT packing... Updating timing models... Running timing-driven placement... Total REAL time at the beginning of Placer: 13 secs Total CPU time at the beginning of Placer: 7 secs Phase 1.7 Design Feasibility Check Phase 1.7 Design Feasibility Check (Checksum:b47644bd) REAL time: 13 secs Phase 2.31 Local Placement Optimization Phase 2.31 Local Placement Optimization (Checksum:c85ef299) REAL time: 13 secs Phase 3.2 Initial Clock and IO Placement WARNING:Place:1019 - A clock IOB / clock component pair have been found that are not placed at an optimal clock IOB / clock site pair. The clock component is placed at site . The IO component is placed at site . This will not allow the use of the fast path between the IO and the Clock buffer. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint was applied on COMP.PIN allowing your design to continue. This constraint disables all clock placer rules related to the specified COMP.PIN. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. WARNING:Place:1013 - A clock IOB / DCM component pair have been found that are not placed at an optimal clock IOB / DCM site pair. The clock component is placed at site . The clock IO/DCM site can be paired if they are placed/locked in the same quadrant. The IO component is placed at site . This will not allow the use of the fast path between the IO and the Clock buffer. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint was applied on COMP.PIN allowing your design to continue. This constraint disables all clock placer rules related to the specified COMP.PIN. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. Phase 3.2 Initial Clock and IO Placement (Checksum:c85ef299) REAL time: 13 secs Phase 4.30 Global Clock Region Assignment Phase 4.30 Global Clock Region Assignment (Checksum:c85ef299) REAL time: 13 secs Phase 5.36 Local Placement Optimization Phase 5.36 Local Placement Optimization (Checksum:c85ef299) REAL time: 13 secs Phase 6.8 Global Placement ..... Phase 6.8 Global Placement (Checksum:182db7d9) REAL time: 13 secs Phase 7.5 Local Placement Optimization Phase 7.5 Local Placement Optimization (Checksum:182db7d9) REAL time: 13 secs Phase 8.18 Placement Optimization Phase 8.18 Placement Optimization (Checksum:182db7d9) REAL time: 13 secs Phase 9.5 Local Placement Optimization Phase 9.5 Local Placement Optimization (Checksum:182db7d9) REAL time: 13 secs Total REAL time to Placer completion: 13 secs Total CPU time to Placer completion: 7 secs Running physical synthesis... Physical synthesis completed. Running post-placement packing... Updating route info ... Design Summary: Number of errors: 0 Number of warnings: 73 Logic Utilization: Total Number Slice Registers: 762 out of 1,408 54% Number used as Flip Flops: 761 Number used as Latches: 1 Number of 4 input LUTs: 1,198 out of 1,408 85% Logic Distribution: Number of occupied Slices: 690 out of 704 98% Number of Slices containing only related logic: 690 out of 690 100% Number of Slices containing unrelated logic: 0 out of 690 0% *See NOTES below for an explanation of the effects of unrelated logic. Total Number of 4 input LUTs: 1,238 out of 1,408 87% Number used as logic: 1,078 Number used as a route-thru: 40 Number used for Dual Port RAMs: 120 (Two LUTs used per Dual Port RAM) The Slice Logic Distribution report is not meaningful if the design is over-mapped for a non-slice resource or if Placement fails. Number of bonded IOBs: 38 out of 68 55% IOB Flip Flops: 12 IOB Latches: 1 Number of BUFGMUXs: 2 out of 24 8% Number of DCMs: 1 out of 2 50% Number of STARTUPs: 1 out of 1 100% Number of STARTUP_SPARTAN3As: 1 out of 1 100% Number of STARTUP_SPARTAN3Es: 1 out of 1 100% Average Fanout of Non-Clock Nets: 3.34 Peak Memory Usage: 224 MB Total REAL time to MAP completion: 18 secs Total CPU time to MAP completion: 11 secs Mapping completed. See MAP report file "FPGA_ctrl_map.mrp" for details. Process "Map" completed successfully Loading device for application Rf_Device from file '3s50a.nph' in environment E:\Xilinx\11.1\ISE. "FPGA_ctrl" is an NCD, version 3.2, device xc3s50a, package vq100, speed -4 INFO:Par:469 - Although the Overall Effort Level (-ol) for this implementation has been set to Standard, Placer will run at effort level High. To override this, please set the Placer Effort Level (-pl) to Standard. Constraints file: FPGA_ctrl.pcf. "FPGA_ctrl" is an NCD, version 3.2, device xc3s50a, package vq100, speed -4 vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv INFO:Security:54 - 'xc3s50a' is a WebPack part. WARNING:Security:42 - Your software subscription period has lapsed. Your current version of Xilinx tools will continue to function, but you no longer qualify for Xilinx software updates or new releases. ---------------------------------------------------------------------- Loading database for application par from file: "FPGA_ctrl_guide.ncd" "FPGA_ctrl" is an NCD, version 3.2, device xc3s50a, package vq100, speed -4 INFO:Par:465 - The PAR option, "-t" (Starting Placer Cost Table), will be disabled in the next software release when used in combination with MAP -timing(Perform Timing-Driven Packing and Placement) or when run with V5 or newer architectures. To explore cost tables, please use the MAP option, "-t" (Starting Placer Cost Table), instead. Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000 Celsius) Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.260 Volts) INFO:Par:282 - No user timing constraints were detected or you have set the option to ignore timing constraints ("par -x"). Place and Route will run in "Performance Evaluation Mode" to automatically improve the performance of all internal clocks in this design. Because there are not defined timing requirements, a timing score will not be reported in the PAR report in this mode. The PAR timing summary will list the performance achieved for each clock. Note: For the fastest runtime, set the effort level to "std". For best performance, set the effort level to "high". Device speed data version: "PRODUCTION 1.41 2009-08-24". INFO:Par:402 - SmartGuide was run during Map. Since all guiding (mapping, packing, placement and routing) is completed in MAP, PAR does not require the use of the guide switches. The -smartguide switch only generates a post place and route guide report in the SmartGuide Report File(.GRF). Runtime can be reduced, if this detailed report is not generated. PAR will automatically generate the SmartGuide summary report based on the guide file used during MAP. This summary information is always in the PAR report file and the GRF. Design Summary Report: Number of External IOBs 38 out of 68 55% Number of External Input IOBs 9 Number of External Input IBUFs 9 Number of LOCed External Input IBUFs 9 out of 9 100% Number of External Output IOBs 20 Number of External Output IOBs 20 Number of LOCed External Output IOBs 20 out of 20 100% Number of External Bidir IOBs 9 Number of External Bidir IOBs 9 Number of LOCed External Bidir IOBs 9 out of 9 100% Number of BUFGMUXs 2 out of 24 8% Number of DCMs 1 out of 2 50% Number of Slices 690 out of 704 98% Number of SLICEMs 64 out of 352 18% Number of STARTUPs 1 out of 1 100% Overall effort level (-ol): Standard Router effort level (-rl): Standard Starting initial Timing Analysis. REAL time: 3 secs Finished initial Timing Analysis. REAL time: 3 secs Starting Router Phase 1 : 748 unrouted; REAL time: 4 secs Phase 2 : 670 unrouted; REAL time: 4 secs Phase 3 : 199 unrouted; REAL time: 5 secs Phase 4 : 372 unrouted; (Par is working to improve performance) REAL time: 5 secs Phase 5 : 0 unrouted; (Par is working to improve performance) REAL time: 6 secs Updating file: FPGA_ctrl.ncd with current fully routed design. Phase 6 : 0 unrouted; (Par is working to improve performance) REAL time: 7 secs Phase 7 : 0 unrouted; (Par is working to improve performance) REAL time: 7 secs Phase 8 : 0 unrouted; (Par is working to improve performance) REAL time: 9 secs Phase 9 : 0 unrouted; (Par is working to improve performance) REAL time: 9 secs Phase 10 : 0 unrouted; (Par is working to improve performance) REAL time: 9 secs Phase 11 : 0 unrouted; (Par is working to improve performance) REAL time: 10 secs WARNING:Route:455 - CLK Net:uResS/Done_Byte may have excessive skew because 2 CLK pins and 0 NON_CLK pins failed to route using a CLK template. WARNING:Route:455 - CLK Net:uXmit/uSpack/Done_Word may have excessive skew because 2 CLK pins and 0 NON_CLK pins failed to route using a CLK template. WARNING:Route:455 - CLK Net:db0/u0/serClk may have excessive skew because 0 CLK pins and 1 NON_CLK pins failed to route using a CLK template. WARNING:Route:455 - CLK Net:db0/u2/Q may have excessive skew because 1 CLK pins and 11 NON_CLK pins failed to route using a CLK template. WARNING:Route:455 - CLK Net:uXmit/uDpack/Done_Word may have excessive skew because 1 CLK pins and 1 NON_CLK pins failed to route using a CLK template. WARNING:Route:455 - CLK Net:Rst_int may have excessive skew because 0 CLK pins and 71 NON_CLK pins failed to route using a CLK template. WARNING:Route:455 - CLK Net:uXmit/uTxMAC/u1/Q may have excessive skew because 0 CLK pins and 3 NON_CLK pins failed to route using a CLK template. WARNING:Route:455 - CLK Net:ser_Go_uINT may have excessive skew because 1 CLK pins and 11 NON_CLK pins failed to route using a CLK template. WARNING:Route:455 - CLK Net:uXmit/uDpack/u1/Q may have excessive skew because 0 CLK pins and 11 NON_CLK pins failed to route using a CLK template. WARNING:Route:455 - CLK Net:uXmit/uDpack/w/C_0_0_not0000 may have excessive skew because 0 CLK pins and 7 NON_CLK pins failed to route using a CLK template. WARNING:Route:455 - CLK Net:uQuer/u3/u1/Q may have excessive skew because 3 CLK pins and 18 NON_CLK pins failed to route using a CLK template. WARNING:Route:455 - CLK Net:uINT/u4/u2/Q may have excessive skew because 1 CLK pins and 12 NON_CLK pins failed to route using a CLK template. Total REAL time to Router completion: 10 secs Total CPU time to Router completion: 9 secs SmartGuide Results ------------------ This section describes the guide results after invoking the Router. This report accurately reflects the differences between the input design and the guide design. Number of Components in the input design | 732 Number of guided Components | 732 out of 732 100.0% Number of re-implemented Components | 0 out of 732 0.0% Number of new/changed Components | 0 out of 732 0.0% Number of Nets in the input design | 1690 Number of guided Nets | 1312 out of 1690 77.6% Number of partially guided Nets | 260 out of 1690 15.4% Number of re-routed Nets | 118 out of 1690 7.0% Number of new/changed Nets | 0 out of 1690 0.0% Partition Implementation Status ------------------------------- No Partitions were found in this design. ------------------------------- Generating "PAR" statistics. ************************** Generating Clock Report ************************** +---------------------+--------------+------+------+------------+-------------+ | Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)| +---------------------+--------------+------+------+------------+-------------+ | DAC_Clk_OBUF | BUFGMUX_X2Y11| No | 585 | 0.566 | 1.037 | +---------------------+--------------+------+------+------------+-------------+ | fClk_out_OBUF | BUFGMUX_X1Y1| No | 31 | 0.066 | 0.541 | +---------------------+--------------+------+------+------------+-------------+ | Rst_int | Local| | 274 | 0.000 | 3.863 | +---------------------+--------------+------+------+------------+-------------+ | ser_Go_uINT | Local| | 12 | 0.000 | 0.759 | +---------------------+--------------+------+------+------------+-------------+ |uXmit/uDpack/w/C_0_0 | | | | | | | _not0000 | Local| | 11 | 0.038 | 1.733 | +---------------------+--------------+------+------+------------+-------------+ | uINT/u4/u2/Q | Local| | 16 | 1.207 | 2.742 | +---------------------+--------------+------+------+------------+-------------+ | uXmit/uDpack/u1/Q | Local| | 15 | 0.205 | 2.244 | +---------------------+--------------+------+------+------------+-------------+ | uXmit/uTxMAC/u1/Q | Local| | 6 | 0.088 | 1.766 | +---------------------+--------------+------+------+------------+-------------+ | db0/u0/serClk | Local| | 4 | 0.058 | 1.896 | +---------------------+--------------+------+------+------------+-------------+ | uQuer/u3/u1/Q | Local| | 21 | 0.004 | 1.515 | +---------------------+--------------+------+------+------------+-------------+ | uResS/Done_Byte | Local| | 2 | 0.361 | 2.261 | +---------------------+--------------+------+------+------------+-------------+ |uXmit/uSpack/Done_Wo | | | | | | | rd | Local| | 6 | 1.934 | 2.547 | +---------------------+--------------+------+------+------------+-------------+ |uXmit/uDpack/Done_Wo | | | | | | | rd | Local| | 2 | 0.000 | 1.436 | +---------------------+--------------+------+------+------------+-------------+ | db0/u2/Q | Local| | 12 | 0.000 | 2.365 | +---------------------+--------------+------+------+------------+-------------+ * Net Skew is the difference between the minimum and maximum routing only delays for the net. Note this is different from Clock Skew which is reported in TRCE timing report. Clock Skew is the difference between the minimum and maximum path delays which includes logic delays. Timing Score: 0 (Setup: 0, Hold: 0) Asterisk (*) preceding a constraint indicates it was not met. This may be due to a setup or hold violation. ---------------------------------------------------------------------------------------------------------- Constraint | Check | Worst Case | Best Case | Timing | Timing | | Slack | Achievable | Errors | Score ---------------------------------------------------------------------------------------------------------- Autotimespec constraint for clock net DAC | SETUP | N/A| 27.720ns| N/A| 0 _Clk_OBUF | HOLD | 0.911ns| | 0| 0 ---------------------------------------------------------------------------------------------------------- Autotimespec constraint for clock net uXm | SETUP | N/A| 3.250ns| N/A| 0 it/uDpack/w/C_0_0_not0000 | HOLD | 1.375ns| | 0| 0 ---------------------------------------------------------------------------------------------------------- Autotimespec constraint for clock net uXm | SETUP | N/A| 4.185ns| N/A| 0 it/uDpack/u1/Q | HOLD | 0.926ns| | 0| 0 ---------------------------------------------------------------------------------------------------------- Autotimespec constraint for clock net uXm | SETUP | N/A| 2.454ns| N/A| 0 it/uTxMAC/u1/Q | HOLD | 1.242ns| | 0| 0 ---------------------------------------------------------------------------------------------------------- Autotimespec constraint for clock net fCl | SETUP | N/A| 29.064ns| N/A| 0 k_out_OBUF | HOLD | 1.067ns| | 0| 0 ---------------------------------------------------------------------------------------------------------- Autotimespec constraint for clock net db0 | SETUP | N/A| 4.648ns| N/A| 0 /u0/serClk | HOLD | 1.026ns| | 0| 0 ---------------------------------------------------------------------------------------------------------- Autotimespec constraint for clock net uQu | SETUP | N/A| 2.257ns| N/A| 0 er/u3/u1/Q | HOLD | 1.246ns| | 0| 0 ---------------------------------------------------------------------------------------------------------- Autotimespec constraint for clock net uRe | SETUP | N/A| 2.489ns| N/A| 0 sS/Done_Byte | HOLD | 1.197ns| | 0| 0 ---------------------------------------------------------------------------------------------------------- Autotimespec constraint for clock net uXm | SETUP | N/A| 6.312ns| N/A| 0 it/uSpack/Done_Word | HOLD | 0.900ns| | 0| 0 ---------------------------------------------------------------------------------------------------------- All constraints were met. INFO:Timing:2761 - N/A entries in the Constraints list may indicate that the constraint does not cover any paths or that it has no requested value. Generating Pad Report. All signals are completely routed. Total REAL time to PAR completion: 11 secs Total CPU time to PAR completion: 11 secs Peak Memory Usage: 156 MB Placer: Placement generated during map. Routing: Completed - No errors found. Number of error messages: 0 Number of warning messages: 12 Number of info messages: 4 Writing design to file FPGA_ctrl.ncd PAR done! Process "Place & Route" completed successfully Started : "Generate Post-Place & Route Static Timing". Loading device for application Rf_Device from file '3s50a.nph' in environment E:\Xilinx\11.1\ISE. "FPGA_ctrl" is an NCD, version 3.2, device xc3s50a, package vq100, speed -4 Analysis completed Fri Oct 01 17:19:54 2010 -------------------------------------------------------------------------------- Generating Report ... Number of warnings: 0 Total time: 3 secs Process "Generate Post-Place & Route Static Timing" completed successfully Started : "Generate Programming File". WARNING:Bitgen:101 - There is a STARTUP component with a signal on the CLK pin but StartupClk is Cclk. WARNING:PhysDesignRules:372 - Gated clock. Clock net Rst_int is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. WARNING:PhysDesignRules:372 - Gated clock. Clock net ser_Go_uINT is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. WARNING:PhysDesignRules:372 - Gated clock. Clock net uXmit/uDpack/w/C_0_0_not0000 is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. WARNING:PhysDesignRules:372 - Gated clock. Clock net uResS/Done_Byte is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. WARNING:PhysDesignRules:372 - Gated clock. Clock net uXmit/uSpack/Done_Word is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. WARNING:PhysDesignRules:372 - Gated clock. Clock net uXmit/uDpack/Done_Word is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. Process "Generate Programming File" completed successfully