Release 11.2 - ngc2edif L.46 (nt) Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved. Reading design FPGA_ctrl.ngc ... WARNING:NetListWriters:298 - No output is written to FPGA_ctrl.xncf, ignored. Processing design ... Preping design's networks ... Preping design's macros ... WARNING:NetListWriters:306 - Signal bus state_D<2 : 0> on block FPGA_ctrl is not reconstructed, because there are some missing bus signals. WARNING:NetListWriters:306 - Signal bus u8/Mtridata_DAC_D<10 : 0> on block FPGA_ctrl is not reconstructed, because there are some missing bus signals. WARNING:NetListWriters:306 - Signal bus u8/Mtridata_DAC_D_mux0000<10 : 0> on block FPGA_ctrl is not reconstructed, because there are some missing bus signals. WARNING:NetListWriters:306 - Signal bus u8/VoltData<9 : 7> on block FPGA_ctrl is not reconstructed, because there are some missing bus signals. finished :Prep Writing EDIF netlist file FPGA_ctrl.edif ... ngc2edif: Total memory usage is 38112 kilobytes Release 11.2 - ngc2edif L.46 (nt) Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved. Reading design FPGA_ctrl.ngc ... WARNING:NetListWriters:298 - No output is written to FPGA_ctrl.xncf, ignored. Processing design ... Preping design's networks ... Preping design's macros ... WARNING:NetListWriters:306 - Signal bus state_D<2 : 0> on block FPGA_ctrl is not reconstructed, because there are some missing bus signals. WARNING:NetListWriters:306 - Signal bus u8/Mtridata_DAC_D<10 : 0> on block FPGA_ctrl is not reconstructed, because there are some missing bus signals. WARNING:NetListWriters:306 - Signal bus u8/Mtridata_DAC_D_mux0000<10 : 0> on block FPGA_ctrl is not reconstructed, because there are some missing bus signals. WARNING:NetListWriters:306 - Signal bus u8/VoltData<9 : 7> on block FPGA_ctrl is not reconstructed, because there are some missing bus signals. finished :Prep Writing EDIF netlist file FPGA_ctrl.edif ... ngc2edif: Total memory usage is 38112 kilobytes Release 11.2 - ngc2edif L.46 (nt) Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved. Reading design FPGA_ctrl.ngc ... WARNING:NetListWriters:298 - No output is written to FPGA_ctrl.xncf, ignored. Processing design ... Preping design's networks ... Preping design's macros ... WARNING:NetListWriters:306 - Signal bus state_D<2 : 0> on block FPGA_ctrl is not reconstructed, because there are some missing bus signals. WARNING:NetListWriters:306 - Signal bus u8/Mtridata_DAC_D<10 : 0> on block FPGA_ctrl is not reconstructed, because there are some missing bus signals. WARNING:NetListWriters:306 - Signal bus u8/Mtridata_DAC_D_mux0000<10 : 0> on block FPGA_ctrl is not reconstructed, because there are some missing bus signals. WARNING:NetListWriters:306 - Signal bus u8/VoltData<9 : 7> on block FPGA_ctrl is not reconstructed, because there are some missing bus signals. finished :Prep Writing EDIF netlist file FPGA_ctrl.edif ... ngc2edif: Total memory usage is 38112 kilobytes Release 11.2 - ngc2edif L.46 (nt) Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved. Reading design FPGA_ctrl.ngc ... WARNING:NetListWriters:298 - No output is written to FPGA_ctrl.xncf, ignored. Processing design ... Preping design's networks ... Preping design's macros ... WARNING:NetListWriters:306 - Signal bus state_D<2 : 0> on block FPGA_ctrl is not reconstructed, because there are some missing bus signals. WARNING:NetListWriters:306 - Signal bus u8/Mtridata_DAC_D<10 : 0> on block FPGA_ctrl is not reconstructed, because there are some missing bus signals. WARNING:NetListWriters:306 - Signal bus u8/Mtridata_DAC_D_mux0000<10 : 0> on block FPGA_ctrl is not reconstructed, because there are some missing bus signals. WARNING:NetListWriters:306 - Signal bus u8/VoltData<9 : 7> on block FPGA_ctrl is not reconstructed, because there are some missing bus signals. finished :Prep Writing EDIF netlist file FPGA_ctrl.edif ... ngc2edif: Total memory usage is 38112 kilobytes Release 11.2 - ngc2edif L.46 (nt) Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved. Reading design FPGA_ctrl.ngc ... WARNING:NetListWriters:298 - No output is written to FPGA_ctrl.xncf, ignored. Processing design ... Preping design's networks ... Preping design's macros ... WARNING:NetListWriters:306 - Signal bus state_D<2 : 0> on block FPGA_ctrl is not reconstructed, because there are some missing bus signals. WARNING:NetListWriters:306 - Signal bus u8/Mtridata_DAC_D<10 : 0> on block FPGA_ctrl is not reconstructed, because there are some missing bus signals. WARNING:NetListWriters:306 - Signal bus u8/Mtridata_DAC_D_mux0000<10 : 0> on block FPGA_ctrl is not reconstructed, because there are some missing bus signals. WARNING:NetListWriters:306 - Signal bus u8/VoltData<9 : 7> on block FPGA_ctrl is not reconstructed, because there are some missing bus signals. finished :Prep Writing EDIF netlist file FPGA_ctrl.edif ... ngc2edif: Total memory usage is 38112 kilobytes Release 11.2 - ngc2edif L.46 (nt) Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved. Reading design FPGA_ctrl.ngc ... WARNING:NetListWriters:298 - No output is written to FPGA_ctrl.xncf, ignored. Processing design ... Preping design's networks ... Preping design's macros ... WARNING:NetListWriters:306 - Signal bus state_D<2 : 0> on block FPGA_ctrl is not reconstructed, because there are some missing bus signals. WARNING:NetListWriters:306 - Signal bus u8/Mtridata_DAC_D<10 : 0> on block FPGA_ctrl is not reconstructed, because there are some missing bus signals. WARNING:NetListWriters:306 - Signal bus u8/Mtridata_DAC_D_mux0000<10 : 0> on block FPGA_ctrl is not reconstructed, because there are some missing bus signals. WARNING:NetListWriters:306 - Signal bus u8/VoltData<9 : 7> on block FPGA_ctrl is not reconstructed, because there are some missing bus signals. finished :Prep Writing EDIF netlist file FPGA_ctrl.edif ... ngc2edif: Total memory usage is 38112 kilobytes Release 11.2 - ngc2edif L.46 (nt) Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved. Reading design FPGA_ctrl.ngc ... WARNING:NetListWriters:298 - No output is written to FPGA_ctrl.xncf, ignored. Processing design ... Preping design's networks ... Preping design's macros ... WARNING:NetListWriters:306 - Signal bus state_D<2 : 0> on block FPGA_ctrl is not reconstructed, because there are some missing bus signals. WARNING:NetListWriters:306 - Signal bus u8/Mtridata_DAC_D<10 : 0> on block FPGA_ctrl is not reconstructed, because there are some missing bus signals. WARNING:NetListWriters:306 - Signal bus u8/Mtridata_DAC_D_mux0000<10 : 0> on block FPGA_ctrl is not reconstructed, because there are some missing bus signals. WARNING:NetListWriters:306 - Signal bus u8/VoltData<9 : 7> on block FPGA_ctrl is not reconstructed, because there are some missing bus signals. finished :Prep Writing EDIF netlist file FPGA_ctrl.edif ... ngc2edif: Total memory usage is 38112 kilobytes Release 11.2 - ngc2edif L.46 (nt) Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved. Reading design FPGA_ctrl.ngc ... WARNING:NetListWriters:298 - No output is written to FPGA_ctrl.xncf, ignored. Processing design ... Preping design's networks ... Preping design's macros ... WARNING:NetListWriters:306 - Signal bus state_D<2 : 0> on block FPGA_ctrl is not reconstructed, because there are some missing bus signals. WARNING:NetListWriters:306 - Signal bus u8/Mtridata_DAC_D<10 : 0> on block FPGA_ctrl is not reconstructed, because there are some missing bus signals. WARNING:NetListWriters:306 - Signal bus u8/Mtridata_DAC_D_mux0000<10 : 0> on block FPGA_ctrl is not reconstructed, because there are some missing bus signals. WARNING:NetListWriters:306 - Signal bus u8/VoltData<9 : 7> on block FPGA_ctrl is not reconstructed, because there are some missing bus signals. finished :Prep Writing EDIF netlist file FPGA_ctrl.edif ... ngc2edif: Total memory usage is 38136 kilobytes Release 11.2 - ngc2edif L.46 (nt) Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved. Reading design FPGA_ctrl.ngc ... WARNING:NetListWriters:298 - No output is written to FPGA_ctrl.xncf, ignored. Processing design ... Preping design's networks ... Preping design's macros ... WARNING:NetListWriters:306 - Signal bus state_D<2 : 0> on block FPGA_ctrl is not reconstructed, because there are some missing bus signals. WARNING:NetListWriters:306 - Signal bus u8/Mtridata_DAC_D<10 : 0> on block FPGA_ctrl is not reconstructed, because there are some missing bus signals. WARNING:NetListWriters:306 - Signal bus u8/Mtridata_DAC_D_mux0000<10 : 0> on block FPGA_ctrl is not reconstructed, because there are some missing bus signals. WARNING:NetListWriters:306 - Signal bus u8/VoltData<9 : 7> on block FPGA_ctrl is not reconstructed, because there are some missing bus signals. finished :Prep Writing EDIF netlist file FPGA_ctrl.edif ... ngc2edif: Total memory usage is 38136 kilobytes Release 11.2 - ngc2edif L.46 (nt) Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved. Reading design FPGA_ctrl.ngc ... WARNING:NetListWriters:298 - No output is written to FPGA_ctrl.xncf, ignored. Processing design ... Preping design's networks ... Preping design's macros ... finished :Prep Writing EDIF netlist file FPGA_ctrl.edif ... ngc2edif: Total memory usage is 37180 kilobytes Release 11.2 - ngc2edif L.46 (nt) Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved. Reading design FPGA_ctrl.ngc ... WARNING:NetListWriters:298 - No output is written to FPGA_ctrl.xncf, ignored. Processing design ... Preping design's networks ... Preping design's macros ... finished :Prep Writing EDIF netlist file FPGA_ctrl.edif ... ngc2edif: Total memory usage is 37180 kilobytes Release 11.2 - ngc2edif L.46 (nt) Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved. Reading design FPGA_ctrl.ngc ... WARNING:NetListWriters:298 - No output is written to FPGA_ctrl.xncf, ignored. Processing design ... Preping design's networks ... Preping design's macros ... WARNING:NetListWriters:306 - Signal bus TxRx_A<7 : 0> on block FPGA_ctrl is not reconstructed, because there are some missing bus signals. WARNING:NetListWriters:306 - Signal bus u0/Addr<7 : 0> on block FPGA_ctrl is not reconstructed, because there are some missing bus signals. finished :Prep Writing EDIF netlist file FPGA_ctrl.edif ... ngc2edif: Total memory usage is 35672 kilobytes Release 11.2 - ngc2edif L.46 (nt) Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved. Reading design FPGA_ctrl.ngc ... WARNING:NetListWriters:298 - No output is written to FPGA_ctrl.xncf, ignored. Processing design ... Preping design's networks ... Preping design's macros ... finished :Prep Writing EDIF netlist file FPGA_ctrl.edif ... ngc2edif: Total memory usage is 36696 kilobytes Release 11.2 - ngc2edif L.46 (nt) Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved. Reading design FPGA_ctrl.ngc ... WARNING:NetListWriters:298 - No output is written to FPGA_ctrl.xncf, ignored. Processing design ... Preping design's networks ... Preping design's macros ... WARNING:NetListWriters:306 - Signal bus SReg<18 : 0> on block DAC_shiftreg is not reconstructed, because there are some missing bus signals. WARNING:NetListWriters:306 - Signal bus Data<6 : 3> on block Reg8bit_NO27 is not reconstructed, because there are some missing bus signals. WARNING:NetListWriters:306 - Signal bus Data<6 : 0> on block Reg8bit_NO26 is not reconstructed, because there are some missing bus signals. WARNING:NetListWriters:306 - Signal bus Data<6 : 2> on block Reg8bit_NO25 is not reconstructed, because there are some missing bus signals. WARNING:NetListWriters:306 - Signal bus Data<6 : 3> on block Reg8bit_NO24 is not reconstructed, because there are some missing bus signals. WARNING:NetListWriters:306 - Signal bus Data<6 : 2> on block Reg8bit_NO23 is not reconstructed, because there are some missing bus signals. WARNING:NetListWriters:306 - Signal bus Data<6 : 1> on block Reg8bit_NO21 is not reconstructed, because there are some missing bus signals. WARNING:NetListWriters:306 - Signal bus Data<3 : 0> on block Reg8bit_NO20 is not reconstructed, because there are some missing bus signals. WARNING:NetListWriters:306 - Signal bus Data<6 : 1> on block Reg8bit_NO18 is not reconstructed, because there are some missing bus signals. WARNING:NetListWriters:306 - Signal bus Data<6 : 0> on block Reg8bit_NO13 is not reconstructed, because there are some missing bus signals. WARNING:NetListWriters:306 - Signal bus Data<3 : 0> on block Reg8bit_NO12 is not reconstructed, because there are some missing bus signals. WARNING:NetListWriters:306 - Signal bus Data<7 : 0> on block Reg8bit_NO10 is not reconstructed, because there are some missing bus signals. WARNING:NetListWriters:306 - Signal bus Data<3 : 0> on block Reg8bit_NO9 is not reconstructed, because there are some missing bus signals. WARNING:NetListWriters:306 - Signal bus Data<4 : 0> on block Reg8bit_NO8 is not reconstructed, because there are some missing bus signals. WARNING:NetListWriters:306 - Signal bus Data<3 : 0> on block Reg8bit_NO7 is not reconstructed, because there are some missing bus signals. WARNING:NetListWriters:306 - Signal bus Data<4 : 1> on block Reg8bit_NO6 is not reconstructed, because there are some missing bus signals. WARNING:NetListWriters:306 - Signal bus Data<3 : 0> on block Reg8bit_NO5 is not reconstructed, because there are some missing bus signals. WARNING:NetListWriters:306 - Signal bus Data<7 : 1> on block Reg8bit_NO4 is not reconstructed, because there are some missing bus signals. WARNING:NetListWriters:306 - Signal bus Data<3 : 0> on block Reg8bit_NO3 is not reconstructed, because there are some missing bus signals. WARNING:NetListWriters:306 - Signal bus Data<3 : 0> on block Reg8bit_NO1 is not reconstructed, because there are some missing bus signals. WARNING:NetListWriters:306 - Signal bus u1/m2/m2/AddrL_reg<3 : 0> on block FPGA_ctrl is not reconstructed, because there are some missing bus signals. WARNING:NetListWriters:306 - Signal bus u1/m2/m2/Data<7 : 0> on block FPGA_ctrl is not reconstructed, because there are some missing bus signals. WARNING:NetListWriters:306 - Signal bus u1/m3/m2/AddrL_reg<3 : 0> on block FPGA_ctrl is not reconstructed, because there are some missing bus signals. WARNING:NetListWriters:306 - Signal bus u1/m3/m2/Data<4 : 0> on block FPGA_ctrl is not reconstructed, because there are some missing bus signals. WARNING:NetListWriters:306 - Signal bus u1/m4/m2/AddrL_reg<3 : 0> on block FPGA_ctrl is not reconstructed, because there are some missing bus signals. WARNING:NetListWriters:306 - Signal bus u1/m4/m2/Data<4 : 1> on block FPGA_ctrl is not reconstructed, because there are some missing bus signals. WARNING:NetListWriters:306 - Signal bus u1/m5/m2/AddrL_reg<3 : 0> on block FPGA_ctrl is not reconstructed, because there are some missing bus signals. WARNING:NetListWriters:306 - Signal bus u1/m5/m2/Data<7 : 1> on block FPGA_ctrl is not reconstructed, because there are some missing bus signals. WARNING:NetListWriters:306 - Signal bus u1/m6/a1/AddrL_reg<6 : 0> on block FPGA_ctrl is not reconstructed, because there are some missing bus signals. WARNING:NetListWriters:306 - Signal bus u1/m6/m/m2/AddrL_reg<3 : 0> on block FPGA_ctrl is not reconstructed, because there are some missing bus signals. WARNING:NetListWriters:306 - Signal bus u1/m7/m2/AddrL_reg<3 : 0> on block FPGA_ctrl is not reconstructed, because there are some missing bus signals. WARNING:NetListWriters:306 - Signal bus u3/RAwr_aH/AddrL_reg<3 : 0> on block FPGA_ctrl is not reconstructed, because there are some missing bus signals. WARNING:NetListWriters:306 - Signal bus u3/uDpack/u2/AddrL_reg<6 : 3> on block FPGA_ctrl is not reconstructed, because there are some missing bus signals. WARNING:NetListWriters:306 - Signal bus u3/uDpack/u2/Data<6 : 2> on block FPGA_ctrl is not reconstructed, because there are some missing bus signals. WARNING:NetListWriters:306 - Signal bus u3/uDpack/w/Data<6 : 2> on block FPGA_ctrl is not reconstructed, because there are some missing bus signals. WARNING:NetListWriters:306 - Signal bus u3/uSpack/uTxSt1/AddrL_reg<6 : 3> on block FPGA_ctrl is not reconstructed, because there are some missing bus signals. WARNING:NetListWriters:306 - Signal bus u3/uSpack/w/Data<6 : 0> on block FPGA_ctrl is not reconstructed, because there are some missing bus signals. WARNING:NetListWriters:306 - Signal bus u3/uTxS2/AddrL_reg<6 : 1> on block FPGA_ctrl is not reconstructed, because there are some missing bus signals. WARNING:NetListWriters:306 - Signal bus u3/uTxSt1/AddrL_reg<6 : 1> on block FPGA_ctrl is not reconstructed, because there are some missing bus signals. finished :Prep Writing EDIF netlist file FPGA_ctrl.edif ... ngc2edif: Total memory usage is 36696 kilobytes Release 11.2 - ngc2edif L.46 (nt) Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved. Reading design FPGA_ctrl.ngc ... WARNING:NetListWriters:298 - No output is written to FPGA_ctrl.xncf, ignored. Processing design ... Preping design's networks ... Preping design's macros ... WARNING:NetListWriters:306 - Signal bus SReg<18 : 0> on block DAC_shiftreg is not reconstructed, because there are some missing bus signals. WARNING:NetListWriters:306 - Signal bus Data<6 : 3> on block Reg8bit_NO27 is not reconstructed, because there are some missing bus signals. WARNING:NetListWriters:306 - Signal bus Data<6 : 0> on block Reg8bit_NO26 is not reconstructed, because there are some missing bus signals. WARNING:NetListWriters:306 - Signal bus Data<6 : 2> on block Reg8bit_NO25 is not reconstructed, because there are some missing bus signals. WARNING:NetListWriters:306 - Signal bus Data<6 : 3> on block Reg8bit_NO24 is not reconstructed, because there are some missing bus signals. WARNING:NetListWriters:306 - Signal bus Data<6 : 2> on block Reg8bit_NO23 is not reconstructed, because there are some missing bus signals. WARNING:NetListWriters:306 - Signal bus Data<6 : 1> on block Reg8bit_NO21 is not reconstructed, because there are some missing bus signals. WARNING:NetListWriters:306 - Signal bus Data<3 : 0> on block Reg8bit_NO20 is not reconstructed, because there are some missing bus signals. WARNING:NetListWriters:306 - Signal bus Data<6 : 1> on block Reg8bit_NO18 is not reconstructed, because there are some missing bus signals. WARNING:NetListWriters:306 - Signal bus Data<6 : 0> on block Reg8bit_NO13 is not reconstructed, because there are some missing bus signals. WARNING:NetListWriters:306 - Signal bus Data<3 : 0> on block Reg8bit_NO12 is not reconstructed, because there are some missing bus signals. WARNING:NetListWriters:306 - Signal bus Data<7 : 0> on block Reg8bit_NO10 is not reconstructed, because there are some missing bus signals. WARNING:NetListWriters:306 - Signal bus Data<3 : 0> on block Reg8bit_NO9 is not reconstructed, because there are some missing bus signals. WARNING:NetListWriters:306 - Signal bus Data<4 : 0> on block Reg8bit_NO8 is not reconstructed, because there are some missing bus signals. WARNING:NetListWriters:306 - Signal bus Data<3 : 0> on block Reg8bit_NO7 is not reconstructed, because there are some missing bus signals. WARNING:NetListWriters:306 - Signal bus Data<4 : 1> on block Reg8bit_NO6 is not reconstructed, because there are some missing bus signals. WARNING:NetListWriters:306 - Signal bus Data<3 : 0> on block Reg8bit_NO5 is not reconstructed, because there are some missing bus signals. WARNING:NetListWriters:306 - Signal bus Data<7 : 1> on block Reg8bit_NO4 is not reconstructed, because there are some missing bus signals. WARNING:NetListWriters:306 - Signal bus Data<3 : 0> on block Reg8bit_NO3 is not reconstructed, because there are some missing bus signals. WARNING:NetListWriters:306 - Signal bus Data<3 : 0> on block Reg8bit_NO1 is not reconstructed, because there are some missing bus signals. WARNING:NetListWriters:306 - Signal bus u1/m2/m2/AddrL_reg<3 : 0> on block FPGA_ctrl is not reconstructed, because there are some missing bus signals. WARNING:NetListWriters:306 - Signal bus u1/m2/m2/Data<7 : 0> on block FPGA_ctrl is not reconstructed, because there are some missing bus signals. WARNING:NetListWriters:306 - Signal bus u1/m3/m2/AddrL_reg<3 : 0> on block FPGA_ctrl is not reconstructed, because there are some missing bus signals. WARNING:NetListWriters:306 - Signal bus u1/m3/m2/Data<4 : 0> on block FPGA_ctrl is not reconstructed, because there are some missing bus signals. WARNING:NetListWriters:306 - Signal bus u1/m4/m2/AddrL_reg<3 : 0> on block FPGA_ctrl is not reconstructed, because there are some missing bus signals. WARNING:NetListWriters:306 - Signal bus u1/m4/m2/Data<4 : 1> on block FPGA_ctrl is not reconstructed, because there are some missing bus signals. WARNING:NetListWriters:306 - Signal bus u1/m5/m2/AddrL_reg<3 : 0> on block FPGA_ctrl is not reconstructed, because there are some missing bus signals. WARNING:NetListWriters:306 - Signal bus u1/m5/m2/Data<7 : 1> on block FPGA_ctrl is not reconstructed, because there are some missing bus signals. WARNING:NetListWriters:306 - Signal bus u1/m6/a1/AddrL_reg<6 : 0> on block FPGA_ctrl is not reconstructed, because there are some missing bus signals. WARNING:NetListWriters:306 - Signal bus u1/m6/m/m2/AddrL_reg<3 : 0> on block FPGA_ctrl is not reconstructed, because there are some missing bus signals. WARNING:NetListWriters:306 - Signal bus u1/m7/m2/AddrL_reg<3 : 0> on block FPGA_ctrl is not reconstructed, because there are some missing bus signals. WARNING:NetListWriters:306 - Signal bus u3/RAwr_aH/AddrL_reg<3 : 0> on block FPGA_ctrl is not reconstructed, because there are some missing bus signals. WARNING:NetListWriters:306 - Signal bus u3/uDpack/u2/AddrL_reg<6 : 3> on block FPGA_ctrl is not reconstructed, because there are some missing bus signals. WARNING:NetListWriters:306 - Signal bus u3/uDpack/u2/Data<6 : 2> on block FPGA_ctrl is not reconstructed, because there are some missing bus signals. WARNING:NetListWriters:306 - Signal bus u3/uDpack/w/Data<6 : 2> on block FPGA_ctrl is not reconstructed, because there are some missing bus signals. WARNING:NetListWriters:306 - Signal bus u3/uSpack/uTxSt1/AddrL_reg<6 : 3> on block FPGA_ctrl is not reconstructed, because there are some missing bus signals. WARNING:NetListWriters:306 - Signal bus u3/uSpack/w/Data<6 : 0> on block FPGA_ctrl is not reconstructed, because there are some missing bus signals. WARNING:NetListWriters:306 - Signal bus u3/uTxS2/AddrL_reg<6 : 1> on block FPGA_ctrl is not reconstructed, because there are some missing bus signals. WARNING:NetListWriters:306 - Signal bus u3/uTxSt1/AddrL_reg<6 : 1> on block FPGA_ctrl is not reconstructed, because there are some missing bus signals. finished :Prep Writing EDIF netlist file FPGA_ctrl.edif ... ngc2edif: Total memory usage is 36696 kilobytes Release 11.2 - ngc2edif L.46 (nt) Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved. Reading design FPGA_ctrl.ngc ... WARNING:NetListWriters:298 - No output is written to FPGA_ctrl.xncf, ignored. Processing design ... Preping design's networks ... Preping design's macros ... WARNING:NetListWriters:306 - Signal bus SReg<18 : 0> on block DAC_shiftreg is not reconstructed, because there are some missing bus signals. WARNING:NetListWriters:306 - Signal bus Data<6 : 3> on block Reg8bit_NO27 is not reconstructed, because there are some missing bus signals. WARNING:NetListWriters:306 - Signal bus Data<6 : 0> on block Reg8bit_NO26 is not reconstructed, because there are some missing bus signals. WARNING:NetListWriters:306 - Signal bus Data<6 : 2> on block Reg8bit_NO25 is not reconstructed, because there are some missing bus signals. WARNING:NetListWriters:306 - Signal bus Data<6 : 3> on block Reg8bit_NO24 is not reconstructed, because there are some missing bus signals. WARNING:NetListWriters:306 - Signal bus Data<6 : 2> on block Reg8bit_NO23 is not reconstructed, because there are some missing bus signals. WARNING:NetListWriters:306 - Signal bus Data<6 : 1> on block Reg8bit_NO21 is not reconstructed, because there are some missing bus signals. WARNING:NetListWriters:306 - Signal bus Data<3 : 0> on block Reg8bit_NO20 is not reconstructed, because there are some missing bus signals. WARNING:NetListWriters:306 - Signal bus Data<6 : 1> on block Reg8bit_NO18 is not reconstructed, because there are some missing bus signals. WARNING:NetListWriters:306 - Signal bus Data<6 : 0> on block Reg8bit_NO13 is not reconstructed, because there are some missing bus signals. WARNING:NetListWriters:306 - Signal bus Data<3 : 0> on block Reg8bit_NO12 is not reconstructed, because there are some missing bus signals. WARNING:NetListWriters:306 - Signal bus Data<7 : 0> on block Reg8bit_NO10 is not reconstructed, because there are some missing bus signals. WARNING:NetListWriters:306 - Signal bus Data<3 : 0> on block Reg8bit_NO9 is not reconstructed, because there are some missing bus signals. WARNING:NetListWriters:306 - Signal bus Data<4 : 0> on block Reg8bit_NO8 is not reconstructed, because there are some missing bus signals. WARNING:NetListWriters:306 - Signal bus Data<3 : 0> on block Reg8bit_NO7 is not reconstructed, because there are some missing bus signals. WARNING:NetListWriters:306 - Signal bus Data<4 : 1> on block Reg8bit_NO6 is not reconstructed, because there are some missing bus signals. WARNING:NetListWriters:306 - Signal bus Data<3 : 0> on block Reg8bit_NO5 is not reconstructed, because there are some missing bus signals. WARNING:NetListWriters:306 - Signal bus Data<7 : 1> on block Reg8bit_NO4 is not reconstructed, because there are some missing bus signals. WARNING:NetListWriters:306 - Signal bus Data<3 : 0> on block Reg8bit_NO3 is not reconstructed, because there are some missing bus signals. WARNING:NetListWriters:306 - Signal bus Data<3 : 0> on block Reg8bit_NO1 is not reconstructed, because there are some missing bus signals. WARNING:NetListWriters:306 - Signal bus u1/m2/m2/AddrL_reg<3 : 0> on block FPGA_ctrl is not reconstructed, because there are some missing bus signals. WARNING:NetListWriters:306 - Signal bus u1/m2/m2/Data<7 : 0> on block FPGA_ctrl is not reconstructed, because there are some missing bus signals. WARNING:NetListWriters:306 - Signal bus u1/m3/m2/AddrL_reg<3 : 0> on block FPGA_ctrl is not reconstructed, because there are some missing bus signals. WARNING:NetListWriters:306 - Signal bus u1/m3/m2/Data<4 : 0> on block FPGA_ctrl is not reconstructed, because there are some missing bus signals. WARNING:NetListWriters:306 - Signal bus u1/m4/m2/AddrL_reg<3 : 0> on block FPGA_ctrl is not reconstructed, because there are some missing bus signals. WARNING:NetListWriters:306 - Signal bus u1/m4/m2/Data<4 : 1> on block FPGA_ctrl is not reconstructed, because there are some missing bus signals. WARNING:NetListWriters:306 - Signal bus u1/m5/m2/AddrL_reg<3 : 0> on block FPGA_ctrl is not reconstructed, because there are some missing bus signals. WARNING:NetListWriters:306 - Signal bus u1/m5/m2/Data<7 : 1> on block FPGA_ctrl is not reconstructed, because there are some missing bus signals. WARNING:NetListWriters:306 - Signal bus u1/m6/a1/AddrL_reg<6 : 0> on block FPGA_ctrl is not reconstructed, because there are some missing bus signals. WARNING:NetListWriters:306 - Signal bus u1/m6/m/m2/AddrL_reg<3 : 0> on block FPGA_ctrl is not reconstructed, because there are some missing bus signals. WARNING:NetListWriters:306 - Signal bus u1/m7/m2/AddrL_reg<3 : 0> on block FPGA_ctrl is not reconstructed, because there are some missing bus signals. WARNING:NetListWriters:306 - Signal bus u3/RAwr_aH/AddrL_reg<3 : 0> on block FPGA_ctrl is not reconstructed, because there are some missing bus signals. WARNING:NetListWriters:306 - Signal bus u3/uDpack/u2/AddrL_reg<6 : 3> on block FPGA_ctrl is not reconstructed, because there are some missing bus signals. WARNING:NetListWriters:306 - Signal bus u3/uDpack/u2/Data<6 : 2> on block FPGA_ctrl is not reconstructed, because there are some missing bus signals. WARNING:NetListWriters:306 - Signal bus u3/uDpack/w/Data<6 : 2> on block FPGA_ctrl is not reconstructed, because there are some missing bus signals. WARNING:NetListWriters:306 - Signal bus u3/uSpack/uTxSt1/AddrL_reg<6 : 3> on block FPGA_ctrl is not reconstructed, because there are some missing bus signals. WARNING:NetListWriters:306 - Signal bus u3/uSpack/w/Data<6 : 0> on block FPGA_ctrl is not reconstructed, because there are some missing bus signals. WARNING:NetListWriters:306 - Signal bus u3/uTxS2/AddrL_reg<6 : 1> on block FPGA_ctrl is not reconstructed, because there are some missing bus signals. WARNING:NetListWriters:306 - Signal bus u3/uTxSt1/AddrL_reg<6 : 1> on block FPGA_ctrl is not reconstructed, because there are some missing bus signals. finished :Prep Writing EDIF netlist file FPGA_ctrl.edif ... ngc2edif: Total memory usage is 36696 kilobytes Release 11.2 - ngc2edif L.46 (nt) Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved. Reading design FPGA_ctrl.ngc ... WARNING:NetListWriters:298 - No output is written to FPGA_ctrl.xncf, ignored. Processing design ... Preping design's networks ... Preping design's macros ... WARNING:NetListWriters:306 - Signal bus SReg<18 : 0> on block DAC_shiftreg is not reconstructed, because there are some missing bus signals. WARNING:NetListWriters:306 - Signal bus Data<6 : 3> on block Reg8bit_NO26 is not reconstructed, because there are some missing bus signals. WARNING:NetListWriters:306 - Signal bus Data<6 : 0> on block Reg8bit_NO25 is not reconstructed, because there are some missing bus signals. WARNING:NetListWriters:306 - Signal bus Data<6 : 2> on block Reg8bit_NO24 is not reconstructed, because there are some missing bus signals. WARNING:NetListWriters:306 - Signal bus Data<6 : 3> on block Reg8bit_NO23 is not reconstructed, because there are some missing bus signals. WARNING:NetListWriters:306 - Signal bus Data<6 : 2> on block Reg8bit_NO22 is not reconstructed, because there are some missing bus signals. WARNING:NetListWriters:306 - Signal bus Data<6 : 1> on block Reg8bit_NO21 is not reconstructed, because there are some missing bus signals. WARNING:NetListWriters:306 - Signal bus Data<3 : 0> on block Reg8bit_NO20 is not reconstructed, because there are some missing bus signals. WARNING:NetListWriters:306 - Signal bus Data<6 : 1> on block Reg8bit_NO18 is not reconstructed, because there are some missing bus signals. WARNING:NetListWriters:306 - Signal bus Data<6 : 0> on block Reg8bit_NO13 is not reconstructed, because there are some missing bus signals. WARNING:NetListWriters:306 - Signal bus Data<3 : 0> on block Reg8bit_NO12 is not reconstructed, because there are some missing bus signals. WARNING:NetListWriters:306 - Signal bus Data<7 : 0> on block Reg8bit_NO10 is not reconstructed, because there are some missing bus signals. WARNING:NetListWriters:306 - Signal bus Data<3 : 0> on block Reg8bit_NO9 is not reconstructed, because there are some missing bus signals. WARNING:NetListWriters:306 - Signal bus Data<4 : 0> on block Reg8bit_NO8 is not reconstructed, because there are some missing bus signals. WARNING:NetListWriters:306 - Signal bus Data<3 : 0> on block Reg8bit_NO7 is not reconstructed, because there are some missing bus signals. WARNING:NetListWriters:306 - Signal bus Data<4 : 1> on block Reg8bit_NO6 is not reconstructed, because there are some missing bus signals. WARNING:NetListWriters:306 - Signal bus Data<3 : 0> on block Reg8bit_NO5 is not reconstructed, because there are some missing bus signals. WARNING:NetListWriters:306 - Signal bus Data<7 : 1> on block Reg8bit_NO4 is not reconstructed, because there are some missing bus signals. WARNING:NetListWriters:306 - Signal bus Data<3 : 0> on block Reg8bit_NO3 is not reconstructed, because there are some missing bus signals. WARNING:NetListWriters:306 - Signal bus Data<3 : 0> on block Reg8bit_NO1 is not reconstructed, because there are some missing bus signals. WARNING:NetListWriters:306 - Signal bus u2/m2/m2/AddrL_reg<3 : 0> on block FPGA_ctrl is not reconstructed, because there are some missing bus signals. WARNING:NetListWriters:306 - Signal bus u2/m2/m2/Data<7 : 0> on block FPGA_ctrl is not reconstructed, because there are some missing bus signals. WARNING:NetListWriters:306 - Signal bus u2/m3/m2/AddrL_reg<3 : 0> on block FPGA_ctrl is not reconstructed, because there are some missing bus signals. WARNING:NetListWriters:306 - Signal bus u2/m3/m2/Data<4 : 0> on block FPGA_ctrl is not reconstructed, because there are some missing bus signals. WARNING:NetListWriters:306 - Signal bus u2/m4/m2/AddrL_reg<3 : 0> on block FPGA_ctrl is not reconstructed, because there are some missing bus signals. WARNING:NetListWriters:306 - Signal bus u2/m4/m2/Data<4 : 1> on block FPGA_ctrl is not reconstructed, because there are some missing bus signals. WARNING:NetListWriters:306 - Signal bus u2/m5/m2/AddrL_reg<3 : 0> on block FPGA_ctrl is not reconstructed, because there are some missing bus signals. WARNING:NetListWriters:306 - Signal bus u2/m5/m2/Data<7 : 1> on block FPGA_ctrl is not reconstructed, because there are some missing bus signals. WARNING:NetListWriters:306 - Signal bus u2/m6/a1/AddrL_reg<6 : 0> on block FPGA_ctrl is not reconstructed, because there are some missing bus signals. WARNING:NetListWriters:306 - Signal bus u2/m6/m/m2/AddrL_reg<3 : 0> on block FPGA_ctrl is not reconstructed, because there are some missing bus signals. WARNING:NetListWriters:306 - Signal bus u2/m7/m2/AddrL_reg<3 : 0> on block FPGA_ctrl is not reconstructed, because there are some missing bus signals. WARNING:NetListWriters:306 - Signal bus u4/RAwr_aH/AddrL_reg<3 : 0> on block FPGA_ctrl is not reconstructed, because there are some missing bus signals. WARNING:NetListWriters:306 - Signal bus u4/uCheck/Addr_Madd__add0000_cy<5 : 3> on block FPGA_ctrl is not reconstructed, because there are some missing bus signals. WARNING:NetListWriters:306 - Signal bus u4/uDpack/u2/AddrL_reg<6 : 3> on block FPGA_ctrl is not reconstructed, because there are some missing bus signals. WARNING:NetListWriters:306 - Signal bus u4/uDpack/u2/Data<6 : 2> on block FPGA_ctrl is not reconstructed, because there are some missing bus signals. WARNING:NetListWriters:306 - Signal bus u4/uDpack/w/Data<6 : 2> on block FPGA_ctrl is not reconstructed, because there are some missing bus signals. WARNING:NetListWriters:306 - Signal bus u4/uSpack/uTxSt1/AddrL_reg<6 : 3> on block FPGA_ctrl is not reconstructed, because there are some missing bus signals. WARNING:NetListWriters:306 - Signal bus u4/uSpack/w/Data<6 : 0> on block FPGA_ctrl is not reconstructed, because there are some missing bus signals. WARNING:NetListWriters:306 - Signal bus u4/uTxS2/AddrL_reg<6 : 1> on block FPGA_ctrl is not reconstructed, because there are some missing bus signals. WARNING:NetListWriters:306 - Signal bus u4/uTxSt1/AddrL_reg<6 : 1> on block FPGA_ctrl is not reconstructed, because there are some missing bus signals. finished :Prep Writing EDIF netlist file FPGA_ctrl.edif ... ngc2edif: Total memory usage is 37720 kilobytes Release 11.2 - ngc2edif L.46 (nt) Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved. Reading design FPGA_ctrl.ngc ... WARNING:NetListWriters:298 - No output is written to FPGA_ctrl.xncf, ignored. Processing design ... Preping design's networks ... Preping design's macros ... WARNING:NetListWriters:306 - Signal bus SReg<18 : 0> on block DAC_shiftreg is not reconstructed, because there are some missing bus signals. WARNING:NetListWriters:306 - Signal bus Data<6 : 3> on block Reg8bit_NO25 is not reconstructed, because there are some missing bus signals. WARNING:NetListWriters:306 - Signal bus Data<6 : 2> on block Reg8bit_NO23 is not reconstructed, because there are some missing bus signals. WARNING:NetListWriters:306 - Signal bus Data<6 : 3> on block Reg8bit_NO22 is not reconstructed, because there are some missing bus signals. WARNING:NetListWriters:306 - Signal bus Data<3 : 0> on block Reg8bit_NO20 is not reconstructed, because there are some missing bus signals. WARNING:NetListWriters:306 - Signal bus Data<6 : 1> on block Reg8bit_NO19 is not reconstructed, because there are some missing bus signals. WARNING:NetListWriters:306 - Signal bus Data<3 : 0> on block Reg8bit_NO18 is not reconstructed, because there are some missing bus signals. WARNING:NetListWriters:306 - Signal bus Data<6 : 1> on block Reg8bit_NO16 is not reconstructed, because there are some missing bus signals. WARNING:NetListWriters:306 - Signal bus Data<6 : 0> on block Reg8bit_NO11 is not reconstructed, because there are some missing bus signals. WARNING:NetListWriters:306 - Signal bus Data<7 : 0> on block Reg8bit_NO8 is not reconstructed, because there are some missing bus signals. WARNING:NetListWriters:306 - Signal bus Data<4 : 0> on block Reg8bit_NO6 is not reconstructed, because there are some missing bus signals. WARNING:NetListWriters:306 - Signal bus Data<4 : 1> on block Reg8bit_NO4 is not reconstructed, because there are some missing bus signals. WARNING:NetListWriters:306 - Signal bus Data<3 : 0> on block Reg8bit_NO2 is not reconstructed, because there are some missing bus signals. WARNING:NetListWriters:306 - Signal bus u2/m2/m2/Data<7 : 0> on block FPGA_ctrl is not reconstructed, because there are some missing bus signals. WARNING:NetListWriters:306 - Signal bus u2/m3/m2/Data<4 : 0> on block FPGA_ctrl is not reconstructed, because there are some missing bus signals. WARNING:NetListWriters:306 - Signal bus u2/m4/m2/Data<4 : 1> on block FPGA_ctrl is not reconstructed, because there are some missing bus signals. WARNING:NetListWriters:306 - Signal bus u2/m6/a1/AddrL_reg<6 : 0> on block FPGA_ctrl is not reconstructed, because there are some missing bus signals. WARNING:NetListWriters:306 - Signal bus u2/m7/m2/Data<3 : 0> on block FPGA_ctrl is not reconstructed, because there are some missing bus signals. WARNING:NetListWriters:306 - Signal bus u4/RAwrAddr<12 : 0> on block FPGA_ctrl is not reconstructed, because there are some missing bus signals. WARNING:NetListWriters:306 - Signal bus u4/RAwr_aH/AddrL_reg<3 : 0> on block FPGA_ctrl is not reconstructed, because there are some missing bus signals. WARNING:NetListWriters:306 - Signal bus u4/uCheck1/Cnt_Madd__add0000_cy<5 : 3> on block FPGA_ctrl is not reconstructed, because there are some missing bus signals. WARNING:NetListWriters:306 - Signal bus u4/uCheck2/ra1/AddrL_reg<3 : 0> on block FPGA_ctrl is not reconstructed, because there are some missing bus signals. WARNING:NetListWriters:306 - Signal bus u4/uDpack/u2/AddrL_reg<6 : 3> on block FPGA_ctrl is not reconstructed, because there are some missing bus signals. WARNING:NetListWriters:306 - Signal bus u4/uDpack/u2/Data<6 : 2> on block FPGA_ctrl is not reconstructed, because there are some missing bus signals. WARNING:NetListWriters:306 - Signal bus u4/uSpack/uTxSt1/AddrL_reg<6 : 3> on block FPGA_ctrl is not reconstructed, because there are some missing bus signals. WARNING:NetListWriters:306 - Signal bus u4/uTxS2/AddrL_reg<6 : 1> on block FPGA_ctrl is not reconstructed, because there are some missing bus signals. WARNING:NetListWriters:306 - Signal bus u4/uTxSt1/AddrL_reg<6 : 1> on block FPGA_ctrl is not reconstructed, because there are some missing bus signals. finished :Prep Writing EDIF netlist file FPGA_ctrl.edif ... ngc2edif: Total memory usage is 37720 kilobytes Release 11.3 - ngc2edif L.57 (nt) Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved. Reading design FPGA_ctrl.ngc ... WARNING:NetListWriters:298 - No output is written to FPGA_ctrl.xncf, ignored. Processing design ... Preping design's networks ... Preping design's macros ... WARNING:NetListWriters:306 - Signal bus SReg<18 : 0> on block DAC_shiftreg is not reconstructed, because there are some missing bus signals. WARNING:NetListWriters:306 - Signal bus Data<6 : 3> on block Reg8bit_NO25 is not reconstructed, because there are some missing bus signals. WARNING:NetListWriters:306 - Signal bus Data<6 : 2> on block Reg8bit_NO23 is not reconstructed, because there are some missing bus signals. WARNING:NetListWriters:306 - Signal bus Data<6 : 3> on block Reg8bit_NO22 is not reconstructed, because there are some missing bus signals. WARNING:NetListWriters:306 - Signal bus Data<3 : 0> on block Reg8bit_NO20 is not reconstructed, because there are some missing bus signals. WARNING:NetListWriters:306 - Signal bus Data<6 : 1> on block Reg8bit_NO19 is not reconstructed, because there are some missing bus signals. WARNING:NetListWriters:306 - Signal bus Data<3 : 0> on block Reg8bit_NO18 is not reconstructed, because there are some missing bus signals. WARNING:NetListWriters:306 - Signal bus Data<6 : 1> on block Reg8bit_NO16 is not reconstructed, because there are some missing bus signals. WARNING:NetListWriters:306 - Signal bus Data<6 : 0> on block Reg8bit_NO11 is not reconstructed, because there are some missing bus signals. WARNING:NetListWriters:306 - Signal bus Data<7 : 0> on block Reg8bit_NO8 is not reconstructed, because there are some missing bus signals. WARNING:NetListWriters:306 - Signal bus Data<4 : 0> on block Reg8bit_NO6 is not reconstructed, because there are some missing bus signals. WARNING:NetListWriters:306 - Signal bus Data<4 : 1> on block Reg8bit_NO4 is not reconstructed, because there are some missing bus signals. WARNING:NetListWriters:306 - Signal bus Data<3 : 0> on block Reg8bit_NO2 is not reconstructed, because there are some missing bus signals. WARNING:NetListWriters:306 - Signal bus u2/m2/m2/Data<7 : 0> on block FPGA_ctrl is not reconstructed, because there are some missing bus signals. WARNING:NetListWriters:306 - Signal bus u2/m3/m2/Data<4 : 0> on block FPGA_ctrl is not reconstructed, because there are some missing bus signals. WARNING:NetListWriters:306 - Signal bus u2/m4/m2/Data<4 : 1> on block FPGA_ctrl is not reconstructed, because there are some missing bus signals. WARNING:NetListWriters:306 - Signal bus u2/m6/a1/AddrL_reg<6 : 0> on block FPGA_ctrl is not reconstructed, because there are some missing bus signals. WARNING:NetListWriters:306 - Signal bus u2/m7/m2/Data<3 : 0> on block FPGA_ctrl is not reconstructed, because there are some missing bus signals. WARNING:NetListWriters:306 - Signal bus u4/RAwrAddr<12 : 0> on block FPGA_ctrl is not reconstructed, because there are some missing bus signals. WARNING:NetListWriters:306 - Signal bus u4/RAwr_aH/AddrL_reg<3 : 0> on block FPGA_ctrl is not reconstructed, because there are some missing bus signals. WARNING:NetListWriters:306 - Signal bus u4/uCheck1/Cnt_Madd__add0000_cy<5 : 3> on block FPGA_ctrl is not reconstructed, because there are some missing bus signals. WARNING:NetListWriters:306 - Signal bus u4/uCheck2/ra1/AddrL_reg<3 : 0> on block FPGA_ctrl is not reconstructed, because there are some missing bus signals. WARNING:NetListWriters:306 - Signal bus u4/uDpack/u2/AddrL_reg<6 : 3> on block FPGA_ctrl is not reconstructed, because there are some missing bus signals. WARNING:NetListWriters:306 - Signal bus u4/uDpack/u2/Data<6 : 2> on block FPGA_ctrl is not reconstructed, because there are some missing bus signals. WARNING:NetListWriters:306 - Signal bus u4/uSpack/uTxSt1/AddrL_reg<6 : 3> on block FPGA_ctrl is not reconstructed, because there are some missing bus signals. WARNING:NetListWriters:306 - Signal bus u4/uTxS2/AddrL_reg<6 : 1> on block FPGA_ctrl is not reconstructed, because there are some missing bus signals. WARNING:NetListWriters:306 - Signal bus u4/uTxSt1/AddrL_reg<6 : 1> on block FPGA_ctrl is not reconstructed, because there are some missing bus signals. finished :Prep Writing EDIF netlist file FPGA_ctrl.edif ... ngc2edif: Total memory usage is 36684 kilobytes Release 11.3 - ngc2edif L.57 (nt) Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved. Reading design FPGA_ctrl.ngc ... WARNING:NetListWriters:298 - No output is written to FPGA_ctrl.xncf, ignored. Processing design ... Preping design's networks ... Preping design's macros ... WARNING:NetListWriters:306 - Signal bus u4/RAwrAddr<12 : 0> on block FPGA_ctrl is not reconstructed, because there are some missing bus signals. WARNING:NetListWriters:306 - Signal bus u4/uCheck1/Cnt_Madd__add0000_cy<5 : 3> on block FPGA_ctrl is not reconstructed, because there are some missing bus signals. WARNING:NetListWriters:306 - Signal bus u4/uSpack/Data<6 : 0> on block FPGA_ctrl is not reconstructed, because there are some missing bus signals. finished :Prep Writing EDIF netlist file FPGA_ctrl.edif ... ngc2edif: Total memory usage is 36684 kilobytes Release 11.3 - ngc2edif L.57 (nt) Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved. Reading design FPGA_ctrl.ngc ... WARNING:NetListWriters:298 - No output is written to FPGA_ctrl.xncf, ignored. Processing design ... Preping design's networks ... Preping design's macros ... WARNING:NetListWriters:306 - Signal bus u4/RAwrAddr<12 : 0> on block FPGA_ctrl is not reconstructed, because there are some missing bus signals. WARNING:NetListWriters:306 - Signal bus u4/uCheck1/Cnt_Madd__add0000_cy<5 : 3> on block FPGA_ctrl is not reconstructed, because there are some missing bus signals. WARNING:NetListWriters:306 - Signal bus u4/uSpack/Data<6 : 0> on block FPGA_ctrl is not reconstructed, because there are some missing bus signals. finished :Prep Writing EDIF netlist file FPGA_ctrl.edif ... ngc2edif: Total memory usage is 36684 kilobytes Release 11.3 - ngc2edif L.57 (nt) Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved. Reading design FPGA_ctrl.ngc ... WARNING:NetListWriters:298 - No output is written to FPGA_ctrl.xncf, ignored. Processing design ... Preping design's networks ... Preping design's macros ... finished :Prep Writing EDIF netlist file FPGA_ctrl.edif ... ngc2edif: Total memory usage is 35660 kilobytes Release 11.3 - ngc2edif L.57 (nt) Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved. Reading design FPGA_ctrl.ngc ... WARNING:NetListWriters:298 - No output is written to FPGA_ctrl.xncf, ignored. Processing design ... Preping design's networks ... Preping design's macros ... WARNING:NetListWriters:306 - Signal bus u4/RAwrAddr<12 : 0> on block FPGA_ctrl is not reconstructed, because there are some missing bus signals. WARNING:NetListWriters:306 - Signal bus u4/uCheck1/Cnt_Madd__add0000_cy<5 : 3> on block FPGA_ctrl is not reconstructed, because there are some missing bus signals. finished :Prep Writing EDIF netlist file FPGA_ctrl.edif ... ngc2edif: Total memory usage is 36684 kilobytes Release 11.3 - ngc2edif L.57 (nt) Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved. Reading design FPGA_ctrl.ngc ... WARNING:NetListWriters:298 - No output is written to FPGA_ctrl.xncf, ignored. Processing design ... Preping design's networks ... Preping design's macros ... WARNING:NetListWriters:306 - Signal bus u4/RAwrAddr<12 : 0> on block FPGA_ctrl is not reconstructed, because there are some missing bus signals. WARNING:NetListWriters:306 - Signal bus u4/uCheck1/Cnt_Madd__add0000_cy<5 : 3> on block FPGA_ctrl is not reconstructed, because there are some missing bus signals. finished :Prep Writing EDIF netlist file FPGA_ctrl.edif ... ngc2edif: Total memory usage is 36684 kilobytes Release 11.3 - ngc2edif L.57 (nt) Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved. Reading design FPGA_ctrl.ngc ... WARNING:NetListWriters:298 - No output is written to FPGA_ctrl.xncf, ignored. Processing design ... Preping design's networks ... Preping design's macros ... WARNING:NetListWriters:306 - Signal bus u0/Data<5 : 0> on block FPGA_ctrl is not reconstructed, because there are some missing bus signals. WARNING:NetListWriters:306 - Signal bus u0/Data_INT1<2 : 0> on block FPGA_ctrl is not reconstructed, because there are some missing bus signals. WARNING:NetListWriters:306 - Signal bus u0/r1/Data<5 : 0> on block FPGA_ctrl is not reconstructed, because there are some missing bus signals. WARNING:NetListWriters:306 - Signal bus u0/r2/Data<3 : 0> on block FPGA_ctrl is not reconstructed, because there are some missing bus signals. finished :Prep Writing EDIF netlist file FPGA_ctrl.edif ... ngc2edif: Total memory usage is 36684 kilobytes Release 11.3 - ngc2edif L.57 (nt) Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved. Reading design FPGA_ctrl.ngc ... WARNING:NetListWriters:298 - No output is written to FPGA_ctrl.xncf, ignored. Processing design ... Preping design's networks ... Preping design's macros ... WARNING:NetListWriters:306 - Signal bus u0/Data<5 : 0> on block FPGA_ctrl is not reconstructed, because there are some missing bus signals. WARNING:NetListWriters:306 - Signal bus u0/Data_INT1<2 : 0> on block FPGA_ctrl is not reconstructed, because there are some missing bus signals. WARNING:NetListWriters:306 - Signal bus u0/r1/Data<5 : 0> on block FPGA_ctrl is not reconstructed, because there are some missing bus signals. WARNING:NetListWriters:306 - Signal bus u0/r2/Data<3 : 0> on block FPGA_ctrl is not reconstructed, because there are some missing bus signals. finished :Prep Writing EDIF netlist file FPGA_ctrl.edif ... ngc2edif: Total memory usage is 36684 kilobytes Release 11.3 - ngc2edif L.57 (nt) Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved. Reading design FPGA_ctrl.ngc ... WARNING:NetListWriters:298 - No output is written to FPGA_ctrl.xncf, ignored. Processing design ... Preping design's networks ... Preping design's macros ... WARNING:NetListWriters:306 - Signal bus u0/Data<5 : 0> on block FPGA_ctrl is not reconstructed, because there are some missing bus signals. WARNING:NetListWriters:306 - Signal bus u0/Data_INT1<2 : 0> on block FPGA_ctrl is not reconstructed, because there are some missing bus signals. WARNING:NetListWriters:306 - Signal bus u0/r1/Data<5 : 0> on block FPGA_ctrl is not reconstructed, because there are some missing bus signals. WARNING:NetListWriters:306 - Signal bus u0/r2/Data<3 : 0> on block FPGA_ctrl is not reconstructed, because there are some missing bus signals. finished :Prep Writing EDIF netlist file FPGA_ctrl.edif ... ngc2edif: Total memory usage is 36684 kilobytes