INFO: [HD-Application 1] Opened log file C:\Work\GlueX\Tagger\Electronics\FPGA\TotalTest\planAhead.log
INFO: [HD-Application 2] Opened journal file C:\Work\GlueX\Tagger\Electronics\FPGA\TotalTest\planAhead.jou
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# PlanAhead v11.1
# Build 44534 by hdbuild on Thu Mar  5 11:02:58 PST 2009
# Start of session at: 6/24/09 1:03:53 PM
# Process ID: 3756
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INFO: [HD-RTPRIM 0] Parsing template file 'C:\Xilinx\11.1\ISE\data\projnav\templates\verilog.xml'
INFO: [HD-RTPRIM 1] Finished parsing template file 'C:\Xilinx\11.1\ISE\data\projnav\templates\verilog.xml'
INFO: [HD-RTPRIM 0] Parsing template file 'C:\Xilinx\11.1\ISE\data\projnav\templates\vhdl.xml'
INFO: [HD-RTPRIM 1] Finished parsing template file 'C:\Xilinx\11.1\ISE\data\projnav\templates\vhdl.xml'
INFO: [HD-RTPRIM 0] Parsing template file 'C:\Xilinx\11.1\ISE\data\projnav\templates\ucf.xml'
INFO: [HD-RTPRIM 1] Finished parsing template file 'C:\Xilinx\11.1\ISE\data\projnav\templates\ucf.xml'
Command> source C:/Work/GlueX/Tagger/Electronics/FPGA/TotalTest/pa.fromNetlist.tcl
# hdi::project new -name TotalTest -dir C:/Work/GlueX/Tagger/Electronics/FPGA/TotalTest/patmp -netlist FPGA_ctrl.ngc -search_path  {C:/Work/GlueX/Tagger/Electronics/FPGA/TotalTest} 
INFO: [HD-EDIFIN 0] Parsing Edif File '.\.HDI-PlanAhead-3756-TOSHIBA-Laptop\ngc2edif\FPGA_ctrl.edif'
INFO: [HD-EDIFIN 1] Finished Parsing Edif File '.\.HDI-PlanAhead-3756-TOSHIBA-Laptop\ngc2edif\FPGA_ctrl.edif'
WARN: [HD-NETLIST 3] Netlist is not ideal for floorplanning, since the cellview 'FPGA_ctrl' defined in file 'FPGA_ctrl.ngc' contains large number of primitives.
# hdi::project setArch -name TotalTest -arch spartan3a
# hdi::param set -name project.pinAheadLayout -bvalue yes
# hdi::param set -name project.paUcfFile -svalue FPGA_ctrl.ucf
# hdi::floorplan new -name floorplan_1 -part xc3s50avq100-4 -project TotalTest
INFO: [HD-ArchReader 14] Reading macro library C:\Xilinx\11.1\PlanAhead\parts\xilinx\spartan3a\hd_int_macros.edn
INFO: [HD-EDIFIN 0] Parsing Edif File 'C:\Xilinx\11.1\PlanAhead\parts\xilinx\spartan3a\hd_int_macros.edn'
INFO: [HD-EDIFIN 1] Finished Parsing Edif File 'C:\Xilinx\11.1\PlanAhead\parts\xilinx\spartan3a\hd_int_macros.edn'
INFO: [HD-ArchReader 7] Loading clock regions from C:\Xilinx\11.1\PlanAhead\parts\xilinx\spartan3a\3s50a\ClockRegion.xml
INFO: [HD-ArchReader 8] Loading clock buffers from C:\Xilinx\11.1\PlanAhead\parts\xilinx\spartan3a\3s50a\ClockBuffers.xml
INFO: [HD-ArchReader 3] Loading package from C:\Xilinx\11.1\PlanAhead\parts\xilinx\spartan3a\3s50a\vq100\Package.xml
INFO: [HD-ArchReader 4] Loading io standards from C:\Xilinx\11.1\PlanAhead\parts\xilinx\spartan3a\IOStandards.xml
INFO: [HD-ArchReader 5] Loading pkg sso from C:\Xilinx\11.1\PlanAhead\parts\xilinx\spartan3a\3s50a\vq100\SSORules.xml
INFO: [HD-GDRC 0] Loading list of drcs for the architecture : C:\Xilinx\11.1\PlanAhead\parts\xilinx\spartan3a\drc.xml
# hdi::pconst import -project TotalTest -floorplan floorplan_1 -file FPGA_ctrl.ucf
INFO: [HD-UCFReader 0] Parsing UCF File : FPGA_ctrl.ucf
INFO: [HD-UCFReader 1] Finished Parsing UCF File : FPGA_ctrl.ucf
Command> hdi::port configure -project TotalTest -floorplan floorplan_1 -names Eth_iRst -ioStd LVCMOS33 -defaultDriveStrength yes -defaultSlewType yes -pullType PULLUP
Command> hdi::floorplan save -name floorplan_1 -project TotalTest
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# End of session at: 6/24/09 1:05:18 PM
# Process ID: 3756
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