Release 11.3 - netgen L.57 (nt)
Copyright (c) 1995-2009 Xilinx, Inc.  All rights reserved.

Command Line: netgen -intstyle ise -ar Structure -tm FPGA_ctrl -w -dir
netgen/synthesis -ofmt vhdl -sim FPGA_ctrl.ngc FPGA_ctrl_synthesis.vhd  

Reading design 'FPGA_ctrl.ngc' ...
Flattening design ...
Processing design ... 
  Preping design's networks ...
  Preping design's macros ...
Writing VHDL netlist 'E:\igors
work\GlueX\Tagger\Electronics\FPGA\TotalTest\netgen\synthesis\FPGA_ctrl_synthesi
s.vhd' ...
INFO:NetListWriters:635 - The generated VHDL netlist contains Xilinx UNISIM
   simulation primitives and has to be used with UNISIM library for correct
   compilation and simulation. 
INFO:NetListWriters:703 - Setup Simulation - To perform a setup simulation,
   specify values in the Maximum (MAX) field with the following command line
   modifier:  -SDFMAX
INFO:NetListWriters:702 - Hold Simulation - To perform the most accurate hold
   simulation, specify values in the Minimum (MIN) field with the following
   command line modifier:  -SDFMIN
INFO:NetListWriters:665 - For more information on how to pass the SDF switches
   to the simulator, see your Simulator tool documentation.
Number of warnings: 0
Number of info messages: 4
Total memory usage is 70652 kilobytes