Release 11.3 - Bitgen L.57 (nt)
Copyright (c) 1995-2009 Xilinx, Inc.  All rights reserved.
Loading device for application Rf_Device from file '3s50a.nph' in environment
E:\Xilinx\11.1\ISE.
   "FPGA_ctrl" is an NCD, version 3.2, device xc3s50a, package vq100, speed -4
Opened constraints file FPGA_ctrl.pcf.

Mon Oct 21 15:50:23 2013

E:\Xilinx\11.1\ISE\bin\nt\unwrapped\bitgen.exe -intstyle ise -w -g DebugBitstream:No -g Binary:no -g CRC:Enable -g Reset_on_err:No -g ConfigRate:33 -g ProgPin:PullUp -g DonePin:PullUp -g TckPin:PullUp -g TdiPin:PullUp -g TdoPin:PullUp -g TmsPin:PullUp -g UnusedPin:PullDown -g UserID:0xFFFFFFFF -g StartUpClk:CClk -g DONE_cycle:4 -g GTS_cycle:5 -g GWE_cycle:6 -g LCK_cycle:NoWait -g Security:None -g DonePipe:No -g DriveDone:Yes -g en_sw_gsr:No -g en_porb:Yes -g drive_awake:No -g sw_clk:Startupclk -g sw_gwe_cycle:5 -g sw_gts_cycle:4 FPGA_ctrl.ncd 

WARNING:Bitgen:101 - There is a STARTUP component with a signal on the CLK pin
   but StartupClk is Cclk.
Summary of Bitgen Options:
+----------------------+----------------------+
| Option Name          | Current Setting      |
+----------------------+----------------------+
| Compress             | (Not Specified)*     |
+----------------------+----------------------+
| Readback             | (Not Specified)*     |
+----------------------+----------------------+
| CRC                  | Enable**             |
+----------------------+----------------------+
| DebugBitstream       | No**                 |
+----------------------+----------------------+
| ConfigRate           | 33                   |
+----------------------+----------------------+
| StartupClk           | Cclk**               |
+----------------------+----------------------+
| DonePin              | Pullup**             |
+----------------------+----------------------+
| ProgPin              | Pullup**             |
+----------------------+----------------------+
| TckPin               | Pullup**             |
+----------------------+----------------------+
| TdiPin               | Pullup**             |
+----------------------+----------------------+
| TdoPin               | Pullup**             |
+----------------------+----------------------+
| TmsPin               | Pullup**             |
+----------------------+----------------------+
| UnusedPin            | Pulldown**           |
+----------------------+----------------------+
| GWE_cycle            | 6**                  |
+----------------------+----------------------+
| GTS_cycle            | 5**                  |
+----------------------+----------------------+
| LCK_cycle            | NoWait**             |
+----------------------+----------------------+
| DONE_cycle           | 4**                  |
+----------------------+----------------------+
| Persist              | No*                  |
+----------------------+----------------------+
| DriveDone            | Yes                  |
+----------------------+----------------------+
| DonePipe             | No**                 |
+----------------------+----------------------+
| Security             | None**               |
+----------------------+----------------------+
| UserID               | 0xFFFFFFFF**         |
+----------------------+----------------------+
| ActivateGclk         | No*                  |
+----------------------+----------------------+
| ActiveReconfig       | No*                  |
+----------------------+----------------------+
| PartialMask0         | (Not Specified)*     |
+----------------------+----------------------+
| PartialMask1         | (Not Specified)*     |
+----------------------+----------------------+
| PartialMask2         | (Not Specified)*     |
+----------------------+----------------------+
| PartialGclk          | (Not Specified)*     |
+----------------------+----------------------+
| PartialLeft          | (Not Specified)*     |
+----------------------+----------------------+
| PartialRight         | (Not Specified)*     |
+----------------------+----------------------+
| drive_awake          | No**                 |
+----------------------+----------------------+
| Reset_on_err         | No**                 |
+----------------------+----------------------+
| suspend_filter       | Yes*                 |
+----------------------+----------------------+
| en_sw_gsr            | No**                 |
+----------------------+----------------------+
| en_suspend           | No*                  |
+----------------------+----------------------+
| en_porb              | Yes**                |
+----------------------+----------------------+
| sw_clk               | Startupclk**         |
+----------------------+----------------------+
| sw_gwe_cycle         | 5**                  |
+----------------------+----------------------+
| sw_gts_cycle         | 4**                  |
+----------------------+----------------------+
| glutmask             | Yes*                 |
+----------------------+----------------------+
| next_config_addr     | 0x00000000*          |
+----------------------+----------------------+
| next_config_new_mode | No*                  |
+----------------------+----------------------+
| next_config_boot_mode | 001*                 |
+----------------------+----------------------+
| next_config_register_write | Enable*              |
+----------------------+----------------------+
| ICAP_Enable          | Auto*                |
+----------------------+----------------------+
| IEEE1532             | No*                  |
+----------------------+----------------------+
| Binary               | No**                 |
+----------------------+----------------------+
 *  Default setting.
 ** The specified setting matches the default setting.

Running DRC.
WARNING:PhysDesignRules:372 - Gated clock. Clock net Rst_int is sourced by a
   combinatorial pin. This is not good design practice. Use the CE pin to
   control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net uXmit/uSpack/Done_Word is
   sourced by a combinatorial pin. This is not good design practice. Use the CE
   pin to control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net
   uXmit/uDpack/w/C_0_0_not0000 is sourced by a combinatorial pin. This is not
   good design practice. Use the CE pin to control the loading of data into the
   flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net uXmit/uDpack/Done_Word is
   sourced by a combinatorial pin. This is not good design practice. Use the CE
   pin to control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net ser_Go_uINT is sourced by a
   combinatorial pin. This is not good design practice. Use the CE pin to
   control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net uResS/Done_Byte is sourced
   by a combinatorial pin. This is not good design practice. Use the CE pin to
   control the loading of data into the flip-flop.
DRC detected 0 errors and 6 warnings.  Please see the previously displayed
individual error or warning messages for more details.
Creating bit map...
Saving bit stream in "fpga_ctrl.bit".
Bitstream generation is complete.