0a 10 00 0 28 40 Reset_hard: Done holding Eth. Ctrl. reset pin ------------ 50 80 IRQ: INT0 0001_0000 - Oscillator init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 29 41 Reset_hard: Done! Wrote to all Eth. Ctrl. config. regs 24 36 state: 100 - Querier (of Temp. and ADC) 00 0 00 0 00 0 ff 255 ff 255 ff 255 00 0 25 37 state: 101 - Transmitter: S-Packet 44 68 IRQ: INT0 0000_0100 - Packet transmitted 0e 14 00 0 28 40 Reset_hard: Done holding Eth. Ctrl. reset pin ------------ 50 80 IRQ: INT0 0001_0000 - Oscillator init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 29 41 Reset_hard: Done! Wrote to all Eth. Ctrl. config. regs 24 36 state: 100 - Querier (of Temp. and ADC) ff 255 ff 255 ff 255 ff 255 ff 255 ff 255 ff 255 25 37 state: 101 - Transmitter: S-Packet 44 68 IRQ: INT0 0000_0100 - Packet transmitted 0e 14 00 0 28 40 Reset_hard: Done holding Eth. Ctrl. reset pin ------------ 50 80 IRQ: INT0 0001_0000 - Oscillator init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 29 41 Reset_hard: Done! Wrote to all Eth. Ctrl. config. regs 24 36 state: 100 - Querier (of Temp. and ADC) 00 0 ff 255 ff 255 ff 255 ff 255 ff 255 ff 255 ff 255 41 65 IRQ: INT0 0000_0001 - Packet received 0e 14 00 0 28 40 Reset_hard: Done holding Eth. Ctrl. reset pin ------------ 50 80 IRQ: INT0 0001_0000 - Oscillator init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 29 41 Reset_hard: Done! Wrote to all Eth. Ctrl. config. regs 24 36 state: 100 - Querier (of Temp. and ADC) ff 255 00 0 00 0 ff 255 00 0 ff 255 00 0 ff 255 44 68 IRQ: INT0 0000_0100 - Packet transmitted 0e 14 00 0 28 40 Reset_hard: Done holding Eth. Ctrl. reset pin ------------ 50 80 IRQ: INT0 0001_0000 - Oscillator init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 29 41 Reset_hard: Done! Wrote to all Eth. Ctrl. config. regs 24 36 state: 100 - Querier (of Temp. and ADC) ff 255 00 0 ff 255 ff 255 ff 255 ff 255 ff 255 25 37 state: 101 - Transmitter: S-Packet 44 68 IRQ: INT0 0000_0100 - Packet transmitted 0e 14 00 0 28 40 Reset_hard: Done holding Eth. Ctrl. reset pin ------------ 50 80 IRQ: INT0 0001_0000 - Oscillator init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 29 41 Reset_hard: Done! Wrote to all Eth. Ctrl. config. regs 24 36 state: 100 - Querier (of Temp. and ADC) ff 255 ff 255 ff 255 ff 255 00 0 ff 255 00 0 ff 255 41 65 IRQ: INT0 0000_0001 - Packet received 0e 14 00 0 28 40 Reset_hard: Done holding Eth. Ctrl. reset pin ------------ 50 80 IRQ: INT0 0001_0000 - Oscillator init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 29 41 Reset_hard: Done! Wrote to all Eth. Ctrl. config. regs 24 36 state: 100 - Querier (of Temp. and ADC) 00 0 00 0 ff 255 ff 255 00 0 ff 255 00 0 ff 255 44 68 IRQ: INT0 0000_0100 - Packet transmitted 0e 14 00 0 28 40 Reset_hard: Done holding Eth. Ctrl. reset pin ------------ 50 80 IRQ: INT0 0001_0000 - Oscillator init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 29 41 Reset_hard: Done! Wrote to all Eth. Ctrl. config. regs 24 36 state: 100 - Querier (of Temp. and ADC) 00 0 ff 255 00 0 ff 255 00 0 ff 255 ff 255 ff 255 44 68 IRQ: INT0 0000_0100 - Packet transmitted 0e 14 00 0 28 40 Reset_hard: Done holding Eth. Ctrl. reset pin ------------ 50 80 IRQ: INT0 0001_0000 - Oscillator init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 29 41 Reset_hard: Done! Wrote to all Eth. Ctrl. config. regs 24 36 state: 100 - Querier (of Temp. and ADC) ff 255 ff 255 00 0 ff 255 00 0 ff 255 ff 255 25 37 state: 101 - Transmitter: S-Packet 44 68 IRQ: INT0 0000_0100 - Packet transmitted 0e 14 00 0 28 40 Reset_hard: Done holding Eth. Ctrl. reset pin ------------ 50 80 IRQ: INT0 0001_0000 - Oscillator init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 29 41 Reset_hard: Done! Wrote to all Eth. Ctrl. config. regs 24 36 state: 100 - Querier (of Temp. and ADC) 00 0 00 0 ff 255 00 0 00 0 ff 255 ff 255 25 37 state: 101 - Transmitter: S-Packet 44 68 IRQ: INT0 0000_0100 - Packet transmitted 0e 14 00 0 28 40 Reset_hard: Done holding Eth. Ctrl. reset pin ------------ 50 80 IRQ: INT0 0001_0000 - Oscillator init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 29 41 Reset_hard: Done! Wrote to all Eth. Ctrl. config. regs 24 36 state: 100 - Querier (of Temp. and ADC) 00 0 ff 255 00 0 ff 255 ff 255 ff 255 00 0 ff 255 44 68 IRQ: INT0 0000_0100 - Packet transmitted 0e 14 00 0 28 40 Reset_hard: Done holding Eth. Ctrl. reset pin ------------ 50 80 IRQ: INT0 0001_0000 - Oscillator init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 29 41 Reset_hard: Done! Wrote to all Eth. Ctrl. config. regs 24 36 state: 100 - Querier (of Temp. and ADC) 00 0 00 0 ff 255 ff 255 ff 255 ff 255 ff 255 25 37 state: 101 - Transmitter: S-Packet 44 68 IRQ: INT0 0000_0100 - Packet transmitted 0e 14 00 0 28 40 Reset_hard: Done holding Eth. Ctrl. reset pin ------------ 50 80 IRQ: INT0 0001_0000 - Oscillator init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 29 41 Reset_hard: Done! Wrote to all Eth. Ctrl. config. regs 24 36 state: 100 - Querier (of Temp. and ADC) ff 255 ff 255 00 0 ff 255 ff 255 ff 255 00 0 ff 255 44 68 IRQ: INT0 0000_0100 - Packet transmitted 0e 14 00 0 28 40 Reset_hard: Done holding Eth. Ctrl. reset pin ------------ 50 80 IRQ: INT0 0001_0000 - Oscillator init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 29 41 Reset_hard: Done! Wrote to all Eth. Ctrl. config. regs 24 36 state: 100 - Querier (of Temp. and ADC) ff 255 ff 255 00 0 ff 255 ff 255 ff 255 00 0 25 37 state: 101 - Transmitter: S-Packet 44 68 IRQ: INT0 0000_0100 - Packet transmitted 0e 14 00 0 28 40 Reset_hard: Done holding Eth. Ctrl. reset pin ------------ 50 80 IRQ: INT0 0001_0000 - Oscillator init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 29 41 Reset_hard: Done! Wrote to all Eth. Ctrl. config. regs 24 36 state: 100 - Querier (of Temp. and ADC) ff 255 ff 255 00 0 ff 255 ff 255 ff 255 ff 255 25 37 state: 101 - Transmitter: S-Packet 44 68 IRQ: INT0 0000_0100 - Packet transmitted 0e 14 00 0 28 40 Reset_hard: Done holding Eth. Ctrl. reset pin ------------ 50 80 IRQ: INT0 0001_0000 - Oscillator init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 29 41 Reset_hard: Done! Wrote to all Eth. Ctrl. config. regs 24 36 state: 100 - Querier (of Temp. and ADC) ff 255 ff 255 ff 255 ff 255 ff 255 ff 255 00 0 25 37 state: 101 - Transmitter: S-Packet 44 68 IRQ: INT0 0000_0100 - Packet transmitted 0e 14 00 0 28 40 Reset_hard: Done holding Eth. Ctrl. reset pin ------------ 50 80 IRQ: INT0 0001_0000 - Oscillator init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 29 41 Reset_hard: Done! Wrote to all Eth. Ctrl. config. regs 24 36 state: 100 - Querier (of Temp. and ADC) 00 0 ff 255 00 0 ff 255 ff 255 ff 255 00 0 25 37 state: 101 - Transmitter: S-Packet 44 68 IRQ: INT0 0000_0100 - Packet transmitted 0e 14 00 0 28 40 Reset_hard: Done holding Eth. Ctrl. reset pin ------------ 50 80 IRQ: INT0 0001_0000 - Oscillator init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 29 41 Reset_hard: Done! Wrote to all Eth. Ctrl. config. regs 24 36 state: 100 - Querier (of Temp. and ADC) 00 0 00 0 ff 255 ff 255 ff 255 ff 255 ff 255 25 37 state: 101 - Transmitter: S-Packet 2d 45 Transmitter: Beginning Tx status check... 00 0 0x57 TxEnd: 0000 0000 40 64 0x58 0100 0000 00 0 0x59 TxStart: 0000 0000 40 64 0x5a 0100 0000 f1 241 0x5b ->0x78-Phy1111 0001 00 0 0x5c TxSta6: 0000 0000 00 0 0x5d 0000 0000 45 69 0x5e TxSta4: 0100 0101 03 3 0x5f 0000 0011 a0 160 0x60 TxSta2: 1010 0000 00 0 0x61 0000 0000 45 69 0x62 TxSta0: 0100 0101 2e 46 Transmitter: End of Tx status registers 22 34 state: 010 - Idler 25 37 state: 101 - Transmitter: S-Packet 00 0 28 40 Reset_hard: Done holding Eth. Ctrl. reset pin ------------ 50 80 IRQ: INT0 0001_0000 - Oscillator init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 29 41 Reset_hard: Done! Wrote to all Eth. Ctrl. config. regs 24 36 state: 100 - Querier (of Temp. and ADC) 00 0 00 0 ff 255 00 0 ff 255 ff 255 00 0 25 37 state: 101 - Transmitter: S-Packet 2d 45 Transmitter: Beginning Tx status check... 00 0 0x57 TxEnd: 0000 0000 40 64 0x58 0100 0000 00 0 0x59 TxStart: 0000 0000 40 64 0x5a 0100 0000 f1 241 0x5b ->0x78-Phy1111 0001 00 0 0x5c TxSta6: 0000 0000 00 0 0x5d 0000 0000 45 69 0x5e TxSta4: 0100 0101 03 3 0x5f 0000 0011 a0 160 0x60 TxSta2: 1010 0000 00 0 0x61 0000 0000 45 69 0x62 TxSta0: 0100 0101 2e 46 Transmitter: End of Tx status registers 22 34 state: 010 - Idler 25 37 state: 101 - Transmitter: S-Packet 00 0 28 40 Reset_hard: Done holding Eth. Ctrl. reset pin ------------ 50 80 IRQ: INT0 0001_0000 - Oscillator init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 29 41 Reset_hard: Done! Wrote to all Eth. Ctrl. config. regs 24 36 state: 100 - Querier (of Temp. and ADC) ff 255 00 0 ff 255 ff 255 ff 255 ff 255 ff 255 ff 255 2d 45 Transmitter: Beginning Tx status check... 00 0 0x57 TxEnd: 0000 0000 40 64 0x58 0100 0000 00 0 0x59 TxStart: 0000 0000 40 64 0x5a 0100 0000 f1 241 0x5b ->0x78-Phy1111 0001 00 0 0x5c TxSta6: 0000 0000 00 0 0x5d 0000 0000 45 69 0x5e TxSta4: 0100 0101 03 3 0x5f 0000 0011 a0 160 0x60 TxSta2: 1010 0000 00 0 0x61 0000 0000 45 69 0x62 TxSta0: 0100 0101 2e 46 Transmitter: End of Tx status registers 22 34 state: 010 - Idler ff 255 00 0 28 40 Reset_hard: Done holding Eth. Ctrl. reset pin ------------ 50 80 IRQ: INT0 0001_0000 - Oscillator init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 29 41 Reset_hard: Done! Wrote to all Eth. Ctrl. config. regs 24 36 state: 100 - Querier (of Temp. and ADC) 25 37 state: 101 - Transmitter: S-Packet 2d 45 Transmitter: Beginning Tx status check... 00 0 0x57 TxEnd: 0000 0000 40 64 0x58 0100 0000 00 0 0x59 TxStart: 0000 0000 40 64 0x5a 0100 0000 f1 241 0x5b ->0x78-Phy1111 0001 00 0 0x5c TxSta6: 0000 0000 00 0 0x5d 0000 0000 45 69 0x5e TxSta4: 0100 0101 03 3 0x5f 0000 0011 a0 160 0x60 TxSta2: 1010 0000 00 0 0x61 0000 0000 45 69 0x62 TxSta0: 0100 0101 2e 46 Transmitter: End of Tx status registers 22 34 state: 010 - Idler 25 37 state: 101 - Transmitter: S-Packet 00 0 28 40 Reset_hard: Done holding Eth. Ctrl. reset pin ------------ 50 80 IRQ: INT0 0001_0000 - Oscillator init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 29 41 Reset_hard: Done! Wrote to all Eth. Ctrl. config. regs 24 36 state: 100 - Querier (of Temp. and ADC) 25 37 state: 101 - Transmitter: S-Packet 2d 45 Transmitter: Beginning Tx status check... 00 0 0x57 TxEnd: 0000 0000 40 64 0x58 0100 0000 00 0 0x59 TxStart: 0000 0000 40 64 0x5a 0100 0000 f1 241 0x5b ->0x78-Phy1111 0001 00 0 0x5c TxSta6: 0000 0000 00 0 0x5d 0000 0000 45 69 0x5e TxSta4: 0100 0101 03 3 0x5f 0000 0011 a0 160 0x60 TxSta2: 1010 0000 00 0 0x61 0000 0000 45 69 0x62 TxSta0: 0100 0101 2e 46 Transmitter: End of Tx status registers 22 34 state: 010 - Idler 25 37 state: 101 - Transmitter: S-Packet 00 0 28 40 Reset_hard: Done holding Eth. Ctrl. reset pin ------------ 50 80 IRQ: INT0 0001_0000 - Oscillator init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 29 41 Reset_hard: Done! Wrote to all Eth. Ctrl. config. regs 24 36 state: 100 - Querier (of Temp. and ADC) 25 37 state: 101 - Transmitter: S-Packet 2d 45 Transmitter: Beginning Tx status check... 00 0 0x57 TxEnd: 0000 0000 40 64 0x58 0100 0000 00 0 0x59 TxStart: 0000 0000 40 64 0x5a 0100 0000 f1 241 0x5b ->0x78-Phy1111 0001 00 0 0x5c TxSta6: 0000 0000 00 0 0x5d 0000 0000 45 69 0x5e TxSta4: 0100 0101 03 3 0x5f 0000 0011 a0 160 0x60 TxSta2: 1010 0000 00 0 0x61 0000 0000 45 69 0x62 TxSta0: 0100 0101 2e 46 Transmitter: End of Tx status registers 22 34 state: 010 - Idler 25 37 state: 101 - Transmitter: S-Packet 00 0 28 40 Reset_hard: Done holding Eth. Ctrl. reset pin ------------ 50 80 IRQ: INT0 0001_0000 - Oscillator init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 29 41 Reset_hard: Done! Wrote to all Eth. Ctrl. config. regs 24 36 state: 100 - Querier (of Temp. and ADC) 25 37 state: 101 - Transmitter: S-Packet 2d 45 Transmitter: Beginning Tx status check... 00 0 0x57 TxEnd: 0000 0000 40 64 0x58 0100 0000 00 0 0x59 TxStart: 0000 0000 40 64 0x5a 0100 0000 f1 241 0x5b ->0x78-Phy1111 0001 00 0 0x5c TxSta6: 0000 0000 00 0 0x5d 0000 0000 45 69 0x5e TxSta4: 0100 0101 03 3 0x5f 0000 0011 a0 160 0x60 TxSta2: 1010 0000 00 0 0x61 0000 0000 28 40 0x62 TxSta0: 0010 1000 50 80 IRQ: INT0 0001_0000 - Oscillator init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 29 41 Reset_hard: Done! Wrote to all Eth. Ctrl. config. regs 24 36 state: 100 - Querier (of Temp. and ADC) 25 37 state: 101 - Transmitter: S-Packet 2d 45 Transmitter: Beginning Tx status check... 00 0 0x57 TxEnd: 0000 0000 40 64 0x58 0100 0000 00 0 0x59 TxStart: 0000 0000 40 64 0x5a 0100 0000 f1 241 0x5b ->0x78-Phy1111 0001 00 0 0x5c TxSta6: 0000 0000 00 0 0x5d 0000 0000 00 0 0x5e TxSta4: 0000 0000 28 40 0x5f 0010 1000 50 80 0x60 TxSta2: 0101 0000 60 96 0x61 0110 0000 29 41 0x62 TxSta0: 0010 1001 24 36 state: 100 - Querier (of Temp. and ADC) 25 37 state: 101 - Transmitter: S-Packet 2d 45 Transmitter: Beginning Tx status check... 00 0 0x57 TxEnd: 0000 0000 40 64 0x58 0100 0000 00 0 0x59 TxStart: 0000 0000 40 64 0x5a 0100 0000 f1 241 0x5b ->0x78-Phy1111 0001 00 0 0x5c TxSta6: 0000 0000 00 0 0x5d 0000 0000 45 69 0x5e TxSta4: 0100 0101 03 3 0x5f 0000 0011 a0 160 0x60 TxSta2: 1010 0000 00 0 0x61 0000 0000 45 69 0x62 TxSta0: 0100 0101 2e 46 Transmitter: End of Tx status registers 22 34 state: 010 - Idler 25 37 state: 101 - Transmitter: S-Packet 00 0 28 40 Reset_hard: Done holding Eth. Ctrl. reset pin ------------ 50 80 IRQ: INT0 0001_0000 - Oscillator init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 29 41 Reset_hard: Done! Wrote to all Eth. Ctrl. config. regs 24 36 state: 100 - Querier (of Temp. and ADC) 25 37 state: 101 - Transmitter: S-Packet 2d 45 Transmitter: Beginning Tx status check... 00 0 0x57 TxEnd: 0000 0000 40 64 0x58 0100 0000 00 0 0x59 TxStart: 0000 0000 40 64 0x5a 0100 0000 f1 241 0x5b ->0x78-Phy1111 0001 00 0 0x5c TxSta6: 0000 0000 00 0 0x5d 0000 0000 45 69 0x5e TxSta4: 0100 0101 03 3 0x5f 0000 0011 a0 160 0x60 TxSta2: 1010 0000 00 0 0x61 0000 0000 45 69 0x62 TxSta0: 0100 0101 2e 46 Transmitter: End of Tx status registers 22 34 state: 010 - Idler 25 37 state: 101 - Transmitter: S-Packet 00 0 28 40 Reset_hard: Done holding Eth. Ctrl. reset pin ------------ 50 80 IRQ: INT0 0001_0000 - Oscillator init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 29 41 Reset_hard: Done! Wrote to all Eth. Ctrl. config. regs 24 36 state: 100 - Querier (of Temp. and ADC) 25 37 state: 101 - Transmitter: S-Packet 2d 45 Transmitter: Beginning Tx status check... 00 0 0x57 TxEnd: 0000 0000 40 64 0x58 0100 0000 00 0 0x59 TxStart: 0000 0000 40 64 0x5a 0100 0000 f1 241 0x5b ->0x78-Phy1111 0001 00 0 0x5c TxSta6: 0000 0000 00 0 0x5d 0000 0000 45 69 0x5e TxSta4: 0100 0101 03 3 0x5f 0000 0011 a0 160 0x60 TxSta2: 1010 0000 00 0 0x61 0000 0000 45 69 0x62 TxSta0: 0100 0101 2e 46 Transmitter: End of Tx status registers 22 34 state: 010 - Idler 25 37 state: 101 - Transmitter: S-Packet 00 0 28 40 Reset_hard: Done holding Eth. Ctrl. reset pin ------------ 50 80 IRQ: INT0 0001_0000 - Oscillator init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 29 41 Reset_hard: Done! Wrote to all Eth. Ctrl. config. regs 24 36 state: 100 - Querier (of Temp. and ADC) 25 37 state: 101 - Transmitter: S-Packet 2d 45 Transmitter: Beginning Tx status check... 00 0 0x57 TxEnd: 0000 0000 40 64 0x58 0100 0000 00 0 0x59 TxStart: 0000 0000 40 64 0x5a 0100 0000 f1 241 0x5b ->0x78-Phy1111 0001 00 0 0x5c TxSta6: 0000 0000 00 0 0x5d 0000 0000 45 69 0x5e TxSta4: 0100 0101 03 3 0x5f 0000 0011 a0 160 0x60 TxSta2: 1010 0000 00 0 0x61 0000 0000 45 69 0x62 TxSta0: 0100 0101 2e 46 Transmitter: End of Tx status registers 22 34 state: 010 - Idler 25 37 state: 101 - Transmitter: S-Packet 00 0 28 40 Reset_hard: Done holding Eth. Ctrl. reset pin ------------ 50 80 IRQ: INT0 0001_0000 - Oscillator init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 29 41 Reset_hard: Done! Wrote to all Eth. Ctrl. config. regs 24 36 state: 100 - Querier (of Temp. and ADC) 25 37 state: 101 - Transmitter: S-Packet 2d 45 Transmitter: Beginning Tx status check... 00 0 0x57 TxEnd: 0000 0000 40 64 0x58 0100 0000 00 0 0x59 TxStart: 0000 0000 40 64 0x5a 0100 0000 f1 241 0x5b ->0x78-Phy1111 0001 00 0 0x5c TxSta6: 0000 0000 00 0 0x5d 0000 0000 45 69 0x5e TxSta4: 0100 0101 03 3 0x5f 0000 0011 a0 160 0x60 TxSta2: 1010 0000 00 0 0x61 0000 0000 45 69 0x62 TxSta0: 0100 0101 2e 46 Transmitter: End of Tx status registers 22 34 state: 010 - Idler 25 37 state: 101 - Transmitter: S-Packet 00 0 28 40 Reset_hard: Done holding Eth. Ctrl. reset pin ------------ 50 80 IRQ: INT0 0001_0000 - Oscillator init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 29 41 Reset_hard: Done! Wrote to all Eth. Ctrl. config. regs 24 36 state: 100 - Querier (of Temp. and ADC) 25 37 state: 101 - Transmitter: S-Packet 2d 45 Transmitter: Beginning Tx status check... 00 0 0x57 TxEnd: 0000 0000 40 64 0x58 0100 0000 00 0 0x59 TxStart: 0000 0000 40 64 0x5a 0100 0000 f1 241 0x5b ->0x78-Phy1111 0001 00 0 0x5c TxSta6: 0000 0000 00 0 0x5d 0000 0000 45 69 0x5e TxSta4: 0100 0101 03 3 0x5f 0000 0011 a0 160 0x60 TxSta2: 1010 0000 00 0 0x61 0000 0000 45 69 0x62 TxSta0: 0100 0101 2e 46 Transmitter: End of Tx status registers 22 34 state: 010 - Idler 25 37 state: 101 - Transmitter: S-Packet 00 0 28 40 Reset_hard: Done holding Eth. Ctrl. reset pin ------------ 50 80 IRQ: INT0 0001_0000 - Oscillator init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 29 41 Reset_hard: Done! Wrote to all Eth. Ctrl. config. regs 24 36 state: 100 - Querier (of Temp. and ADC) 25 37 state: 101 - Transmitter: S-Packet 2d 45 Transmitter: Beginning Tx status check... 00 0 0x57 TxEnd: 0000 0000 40 64 0x58 0100 0000 00 0 0x59 TxStart: 0000 0000 40 64 0x5a 0100 0000 f1 241 0x5b ->0x78-Phy1111 0001 00 0 0x5c TxSta6: 0000 0000 00 0 0x5d 0000 0000 45 69 0x5e TxSta4: 0100 0101 03 3 0x5f 0000 0011 a0 160 0x60 TxSta2: 1010 0000 00 0 0x61 0000 0000 45 69 0x62 TxSta0: 0100 0101 2e 46 Transmitter: End of Tx status registers 22 34 state: 010 - Idler 25 37 state: 101 - Transmitter: S-Packet 00 0 28 40 Reset_hard: Done holding Eth. Ctrl. reset pin ------------ 50 80 IRQ: INT0 0001_0000 - Oscillator init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 29 41 Reset_hard: Done! Wrote to all Eth. Ctrl. config. regs 24 36 state: 100 - Querier (of Temp. and ADC) 25 37 state: 101 - Transmitter: S-Packet 2d 45 Transmitter: Beginning Tx status check... 00 0 0x57 TxEnd: 0000 0000 40 64 0x58 0100 0000 00 0 0x59 TxStart: 0000 0000 40 64 0x5a 0100 0000 f1 241 0x5b ->0x78-Phy1111 0001 00 0 0x5c TxSta6: 0000 0000 00 0 0x5d 0000 0000 45 69 0x5e TxSta4: 0100 0101 03 3 0x5f 0000 0011 a0 160 0x60 TxSta2: 1010 0000 00 0 0x61 0000 0000 45 69 0x62 TxSta0: 0100 0101 2e 46 Transmitter: End of Tx status registers 22 34 state: 010 - Idler 25 37 state: 101 - Transmitter: S-Packet 41 65 IRQ: INT0 0000_0001 - Packet received 00 0 28 40 Reset_hard: Done holding Eth. Ctrl. reset pin ------------ 50 80 IRQ: INT0 0001_0000 - Oscillator init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 29 41 Reset_hard: Done! Wrote to all Eth. Ctrl. config. regs 24 36 state: 100 - Querier (of Temp. and ADC) 25 37 state: 101 - Transmitter: S-Packet 2d 45 Transmitter: Beginning Tx status check... 00 0 0x57 TxEnd: 0000 0000 40 64 0x58 0100 0000 00 0 0x59 TxStart: 0000 0000 40 64 0x5a 0100 0000 f1 241 0x5b ->0x78-Phy1111 0001 00 0 0x5c TxSta6: 0000 0000 00 0 0x5d 0000 0000 45 69 0x5e TxSta4: 0100 0101 03 3 0x5f 0000 0011 a0 160 0x60 TxSta2: 1010 0000 00 0 0x61 0000 0000 45 69 0x62 TxSta0: 0100 0101 2e 46 Transmitter: End of Tx status registers 22 34 state: 010 - Idler 25 37 state: 101 - Transmitter: S-Packet 41 65 IRQ: INT0 0000_0001 - Packet received 00 0 28 40 Reset_hard: Done holding Eth. Ctrl. reset pin ------------ 50 80 IRQ: INT0 0001_0000 - Oscillator init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 29 41 Reset_hard: Done! Wrote to all Eth. Ctrl. config. regs 24 36 state: 100 - Querier (of Temp. and ADC) 25 37 state: 101 - Transmitter: S-Packet 2d 45 Transmitter: Beginning Tx status check... 00 0 0x57 TxEnd: 0000 0000 40 64 0x58 0100 0000 00 0 0x59 TxStart: 0000 0000 40 64 0x5a 0100 0000 f1 241 0x5b ->0x78-Phy1111 0001 00 0 0x5c TxSta6: 0000 0000 00 0 0x5d 0000 0000 45 69 0x5e TxSta4: 0100 0101 03 3 0x5f 0000 0011 a0 160 0x60 TxSta2: 1010 0000 00 0 0x61 0000 0000 45 69 0x62 TxSta0: 0100 0101 2e 46 Transmitter: End of Tx status registers 22 34 state: 010 - Idler 25 37 state: 101 - Transmitter: S-Packet 41 65 IRQ: INT0 0000_0001 - Packet received 00 0 28 40 Reset_hard: Done holding Eth. Ctrl. reset pin ------------ 50 80 IRQ: INT0 0001_0000 - Oscillator init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 29 41 Reset_hard: Done! Wrote to all Eth. Ctrl. config. regs 24 36 state: 100 - Querier (of Temp. and ADC) 25 37 state: 101 - Transmitter: S-Packet 2d 45 Transmitter: Beginning Tx status check... 00 0 0x57 TxEnd: 0000 0000 40 64 0x58 0100 0000 00 0 0x59 TxStart: 0000 0000 40 64 0x5a 0100 0000 f1 241 0x5b ->0x78-Phy1111 0001 00 0 0x5c TxSta6: 0000 0000 00 0 0x5d 0000 0000 45 69 0x5e TxSta4: 0100 0101 03 3 0x5f 0000 0011 a0 160 0x60 TxSta2: 1010 0000 00 0 0x61 0000 0000 45 69 0x62 TxSta0: 0100 0101 2e 46 Transmitter: End of Tx status registers 22 34 state: 010 - Idler 25 37 state: 101 - Transmitter: S-Packet 41 65 IRQ: INT0 0000_0001 - Packet received 00 0 28 40 Reset_hard: Done holding Eth. Ctrl. reset pin ------------ 50 80 IRQ: INT0 0001_0000 - Oscillator init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 29 41 Reset_hard: Done! Wrote to all Eth. Ctrl. config. regs 24 36 state: 100 - Querier (of Temp. and ADC) 25 37 state: 101 - Transmitter: S-Packet 2d 45 Transmitter: Beginning Tx status check... 00 0 0x57 TxEnd: 0000 0000 40 64 0x58 0100 0000 00 0 0x59 TxStart: 0000 0000 40 64 0x5a 0100 0000 f1 241 0x5b ->0x78-Phy1111 0001 00 0 0x5c TxSta6: 0000 0000 00 0 0x5d 0000 0000 45 69 0x5e TxSta4: 0100 0101 03 3 0x5f 0000 0011 a0 160 0x60 TxSta2: 1010 0000 00 0 0x61 0000 0000 45 69 0x62 TxSta0: 0100 0101 2e 46 Transmitter: End of Tx status registers 22 34 state: 010 - Idler 25 37 state: 101 - Transmitter: S-Packet 41 65 IRQ: INT0 0000_0001 - Packet received 00 0 28 40 Reset_hard: Done holding Eth. Ctrl. reset pin ------------ 50 80 IRQ: INT0 0001_0000 - Oscillator init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 29 41 Reset_hard: Done! Wrote to all Eth. Ctrl. config. regs 24 36 state: 100 - Querier (of Temp. and ADC) 25 37 state: 101 - Transmitter: S-Packet 2d 45 Transmitter: Beginning Tx status check... 00 0 0x57 TxEnd: 0000 0000 40 64 0x58 0100 0000 00 0 0x59 TxStart: 0000 0000 40 64 0x5a 0100 0000 f1 241 0x5b ->0x78-Phy1111 0001 00 0 0x5c TxSta6: 0000 0000 00 0 0x5d 0000 0000 45 69 0x5e TxSta4: 0100 0101 03 3 0x5f 0000 0011 a0 160 0x60 TxSta2: 1010 0000 00 0 0x61 0000 0000 45 69 0x62 TxSta0: 0100 0101 2e 46 Transmitter: End of Tx status registers 22 34 state: 010 - Idler 25 37 state: 101 - Transmitter: S-Packet 41 65 IRQ: INT0 0000_0001 - Packet received 00 0 28 40 Reset_hard: Done holding Eth. Ctrl. reset pin ------------ 50 80 IRQ: INT0 0001_0000 - Oscillator init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 29 41 Reset_hard: Done! Wrote to all Eth. Ctrl. config. regs 24 36 state: 100 - Querier (of Temp. and ADC) 25 37 state: 101 - Transmitter: S-Packet 2d 45 Transmitter: Beginning Tx status check... 00 0 0x57 TxEnd: 0000 0000 40 64 0x58 0100 0000 00 0 0x59 TxStart: 0000 0000 40 64 0x5a 0100 0000 f1 241 0x5b ->0x78-Phy1111 0001 00 0 0x5c TxSta6: 0000 0000 00 0 0x5d 0000 0000 45 69 0x5e TxSta4: 0100 0101 03 3 0x5f 0000 0011 a0 160 0x60 TxSta2: 1010 0000 00 0 0x61 0000 0000 45 69 0x62 TxSta0: 0100 0101 2e 46 Transmitter: End of Tx status registers 22 34 state: 010 - Idler 25 37 state: 101 - Transmitter: S-Packet 00 0 28 40 Reset_hard: Done holding Eth. Ctrl. reset pin ------------ 50 80 IRQ: INT0 0001_0000 - Oscillator init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 29 41 Reset_hard: Done! Wrote to all Eth. Ctrl. config. regs 24 36 state: 100 - Querier (of Temp. and ADC) 25 37 state: 101 - Transmitter: S-Packet 2d 45 Transmitter: Beginning Tx status check... 00 0 0x57 TxEnd: 0000 0000 40 64 0x58 0100 0000 00 0 0x59 TxStart: 0000 0000 40 64 0x5a 0100 0000 f1 241 0x5b ->0x78-Phy1111 0001 00 0 0x5c TxSta6: 0000 0000 00 0 0x5d 0000 0000 45 69 0x5e TxSta4: 0100 0101 03 3 0x5f 0000 0011 a0 160 0x60 TxSta2: 1010 0000 00 0 0x61 0000 0000 45 69 0x62 TxSta0: 0100 0101 2e 46 Transmitter: End of Tx status registers 22 34 state: 010 - Idler 25 37 state: 101 - Transmitter: S-Packet 41 65 IRQ: INT0 0000_0001 - Packet received 00 0 28 40 Reset_hard: Done holding Eth. Ctrl. reset pin ------------ 50 80 IRQ: INT0 0001_0000 - Oscillator init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 29 41 Reset_hard: Done! Wrote to all Eth. Ctrl. config. regs 24 36 state: 100 - Querier (of Temp. and ADC) 25 37 state: 101 - Transmitter: S-Packet 2d 45 Transmitter: Beginning Tx status check... 00 0 0x57 TxEnd: 0000 0000 40 64 0x58 0100 0000 00 0 0x59 TxStart: 0000 0000 40 64 0x5a 0100 0000 f1 241 0x5b ->0x78-Phy1111 0001 00 0 0x5c TxSta6: 0000 0000 00 0 0x5d 0000 0000 45 69 0x5e TxSta4: 0100 0101 03 3 0x5f 0000 0011 a0 160 0x60 TxSta2: 1010 0000 00 0 0x61 0000 0000 45 69 0x62 TxSta0: 0100 0101 2e 46 Transmitter: End of Tx status registers 22 34 state: 010 - Idler 25 37 state: 101 - Transmitter: S-Packet 41 65 IRQ: INT0 0000_0001 - Packet received 00 0 28 40 Reset_hard: Done holding Eth. Ctrl. reset pin ------------ 50 80 IRQ: INT0 0001_0000 - Oscillator init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 29 41 Reset_hard: Done! Wrote to all Eth. Ctrl. config. regs 24 36 state: 100 - Querier (of Temp. and ADC) 25 37 state: 101 - Transmitter: S-Packet 2d 45 Transmitter: Beginning Tx status check... 00 0 0x57 TxEnd: 0000 0000 40 64 0x58 0100 0000 00 0 0x59 TxStart: 0000 0000 40 64 0x5a 0100 0000 f1 241 0x5b ->0x78-Phy1111 0001 00 0 0x5c TxSta6: 0000 0000 00 0 0x5d 0000 0000 45 69 0x5e TxSta4: 0100 0101 03 3 0x5f 0000 0011 a0 160 0x60 TxSta2: 1010 0000 00 0 0x61 0000 0000 45 69 0x62 TxSta0: 0100 0101 2e 46 Transmitter: End of Tx status registers 22 34 state: 010 - Idler 25 37 state: 101 - Transmitter: S-Packet 00 0 28 40 Reset_hard: Done holding Eth. Ctrl. reset pin ------------ 50 80 IRQ: INT0 0001_0000 - Oscillator init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 29 41 Reset_hard: Done! Wrote to all Eth. Ctrl. config. regs 24 36 state: 100 - Querier (of Temp. and ADC) 25 37 state: 101 - Transmitter: S-Packet 2d 45 Transmitter: Beginning Tx status check... 00 0 0x57 TxEnd: 0000 0000 40 64 0x58 0100 0000 00 0 0x59 TxStart: 0000 0000 40 64 0x5a 0100 0000 f1 241 0x5b ->0x78-Phy1111 0001 00 0 0x5c TxSta6: 0000 0000 00 0 0x5d 0000 0000 45 69 0x5e TxSta4: 0100 0101 03 3 0x5f 0000 0011 a0 160 0x60 TxSta2: 1010 0000 00 0 0x61 0000 0000 45 69 0x62 TxSta0: 0100 0101 2e 46 Transmitter: End of Tx status registers 22 34 state: 010 - Idler 25 37 state: 101 - Transmitter: S-Packet 41 65 IRQ: INT0 0000_0001 - Packet received 00 0 28 40 Reset_hard: Done holding Eth. Ctrl. reset pin ------------ 50 80 IRQ: INT0 0001_0000 - Oscillator init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 29 41 Reset_hard: Done! Wrote to all Eth. Ctrl. config. regs 24 36 state: 100 - Querier (of Temp. and ADC) 25 37 state: 101 - Transmitter: S-Packet 2d 45 Transmitter: Beginning Tx status check... 00 0 0x57 TxEnd: 0000 0000 40 64 0x58 0100 0000 00 0 0x59 TxStart: 0000 0000 40 64 0x5a 0100 0000 f1 241 0x5b ->0x78-Phy1111 0001 00 0 0x5c TxSta6: 0000 0000 00 0 0x5d 0000 0000 45 69 0x5e TxSta4: 0100 0101 03 3 0x5f 0000 0011 a0 160 0x60 TxSta2: 1010 0000 00 0 0x61 0000 0000 45 69 0x62 TxSta0: 0100 0101 2e 46 Transmitter: End of Tx status registers 22 34 state: 010 - Idler 25 37 state: 101 - Transmitter: S-Packet 41 65 IRQ: INT0 0000_0001 - Packet received 00 0 28 40 Reset_hard: Done holding Eth. Ctrl. reset pin ------------ 50 80 IRQ: INT0 0001_0000 - Oscillator init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 29 41 Reset_hard: Done! Wrote to all Eth. Ctrl. config. regs 24 36 state: 100 - Querier (of Temp. and ADC) 25 37 state: 101 - Transmitter: S-Packet 2d 45 Transmitter: Beginning Tx status check... 00 0 0x57 TxEnd: 0000 0000 40 64 0x58 0100 0000 00 0 0x59 TxStart: 0000 0000 40 64 0x5a 0100 0000 f1 241 0x5b ->0x78-Phy1111 0001 00 0 0x5c TxSta6: 0000 0000 00 0 0x5d 0000 0000 45 69 0x5e TxSta4: 0100 0101 03 3 0x5f 0000 0011 a0 160 0x60 TxSta2: 1010 0000 00 0 0x61 0000 0000 45 69 0x62 TxSta0: 0100 0101 2e 46 Transmitter: End of Tx status registers 22 34 state: 010 - Idler 25 37 state: 101 - Transmitter: S-Packet 41 65 IRQ: INT0 0000_0001 - Packet received 00 0 28 40 Reset_hard: Done holding Eth. Ctrl. reset pin ------------ 50 80 IRQ: INT0 0001_0000 - Oscillator init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 29 41 Reset_hard: Done! Wrote to all Eth. Ctrl. config. regs 24 36 state: 100 - Querier (of Temp. and ADC) 25 37 state: 101 - Transmitter: S-Packet 2d 45 Transmitter: Beginning Tx status check... 00 0 0x57 TxEnd: 0000 0000 40 64 0x58 0100 0000 00 0 0x59 TxStart: 0000 0000 40 64 0x5a 0100 0000 f1 241 0x5b ->0x78-Phy1111 0001 00 0 0x5c TxSta6: 0000 0000 00 0 0x5d 0000 0000 45 69 0x5e TxSta4: 0100 0101 03 3 0x5f 0000 0011 a0 160 0x60 TxSta2: 1010 0000 00 0 0x61 0000 0000 45 69 0x62 TxSta0: 0100 0101 2e 46 Transmitter: End of Tx status registers 22 34 state: 010 - Idler 25 37 state: 101 - Transmitter: S-Packet 41 65 IRQ: INT0 0000_0001 - Packet received 00 0 28 40 Reset_hard: Done holding Eth. Ctrl. reset pin ------------ 50 80 IRQ: INT0 0001_0000 - Oscillator init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 29 41 Reset_hard: Done! Wrote to all Eth. Ctrl. config. regs 24 36 state: 100 - Querier (of Temp. and ADC) 25 37 state: 101 - Transmitter: S-Packet 2d 45 Transmitter: Beginning Tx status check... 00 0 0x57 TxEnd: 0000 0000 40 64 0x58 0100 0000 00 0 0x59 TxStart: 0000 0000 40 64 0x5a 0100 0000 f1 241 0x5b ->0x78-Phy1111 0001 00 0 0x5c TxSta6: 0000 0000 00 0 0x5d 0000 0000 45 69 0x5e TxSta4: 0100 0101 03 3 0x5f 0000 0011 a0 160 0x60 TxSta2: 1010 0000 00 0 0x61 0000 0000 45 69 0x62 TxSta0: 0100 0101 2e 46 Transmitter: End of Tx status registers 22 34 state: 010 - Idler 25 37 state: 101 - Transmitter: S-Packet 41 65 IRQ: INT0 0000_0001 - Packet received 00 0 28 40 Reset_hard: Done holding Eth. Ctrl. reset pin ------------ 50 80 IRQ: INT0 0001_0000 - Oscillator init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 29 41 Reset_hard: Done! Wrote to all Eth. Ctrl. config. regs 24 36 state: 100 - Querier (of Temp. and ADC) 25 37 state: 101 - Transmitter: S-Packet 2d 45 Transmitter: Beginning Tx status check... 00 0 0x57 TxEnd: 0000 0000 40 64 0x58 0100 0000 00 0 0x59 TxStart: 0000 0000 40 64 0x5a 0100 0000 f1 241 0x5b ->0x78-Phy1111 0001 00 0 0x5c TxSta6: 0000 0000 00 0 0x5d 0000 0000 45 69 0x5e TxSta4: 0100 0101 03 3 0x5f 0000 0011 a0 160 0x60 TxSta2: 1010 0000 00 0 0x61 0000 0000 45 69 0x62 TxSta0: 0100 0101 2e 46 Transmitter: End of Tx status registers 22 34 state: 010 - Idler 25 37 state: 101 - Transmitter: S-Packet 41 65 IRQ: INT0 0000_0001 - Packet received 00 0 28 40 Reset_hard: Done holding Eth. Ctrl. reset pin ------------ 50 80 IRQ: INT0 0001_0000 - Oscillator init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 29 41 Reset_hard: Done! Wrote to all Eth. Ctrl. config. regs 24 36 state: 100 - Querier (of Temp. and ADC) 25 37 state: 101 - Transmitter: S-Packet 2d 45 Transmitter: Beginning Tx status check... 00 0 0x57 TxEnd: 0000 0000 40 64 0x58 0100 0000 00 0 0x59 TxStart: 0000 0000 40 64 0x5a 0100 0000 f1 241 0x5b ->0x78-Phy1111 0001 00 0 0x5c TxSta6: 0000 0000 00 0 0x5d 0000 0000 45 69 0x5e TxSta4: 0100 0101 03 3 0x5f 0000 0011 a0 160 0x60 TxSta2: 1010 0000 00 0 0x61 0000 0000 45 69 0x62 TxSta0: 0100 0101 2e 46 Transmitter: End of Tx status registers 22 34 state: 010 - Idler 25 37 state: 101 - Transmitter: S-Packet 41 65 IRQ: INT0 0000_0001 - Packet received 00 0 28 40 Reset_hard: Done holding Eth. Ctrl. reset pin ------------ 50 80 IRQ: INT0 0001_0000 - Oscillator init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 29 41 Reset_hard: Done! Wrote to all Eth. Ctrl. config. regs 24 36 state: 100 - Querier (of Temp. and ADC) 25 37 state: 101 - Transmitter: S-Packet 2d 45 Transmitter: Beginning Tx status check... 00 0 0x57 TxEnd: 0000 0000 40 64 0x58 0100 0000 00 0 0x59 TxStart: 0000 0000 40 64 0x5a 0100 0000 f1 241 0x5b ->0x78-Phy1111 0001 00 0 0x5c TxSta6: 0000 0000 00 0 0x5d 0000 0000 45 69 0x5e TxSta4: 0100 0101 03 3 0x5f 0000 0011 a0 160 0x60 TxSta2: 1010 0000 00 0 0x61 0000 0000 45 69 0x62 TxSta0: 0100 0101 2e 46 Transmitter: End of Tx status registers 22 34 state: 010 - Idler 25 37 state: 101 - Transmitter: S-Packet 41 65 IRQ: INT0 0000_0001 - Packet received 00 0 28 40 Reset_hard: Done holding Eth. Ctrl. reset pin ------------ 50 80 IRQ: INT0 0001_0000 - Oscillator init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 29 41 Reset_hard: Done! Wrote to all Eth. Ctrl. config. regs 24 36 state: 100 - Querier (of Temp. and ADC) 25 37 state: 101 - Transmitter: S-Packet 2d 45 Transmitter: Beginning Tx status check... 00 0 0x57 TxEnd: 0000 0000 40 64 0x58 0100 0000 00 0 0x59 TxStart: 0000 0000 40 64 0x5a 0100 0000 f1 241 0x5b ->0x78-Phy1111 0001 00 0 0x5c TxSta6: 0000 0000 00 0 0x5d 0000 0000 45 69 0x5e TxSta4: 0100 0101 03 3 0x5f 0000 0011 a0 160 0x60 TxSta2: 1010 0000 00 0 0x61 0000 0000 45 69 0x62 TxSta0: 0100 0101 2e 46 Transmitter: End of Tx status registers 22 34 state: 010 - Idler 25 37 state: 101 - Transmitter: S-Packet 41 65 IRQ: INT0 0000_0001 - Packet received 00 0 df 223 ff 255 f0 240 00 0 ff 255 00 0 3f 63 00 0 00 0 7f 127 00 0 00 0 ff 255 f8 248 00 0 ff 255 00 0 80 128 00 0 7f 127 f0 240 00 0 00 0 3f 63 f0 240 00 0 00 0 ff 255 fc 252 00 0 77 119 00 0 00 0 fb 251 f0 240 00 0 00 0 b7 183 00 0 00 0 f7 247 ff 255 00 0 00 0 ff 255 fe 254 00 0 00 0 ff 255 ff 255 00 0 00 0 00 0 ff 255 ff 255 80 128 00 0 df 223 fe 254 00 0 00 0 ff 255 fc 252 00 0 28 40 Reset_hard: Done holding Eth. Ctrl. reset pin ------------ 50 80 IRQ: INT0 0001_0000 - Oscillator init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 29 41 Reset_hard: Done! Wrote to all Eth. Ctrl. config. regs 25 37 state: 101 - Transmitter: S-Packet 2d 45 Transmitter: Beginning Tx status check... 00 0 0x57 TxEnd: 0000 0000 00 0 0x58 0000 0000 00 0 0x59 TxStart: 0000 0000 00 0 0x5a 0000 0000 f1 241 0x5b ->0x78-Phy1111 0001 00 0 0x5c TxSta6: 0000 0000 06 6 0x5d 0000 0110 00 0 0x5e TxSta4: 0000 0000 40 64 0x5f 0100 0000 40 64 0x60 TxSta2: 0100 0000 00 0 0x61 0000 0000 00 0 0x62 TxSta0: 0000 0000 2e 46 Transmitter: End of Tx status registers 22 34 state: 010 - Idler 25 37 state: 101 - Transmitter: S-Packet 00 0 28 40 Reset_hard: Done holding Eth. Ctrl. reset pin ------------ 50 80 IRQ: INT0 0001_0000 - Oscillator init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 29 41 Reset_hard: Done! Wrote to all Eth. Ctrl. config. regs 25 37 state: 101 - Transmitter: S-Packet 2d 45 Transmitter: Beginning Tx status check... 00 0 0x57 TxEnd: 0000 0000 00 0 0x58 0000 0000 00 0 0x59 TxStart: 0000 0000 00 0 0x5a 0000 0000 f1 241 0x5b ->0x78-Phy1111 0001 00 0 0x5c TxSta6: 0000 0000 06 6 0x5d 0000 0110 00 0 0x5e TxSta4: 0000 0000 40 64 0x5f 0100 0000 40 64 0x60 TxSta2: 0100 0000 00 0 0x61 0000 0000 00 0 0x62 TxSta0: 0000 0000 2e 46 Transmitter: End of Tx status registers 22 34 state: 010 - Idler 25 37 state: 101 - Transmitter: S-Packet 00 0 28 40 Reset_hard: Done holding Eth. Ctrl. reset pin ------------ 50 80 IRQ: INT0 0001_0000 - Oscillator init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 29 41 Reset_hard: Done! Wrote to all Eth. Ctrl. config. regs 25 37 state: 101 - Transmitter: S-Packet 2d 45 Transmitter: Beginning Tx status check... 00 0 0x57 TxEnd: 0000 0000 00 0 0x58 0000 0000 00 0 0x59 TxStart: 0000 0000 00 0 0x5a 0000 0000 f1 241 0x5b ->0x78-Phy1111 0001 00 0 0x5c TxSta6: 0000 0000 06 6 0x5d 0000 0110 00 0 0x5e TxSta4: 0000 0000 40 64 0x5f 0100 0000 40 64 0x60 TxSta2: 0100 0000 00 0 0x61 0000 0000 00 0 0x62 TxSta0: 0000 0000 2e 46 Transmitter: End of Tx status registers 22 34 state: 010 - Idler 25 37 state: 101 - Transmitter: S-Packet 00 0 28 40 Reset_hard: Done holding Eth. Ctrl. reset pin ------------ 50 80 IRQ: INT0 0001_0000 - Oscillator init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 29 41 Reset_hard: Done! Wrote to all Eth. Ctrl. config. regs 25 37 state: 101 - Transmitter: S-Packet 2d 45 Transmitter: Beginning Tx status check... 00 0 0x57 TxEnd: 0000 0000 00 0 0x58 0000 0000 00 0 0x59 TxStart: 0000 0000 00 0 0x5a 0000 0000 f1 241 0x5b ->0x78-Phy1111 0001 00 0 0x5c TxSta6: 0000 0000 06 6 0x5d 0000 0110 00 0 0x5e TxSta4: 0000 0000 40 64 0x5f 0100 0000 40 64 0x60 TxSta2: 0100 0000 00 0 0x61 0000 0000 00 0 0x62 TxSta0: 0000 0000 2e 46 Transmitter: End of Tx status registers 22 34 state: 010 - Idler 25 37 state: 101 - Transmitter: S-Packet 00 0 28 40 Reset_hard: Done holding Eth. Ctrl. reset pin ------------ 50 80 IRQ: INT0 0001_0000 - Oscillator init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 29 41 Reset_hard: Done! Wrote to all Eth. Ctrl. config. regs 25 37 state: 101 - Transmitter: S-Packet 2d 45 Transmitter: Beginning Tx status check... 00 0 0x57 TxEnd: 0000 0000 00 0 0x58 0000 0000 00 0 0x59 TxStart: 0000 0000 00 0 0x5a 0000 0000 f1 241 0x5b ->0x78-Phy1111 0001 00 0 0x5c TxSta6: 0000 0000 06 6 0x5d 0000 0110 00 0 0x5e TxSta4: 0000 0000 40 64 0x5f 0100 0000 40 64 0x60 TxSta2: 0100 0000 00 0 0x61 0000 0000 00 0 0x62 TxSta0: 0000 0000 2e 46 Transmitter: End of Tx status registers 22 34 state: 010 - Idler 25 37 state: 101 - Transmitter: S-Packet 00 0 28 40 Reset_hard: Done holding Eth. Ctrl. reset pin ------------ 50 80 IRQ: INT0 0001_0000 - Oscillator init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 29 41 Reset_hard: Done! Wrote to all Eth. Ctrl. config. regs 25 37 state: 101 - Transmitter: S-Packet 2d 45 Transmitter: Beginning Tx status check... 00 0 0x57 TxEnd: 0000 0000 00 0 0x58 0000 0000 00 0 0x59 TxStart: 0000 0000 00 0 0x5a 0000 0000 f1 241 0x5b ->0x78-Phy1111 0001 00 0 0x5c TxSta6: 0000 0000 00 0 0x5d 0000 0000 28 40 0x5e TxSta4: 0010 1000 50 80 0x5f 0101 0000 60 96 0x60 TxSta2: 0110 0000 29 41 0x61 0010 1001 25 37 0x62 TxSta0: 0010 0101 2d 45 Transmitter: Beginning Tx status check... 00 0 0x57 TxEnd: 0000 0000 00 0 0x58 0000 0000 00 0 0x59 TxStart: 0000 0000 00 0 0x5a 0000 0000 f1 241 0x5b ->0x78-Phy1111 0001 00 0 0x5c TxSta6: 0000 0000 06 6 0x5d 0000 0110 00 0 0x5e TxSta4: 0000 0000 40 64 0x5f 0100 0000 00 0 0x60 TxSta2: 0000 0000 28 40 0x61 0010 1000 50 80 0x62 TxSta0: 0101 0000 60 96 IRQ: INT0 0010_0000 - Self-init. complete 29 41 Reset_hard: Done! Wrote to all Eth. Ctrl. config. regs 25 37 state: 101 - Transmitter: S-Packet 2d 45 Transmitter: Beginning Tx status check... 00 0 0x57 TxEnd: 0000 0000 00 0 0x58 0000 0000 00 0 0x59 TxStart: 0000 0000 00 0 0x5a 0000 0000 f1 241 0x5b ->0x78-Phy1111 0001 00 0 0x5c TxSta6: 0000 0000 06 6 0x5d 0000 0110 00 0 0x5e TxSta4: 0000 0000 40 64 0x5f 0100 0000 40 64 0x60 TxSta2: 0100 0000 00 0 0x61 0000 0000 00 0 0x62 TxSta0: 0000 0000 2e 46 Transmitter: End of Tx status registers 22 34 state: 010 - Idler 25 37 state: 101 - Transmitter: S-Packet 00 0 28 40 Reset_hard: Done holding Eth. Ctrl. reset pin ------------ 50 80 IRQ: INT0 0001_0000 - Oscillator init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 29 41 Reset_hard: Done! Wrote to all Eth. Ctrl. config. regs 25 37 state: 101 - Transmitter: S-Packet 2d 45 Transmitter: Beginning Tx status check... 00 0 0x57 TxEnd: 0000 0000 00 0 0x58 0000 0000 00 0 0x59 TxStart: 0000 0000 00 0 0x5a 0000 0000 f1 241 0x5b ->0x78-Phy1111 0001 00 0 0x5c TxSta6: 0000 0000 06 6 0x5d 0000 0110 00 0 0x5e TxSta4: 0000 0000 28 40 0x5f 0010 1000 50 80 0x60 TxSta2: 0101 0000 60 96 0x61 0110 0000 29 41 0x62 TxSta0: 0010 1001 25 37 state: 101 - Transmitter: S-Packet 2d 45 Transmitter: Beginning Tx status check... 00 0 0x57 TxEnd: 0000 0000 00 0 0x58 0000 0000 00 0 0x59 TxStart: 0000 0000 00 0 0x5a 0000 0000 f1 241 0x5b ->0x78-Phy1111 0001 00 0 0x5c TxSta6: 0000 0000 06 6 0x5d 0000 0110 00 0 0x5e TxSta4: 0000 0000 40 64 0x5f 0100 0000 40 64 0x60 TxSta2: 0100 0000 00 0 0x61 0000 0000 00 0 0x62 TxSta0: 0000 0000 2e 46 Transmitter: End of Tx status registers 22 34 state: 010 - Idler 25 37 state: 101 - Transmitter: S-Packet 00 0 28 40 Reset_hard: Done holding Eth. Ctrl. reset pin ------------ 50 80 IRQ: INT0 0001_0000 - Oscillator init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 29 41 Reset_hard: Done! Wrote to all Eth. Ctrl. config. regs 25 37 state: 101 - Transmitter: S-Packet 2d 45 Transmitter: Beginning Tx status check... 00 0 0x57 TxEnd: 0000 0000 00 0 0x58 0000 0000 00 0 0x59 TxStart: 0000 0000 00 0 0x5a 0000 0000 f0 240 0x5b ->0x78-Phy1111 0000 00 0 0x5c TxSta6: 0000 0000 00 0 0x5d 0000 0000 00 0 0x5e TxSta4: 0000 0000 40 64 0x5f 0100 0000 40 64 0x60 TxSta2: 0100 0000 00 0 0x61 0000 0000 00 0 0x62 TxSta0: 0000 0000 2e 46 Transmitter: End of Tx status registers 22 34 state: 010 - Idler 25 37 state: 101 - Transmitter: S-Packet 00 0 28 40 Reset_hard: Done holding Eth. Ctrl. reset pin ------------ 50 80 IRQ: INT0 0001_0000 - Oscillator init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 29 41 Reset_hard: Done! Wrote to all Eth. Ctrl. config. regs 25 37 state: 101 - Transmitter: S-Packet 2d 45 Transmitter: Beginning Tx status check... 00 0 0x57 TxEnd: 0000 0000 00 0 0x58 0000 0000 00 0 0x59 TxStart: 0000 0000 00 0 0x5a 0000 0000 f1 241 0x5b ->0x78-Phy1111 0001 00 0 0x5c TxSta6: 0000 0000 06 6 0x5d 0000 0110 00 0 0x5e TxSta4: 0000 0000 40 64 0x5f 0100 0000 40 64 0x60 TxSta2: 0100 0000 00 0 0x61 0000 0000 00 0 0x62 TxSta0: 0000 0000 2e 46 Transmitter: End of Tx status registers 22 34 state: 010 - Idler 25 37 state: 101 - Transmitter: S-Packet 00 0 28 40 Reset_hard: Done holding Eth. Ctrl. reset pin ------------ 50 80 IRQ: INT0 0001_0000 - Oscillator init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 29 41 Reset_hard: Done! Wrote to all Eth. Ctrl. config. regs 25 37 state: 101 - Transmitter: S-Packet 2d 45 Transmitter: Beginning Tx status check... 00 0 0x57 TxEnd: 0000 0000 00 0 0x58 0000 0000 00 0 0x59 TxStart: 0000 0000 00 0 0x5a 0000 0000 f1 241 0x5b ->0x78-Phy1111 0001 00 0 0x5c TxSta6: 0000 0000 06 6 0x5d 0000 0110 00 0 0x5e TxSta4: 0000 0000 40 64 0x5f 0100 0000 40 64 0x60 TxSta2: 0100 0000 00 0 0x61 0000 0000 00 0 0x62 TxSta0: 0000 0000 2e 46 Transmitter: End of Tx status registers 22 34 state: 010 - Idler 25 37 state: 101 - Transmitter: S-Packet 00 0 28 40 Reset_hard: Done holding Eth. Ctrl. reset pin ------------ 50 80 IRQ: INT0 0001_0000 - Oscillator init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 29 41 Reset_hard: Done! Wrote to all Eth. Ctrl. config. regs 25 37 state: 101 - Transmitter: S-Packet 2d 45 Transmitter: Beginning Tx status check... 00 0 0x57 TxEnd: 0000 0000 00 0 0x58 0000 0000 00 0 0x59 TxStart: 0000 0000 00 0 0x5a 0000 0000 f1 241 0x5b ->0x78-Phy1111 0001 00 0 0x5c TxSta6: 0000 0000 06 6 0x5d 0000 0110 00 0 0x5e TxSta4: 0000 0000 40 64 0x5f 0100 0000 40 64 0x60 TxSta2: 0100 0000 00 0 0x61 0000 0000 00 0 0x62 TxSta0: 0000 0000 2e 46 Transmitter: End of Tx status registers 22 34 state: 010 - Idler 25 37 state: 101 - Transmitter: S-Packet 00 0 28 40 Reset_hard: Done holding Eth. Ctrl. reset pin ------------ 50 80 IRQ: INT0 0001_0000 - Oscillator init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 29 41 Reset_hard: Done! Wrote to all Eth. Ctrl. config. regs 25 37 state: 101 - Transmitter: S-Packet 2d 45 Transmitter: Beginning Tx status check... 00 0 0x57 TxEnd: 0000 0000 00 0 0x58 0000 0000 00 0 0x59 TxStart: 0000 0000 00 0 0x5a 0000 0000 f1 241 0x5b ->0x78-Phy1111 0001 00 0 0x5c TxSta6: 0000 0000 06 6 0x5d 0000 0110 00 0 0x5e TxSta4: 0000 0000 40 64 0x5f 0100 0000 40 64 0x60 TxSta2: 0100 0000 00 0 0x61 0000 0000 00 0 0x62 TxSta0: 0000 0000 2e 46 Transmitter: End of Tx status registers 22 34 state: 010 - Idler 25 37 state: 101 - Transmitter: S-Packet 00 0 28 40 Reset_hard: Done holding Eth. Ctrl. reset pin ------------ 50 80 IRQ: INT0 0001_0000 - Oscillator init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 29 41 Reset_hard: Done! Wrote to all Eth. Ctrl. config. regs 25 37 state: 101 - Transmitter: S-Packet 2d 45 Transmitter: Beginning Tx status check... 00 0 0x57 TxEnd: 0000 0000 00 0 0x58 0000 0000 00 0 0x59 TxStart: 0000 0000 00 0 0x5a 0000 0000 f1 241 0x5b ->0x78-Phy1111 0001 00 0 0x5c TxSta6: 0000 0000 06 6 0x5d 0000 0110 00 0 0x5e TxSta4: 0000 0000 40 64 0x5f 0100 0000 00 0 0x60 TxSta2: 0000 0000 00 0 0x61 0000 0000 00 0 0x62 TxSta0: 0000 0000 2e 46 Transmitter: End of Tx status registers 22 34 state: 010 - Idler 25 37 state: 101 - Transmitter: S-Packet 00 0 28 40 Reset_hard: Done holding Eth. Ctrl. reset pin ------------ 50 80 IRQ: INT0 0001_0000 - Oscillator init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 29 41 Reset_hard: Done! Wrote to all Eth. Ctrl. config. regs 25 37 state: 101 - Transmitter: S-Packet 77 119 2d 45 Transmitter: Beginning Tx status check... 00 0 0x57 TxEnd: 0000 0000 00 0 0x58 0000 0000 00 0 0x59 TxStart: 0000 0000 00 0 0x5a 0000 0000 f1 241 0x5b ->0x78-Phy1111 0001 00 0 0x5c TxSta6: 0000 0000 06 6 0x5d 0000 0110 00 0 0x5e TxSta4: 0000 0000 40 64 0x5f 0100 0000 00 0 0x60 TxSta2: 0000 0000 00 0 0x61 0000 0000 00 0 0x62 TxSta0: 0000 0000 2e 46 Transmitter: End of Tx status registers 22 34 state: 010 - Idler 77 119 00 0 28 40 Reset_hard: Done holding Eth. Ctrl. reset pin ------------ 50 80 IRQ: INT0 0001_0000 - Oscillator init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 29 41 Reset_hard: Done! Wrote to all Eth. Ctrl. config. regs 25 37 state: 101 - Transmitter: S-Packet 77 119 00 0 28 40 Reset_hard: Done holding Eth. Ctrl. reset pin ------------ 50 80 IRQ: INT0 0001_0000 - Oscillator init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 29 41 Reset_hard: Done! Wrote to all Eth. Ctrl. config. regs 25 37 state: 101 - Transmitter: S-Packet 77 119 00 0 28 40 Reset_hard: Done holding Eth. Ctrl. reset pin ------------ 50 80 IRQ: INT0 0001_0000 - Oscillator init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 29 41 Reset_hard: Done! Wrote to all Eth. Ctrl. config. regs 25 37 state: 101 - Transmitter: S-Packet 77 119 00 0 28 40 Reset_hard: Done holding Eth. Ctrl. reset pin ------------ 50 80 IRQ: INT0 0001_0000 - Oscillator init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 29 41 Reset_hard: Done! Wrote to all Eth. Ctrl. config. regs 25 37 state: 101 - Transmitter: S-Packet 77 119 00 0 28 40 Reset_hard: Done holding Eth. Ctrl. reset pin ------------ 50 80 IRQ: INT0 0001_0000 - Oscillator init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 29 41 Reset_hard: Done! Wrote to all Eth. Ctrl. config. regs 25 37 state: 101 - Transmitter: S-Packet 77 119 00 0 28 40 Reset_hard: Done holding Eth. Ctrl. reset pin ------------ 50 80 IRQ: INT0 0001_0000 - Oscillator init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 29 41 Reset_hard: Done! Wrote to all Eth. Ctrl. config. regs 25 37 state: 101 - Transmitter: S-Packet 77 119 00 0 28 40 Reset_hard: Done holding Eth. Ctrl. reset pin ------------ 50 80 IRQ: INT0 0001_0000 - Oscillator init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 29 41 Reset_hard: Done! Wrote to all Eth. Ctrl. config. regs 25 37 state: 101 - Transmitter: S-Packet 77 119 00 0 28 40 Reset_hard: Done holding Eth. Ctrl. reset pin ------------ 50 80 IRQ: INT0 0001_0000 - Oscillator init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 29 41 Reset_hard: Done! Wrote to all Eth. Ctrl. config. regs 25 37 state: 101 - Transmitter: S-Packet 77 119 00 0 28 40 Reset_hard: Done holding Eth. Ctrl. reset pin ------------ 50 80 IRQ: INT0 0001_0000 - Oscillator init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 29 41 Reset_hard: Done! Wrote to all Eth. Ctrl. config. regs 25 37 state: 101 - Transmitter: S-Packet 77 119 2d 45 Transmitter: Beginning Tx status check... 00 0 0x57 TxEnd: 0000 0000 00 0 0x58 0000 0000 00 0 0x59 TxStart: 0000 0000 00 0 0x5a 0000 0000 f1 241 0x5b ->0x78-Phy1111 0001 00 0 0x5c TxSta6: 0000 0000 06 6 0x5d 0000 0110 00 0 0x5e TxSta4: 0000 0000 40 64 0x5f 0100 0000 00 0 0x60 TxSta2: 0000 0000 00 0 0x61 0000 0000 00 0 0x62 TxSta0: 0000 0000 2e 46 Transmitter: End of Tx status registers 22 34 state: 010 - Idler 77 119 00 0 28 40 Reset_hard: Done holding Eth. Ctrl. reset pin ------------ 50 80 IRQ: INT0 0001_0000 - Oscillator init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 29 41 Reset_hard: Done! Wrote to all Eth. Ctrl. config. regs 25 37 state: 101 - Transmitter: S-Packet 77 119 00 0 28 40 Reset_hard: Done holding Eth. Ctrl. reset pin ------------ 50 80 IRQ: INT0 0001_0000 - Oscillator init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 29 41 Reset_hard: Done! Wrote to all Eth. Ctrl. config. regs 25 37 state: 101 - Transmitter: S-Packet 77 119 ff 255 2d 45 Transmitter: Beginning Tx status check... 00 0 0x57 TxEnd: 0000 0000 00 0 0x58 0000 0000 00 0 0x59 TxStart: 0000 0000 00 0 0x5a 0000 0000 f1 241 0x5b ->0x78-Phy1111 0001 00 0 0x5c TxSta6: 0000 0000 06 6 0x5d 0000 0110 00 0 0x5e TxSta4: 0000 0000 40 64 0x5f 0100 0000 00 0 0x60 TxSta2: 0000 0000 00 0 0x61 0000 0000 00 0 0x62 TxSta0: 0000 0000 2e 46 Transmitter: End of Tx status registers 22 34 state: 010 - Idler ff 255 00 0 28 40 Reset_hard: Done holding Eth. Ctrl. reset pin ------------ 50 80 IRQ: INT0 0001_0000 - Oscillator init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 29 41 Reset_hard: Done! Wrote to all Eth. Ctrl. config. regs 25 37 state: 101 - Transmitter: S-Packet 77 119 00 0 2d 45 Transmitter: Beginning Tx status check... 00 0 0x57 TxEnd: 0000 0000 00 0 0x58 0000 0000 00 0 0x59 TxStart: 0000 0000 00 0 0x5a 0000 0000 f1 241 0x5b ->0x78-Phy1111 0001 00 0 0x5c TxSta6: 0000 0000 06 6 0x5d 0000 0110 00 0 0x5e TxSta4: 0000 0000 40 64 0x5f 0100 0000 00 0 0x60 TxSta2: 0000 0000 00 0 0x61 0000 0000 00 0 0x62 TxSta0: 0000 0000 2e 46 Transmitter: End of Tx status registers 22 34 state: 010 - Idler 00 0 00 0 28 40 Reset_hard: Done holding Eth. Ctrl. reset pin ------------ 50 80 IRQ: INT0 0001_0000 - Oscillator init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 29 41 Reset_hard: Done! Wrote to all Eth. Ctrl. config. regs 25 37 state: 101 - Transmitter: S-Packet 77 119 00 0 00 0 2d 45 Transmitter: Beginning Tx status check... 00 0 0x57 TxEnd: 0000 0000 00 0 0x58 0000 0000 00 0 0x59 TxStart: 0000 0000 00 0 0x5a 0000 0000 f1 241 0x5b ->0x78-Phy1111 0001 00 0 0x5c TxSta6: 0000 0000 06 6 0x5d 0000 0110 00 0 0x5e TxSta4: 0000 0000 40 64 0x5f 0100 0000 00 0 0x60 TxSta2: 0000 0000 00 0 0x61 0000 0000 00 0 0x62 TxSta0: 0000 0000 2e 46 Transmitter: End of Tx status registers 22 34 state: 010 - Idler 00 0 00 0 28 40 Reset_hard: Done holding Eth. Ctrl. reset pin ------------ 50 80 IRQ: INT0 0001_0000 - Oscillator init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 29 41 Reset_hard: Done! Wrote to all Eth. Ctrl. config. regs 25 37 state: 101 - Transmitter: S-Packet 77 119 00 0 00 0 2d 45 Transmitter: Beginning Tx status check... 00 0 0x57 TxEnd: 0000 0000 00 0 0x58 0000 0000 00 0 0x59 TxStart: 0000 0000 00 0 0x5a 0000 0000 f1 241 0x5b ->0x78-Phy1111 0001 00 0 0x5c TxSta6: 0000 0000 06 6 0x5d 0000 0110 00 0 0x5e TxSta4: 0000 0000 40 64 0x5f 0100 0000 00 0 0x60 TxSta2: 0000 0000 00 0 0x61 0000 0000 00 0 0x62 TxSta0: 0000 0000 2e 46 Transmitter: End of Tx status registers 22 34 state: 010 - Idler 00 0 00 0 28 40 Reset_hard: Done holding Eth. Ctrl. reset pin ------------ 50 80 IRQ: INT0 0001_0000 - Oscillator init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 35 53 29 41 Reset_hard: Done! Wrote to all Eth. Ctrl. config. regs 25 37 state: 101 - Transmitter: S-Packet 77 119 00 0 00 0 2d 45 Transmitter: Beginning Tx status check... 00 0 0x57 TxEnd: 0000 0000 00 0 0x58 0000 0000 00 0 0x59 TxStart: 0000 0000 00 0 0x5a 0000 0000 f1 241 0x5b ->0x78-Phy1111 0001 00 0 0x5c TxSta6: 0000 0000 06 6 0x5d 0000 0110 00 0 0x5e TxSta4: 0000 0000 40 64 0x5f 0100 0000 00 0 0x60 TxSta2: 0000 0000 00 0 0x61 0000 0000 00 0 0x62 TxSta0: 0000 0000 2e 46 Transmitter: End of Tx status registers 22 34 state: 010 - Idler 00 0 00 0 28 40 Reset_hard: Done holding Eth. Ctrl. reset pin ------------ 50 80 IRQ: INT0 0001_0000 - Oscillator init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 35 53 29 41 Reset_hard: Done! Wrote to all Eth. Ctrl. config. regs 25 37 state: 101 - Transmitter: S-Packet 77 119 00 0 3f 63 00 0 00 0 00 0 00 0 f1 241 00 0 06 6 00 0 40 64 00 0 00 0 00 0 2e 46 Transmitter: End of Tx status registers 22 34 state: 010 - Idler 00 0 00 0 28 40 Reset_hard: Done holding Eth. Ctrl. reset pin ------------ 50 80 IRQ: INT0 0001_0000 - Oscillator init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 35 53 29 41 Reset_hard: Done! Wrote to all Eth. Ctrl. config. regs 25 37 state: 101 - Transmitter: S-Packet 77 119 00 0 3f 63 00 0 40 64 00 0 40 64 f1 241 00 0 00 0 45 69 01 1 80 128 00 0 45 69 2e 46 Transmitter: End of Tx status registers 22 34 state: 010 - Idler 00 0 00 0 28 40 Reset_hard: Done holding Eth. Ctrl. reset pin ------------ 50 80 IRQ: INT0 0001_0000 - Oscillator init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 35 53 29 41 Reset_hard: Done! Wrote to all Eth. Ctrl. config. regs 25 37 state: 101 - Transmitter: S-Packet 77 119 40 64 2f 47 00 0 40 64 00 0 40 64 f1 241 00 0 00 0 45 69 00 0 80 128 00 0 45 69 2e 46 Transmitter: End of Tx status registers 22 34 state: 010 - Idler 40 64 00 0 28 40 Reset_hard: Done holding Eth. Ctrl. reset pin ------------ 50 80 IRQ: INT0 0001_0000 - Oscillator init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 35 53 29 41 Reset_hard: Done! Wrote to all Eth. Ctrl. config. regs 25 37 state: 101 - Transmitter: S-Packet 77 119 40 64 3f 63 00 0 40 64 00 0 40 64 f1 241 00 0 00 0 45 69 00 0 80 128 00 0 45 69 2e 46 Transmitter: End of Tx status registers 22 34 state: 010 - Idler 40 64 00 0 28 40 Reset_hard: Done holding Eth. Ctrl. reset pin ------------ 50 80 IRQ: INT0 0001_0000 - Oscillator init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 35 53 29 41 Reset_hard: Done! Wrote to all Eth. Ctrl. config. regs 25 37 state: 101 - Transmitter: S-Packet 77 119 40 64 2f 47 00 0 40 64 00 0 40 64 f1 241 00 0 00 0 45 69 00 0 80 128 00 0 45 69 2e 46 Transmitter: End of Tx status registers 22 34 state: 010 - Idler 40 64 00 0 28 40 Reset_hard: Done holding Eth. Ctrl. reset pin ------------ 50 80 IRQ: INT0 0001_0000 - Oscillator init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 35 53 29 41 Reset_hard: Done! Wrote to all Eth. Ctrl. config. regs 25 37 state: 101 - Transmitter: S-Packet 40 64 2d 45 Transmitter: Beginning Tx status check... 00 0 0x57 TxEnd: 0000 0000 40 64 0x58 0100 0000 00 0 0x59 TxStart: 0000 0000 40 64 0x5a 0100 0000 f1 241 0x5b ->0x78-Phy1111 0001 00 0 0x5c TxSta6: 0000 0000 00 0 0x5d 0000 0000 45 69 0x5e TxSta4: 0100 0101 01 1 0x5f 0000 0001 80 128 0x60 TxSta2: 1000 0000 00 0 0x61 0000 0000 45 69 0x62 TxSta0: 0100 0101 2e 46 Transmitter: End of Tx status registers 22 34 state: 010 - Idler 40 64 00 0 28 40 Reset_hard: Done holding Eth. Ctrl. reset pin ------------ 50 80 IRQ: INT0 0001_0000 - Oscillator init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 35 53 29 41 Reset_hard: Done! Wrote to all Eth. Ctrl. config. regs 25 37 state: 101 - Transmitter: S-Packet 40 64 2d 45 Transmitter: Beginning Tx status check... 00 0 0x57 TxEnd: 0000 0000 40 64 0x58 0100 0000 00 0 0x59 TxStart: 0000 0000 40 64 0x5a 0100 0000 f1 241 0x5b ->0x78-Phy1111 0001 00 0 0x5c TxSta6: 0000 0000 00 0 0x5d 0000 0000 45 69 0x5e TxSta4: 0100 0101 01 1 0x5f 0000 0001 80 128 0x60 TxSta2: 1000 0000 00 0 0x61 0000 0000 45 69 0x62 TxSta0: 0100 0101 2e 46 Transmitter: End of Tx status registers 22 34 state: 010 - Idler 40 64 00 0 28 40 Reset_hard: Done holding Eth. Ctrl. reset pin ------------ 50 80 IRQ: INT0 0001_0000 - Oscillator init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 35 53 29 41 Reset_hard: Done! Wrote to all Eth. Ctrl. config. regs 25 37 state: 101 - Transmitter: S-Packet 40 64 2d 45 Transmitter: Beginning Tx status check... 00 0 0x57 TxEnd: 0000 0000 40 64 0x58 0100 0000 00 0 0x59 TxStart: 0000 0000 40 64 0x5a 0100 0000 f1 241 0x5b ->0x78-Phy1111 0001 00 0 0x5c TxSta6: 0000 0000 00 0 0x5d 0000 0000 45 69 0x5e TxSta4: 0100 0101 00 0 0x5f 0000 0000 c0 192 0x60 TxSta2: 1100 0000 00 0 0x61 0000 0000 45 69 0x62 TxSta0: 0100 0101 2e 46 Transmitter: End of Tx status registers 22 34 state: 010 - Idler 40 64 00 0 28 40 Reset_hard: Done holding Eth. Ctrl. reset pin ------------ 50 80 IRQ: INT0 0001_0000 - Oscillator init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 35 53 29 41 Reset_hard: Done! Wrote to all Eth. Ctrl. config. regs 25 37 state: 101 - Transmitter: S-Packet 40 64 2d 45 Transmitter: Beginning Tx status check... 00 0 0x57 TxEnd: 0000 0000 40 64 0x58 0100 0000 00 0 0x59 TxStart: 0000 0000 40 64 0x5a 0100 0000 f1 241 0x5b ->0x78-Phy1111 0001 00 0 0x5c TxSta6: 0000 0000 00 0 0x5d 0000 0000 45 69 0x5e TxSta4: 0100 0101 00 0 0x5f 0000 0000 28 40 0x60 TxSta2: 0010 1000 50 80 0x61 0101 0000 60 96 0x62 TxSta0: 0110 0000 35 53 29 41 Reset_hard: Done! Wrote to all Eth. Ctrl. config. regs 25 37 state: 101 - Transmitter: S-Packet 40 64 2d 45 Transmitter: Beginning Tx status check... 00 0 0x57 TxEnd: 0000 0000 40 64 0x58 0100 0000 00 0 0x59 TxStart: 0000 0000 40 64 0x5a 0100 0000 f1 241 0x5b ->0x78-Phy1111 0001 00 0 0x5c TxSta6: 0000 0000 00 0 0x5d 0000 0000 45 69 0x5e TxSta4: 0100 0101 00 0 0x5f 0000 0000 c0 192 0x60 TxSta2: 1100 0000 00 0 0x61 0000 0000 45 69 0x62 TxSta0: 0100 0101 2e 46 Transmitter: End of Tx status registers 22 34 state: 010 - Idler 40 64 00 0 28 40 Reset_hard: Done holding Eth. Ctrl. reset pin ------------ 50 80 IRQ: INT0 0001_0000 - Oscillator init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 35 53 29 41 Reset_hard: Done! Wrote to all Eth. Ctrl. config. regs 25 37 state: 101 - Transmitter: S-Packet 40 64 2d 45 Transmitter: Beginning Tx status check... 00 0 0x57 TxEnd: 0000 0000 40 64 0x58 0100 0000 00 0 0x59 TxStart: 0000 0000 40 64 0x5a 0100 0000 f1 241 0x5b ->0x78-Phy1111 0001 00 0 0x5c TxSta6: 0000 0000 00 0 0x5d 0000 0000 45 69 0x5e TxSta4: 0100 0101 00 0 0x5f 0000 0000 c0 192 0x60 TxSta2: 1100 0000 00 0 0x61 0000 0000 45 69 0x62 TxSta0: 0100 0101 2e 46 Transmitter: End of Tx status registers 22 34 state: 010 - Idler 40 64 00 0 28 40 Reset_hard: Done holding Eth. Ctrl. reset pin ------------ 50 80 IRQ: INT0 0001_0000 - Oscillator init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 35 53 29 41 Reset_hard: Done! Wrote to all Eth. Ctrl. config. regs 25 37 state: 101 - Transmitter: S-Packet 40 64 2d 45 Transmitter: Beginning Tx status check... 00 0 0x57 TxEnd: 0000 0000 40 64 0x58 0100 0000 00 0 0x59 TxStart: 0000 0000 40 64 0x5a 0100 0000 f1 241 0x5b ->0x78-Phy1111 0001 00 0 0x5c TxSta6: 0000 0000 00 0 0x5d 0000 0000 45 69 0x5e TxSta4: 0100 0101 00 0 0x5f 0000 0000 c0 192 0x60 TxSta2: 1100 0000 00 0 0x61 0000 0000 45 69 0x62 TxSta0: 0100 0101 2e 46 Transmitter: End of Tx status registers 22 34 state: 010 - Idler 40 64 00 0 28 40 Reset_hard: Done holding Eth. Ctrl. reset pin ------------ 50 80 IRQ: INT0 0001_0000 - Oscillator init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 35 53 29 41 Reset_hard: Done! Wrote to all Eth. Ctrl. config. regs 25 37 state: 101 - Transmitter: S-Packet 40 64 2d 45 Transmitter: Beginning Tx status check... 00 0 0x57 TxEnd: 0000 0000 28 40 0x58 0010 1000 50 80 0x59 TxStart: 0101 0000 60 96 0x5a 0110 0000 35 53 0x5b ->0x78-Phy0011 0101 29 41 0x5c TxSta6: 0010 1001 25 37 0x5d 0010 0101 40 64 0x5e TxSta4: 0100 0000 2d 45 0x5f 0010 1101 00 0 0x60 TxSta2: 0000 0000 40 64 0x61 0100 0000 00 0 0x62 TxSta0: 0000 0000 40 64 f1 241 00 0 00 0 45 69 00 0 c0 192 00 0 45 69 2e 46 Transmitter: End of Tx status registers 22 34 state: 010 - Idler 40 64 00 0 28 40 Reset_hard: Done holding Eth. Ctrl. reset pin ------------ 50 80 IRQ: INT0 0001_0000 - Oscillator init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 35 53 29 41 Reset_hard: Done! Wrote to all Eth. Ctrl. config. regs 25 37 state: 101 - Transmitter: S-Packet 40 64 2d 45 Transmitter: Beginning Tx status check... 00 0 0x57 TxEnd: 0000 0000 40 64 0x58 0100 0000 00 0 0x59 TxStart: 0000 0000 40 64 0x5a 0100 0000 f1 241 0x5b ->0x78-Phy1111 0001 00 0 0x5c TxSta6: 0000 0000 00 0 0x5d 0000 0000 45 69 0x5e TxSta4: 0100 0101 00 0 0x5f 0000 0000 c0 192 0x60 TxSta2: 1100 0000 00 0 0x61 0000 0000 45 69 0x62 TxSta0: 0100 0101 2f 47 45 69 40 64 00 0 28 40 Reset_hard: Done holding Eth. Ctrl. reset pin ------------ 50 80 IRQ: INT0 0001_0000 - Oscillator init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 35 53 29 41 Reset_hard: Done! Wrote to all Eth. Ctrl. config. regs 25 37 state: 101 - Transmitter: S-Packet 40 64 2d 45 Transmitter: Beginning Tx status check... 00 0 0x57 TxEnd: 0000 0000 40 64 0x58 0100 0000 00 0 0x59 TxStart: 0000 0000 40 64 0x5a 0100 0000 f1 241 0x5b ->0x78-Phy1111 0001 00 0 0x5c TxSta6: 0000 0000 00 0 0x5d 0000 0000 45 69 0x5e TxSta4: 0100 0101 00 0 0x5f 0000 0000 c0 192 0x60 TxSta2: 1100 0000 00 0 0x61 0000 0000 45 69 0x62 TxSta0: 0100 0101 2f 47 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 22 34 state: 010 - Idler 08 8 00 0 28 40 Reset_hard: Done holding Eth. Ctrl. reset pin ------------ 50 80 IRQ: INT0 0001_0000 - Oscillator init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 35 53 29 41 Reset_hard: Done! Wrote to all Eth. Ctrl. config. regs 25 37 state: 101 - Transmitter: S-Packet 40 64 2d 45 Transmitter: Beginning Tx status check... 00 0 0x57 TxEnd: 0000 0000 40 64 0x58 0100 0000 00 0 0x59 TxStart: 0000 0000 40 64 0x5a 0100 0000 f1 241 0x5b ->0x78-Phy1111 0001 00 0 0x5c TxSta6: 0000 0000 00 0 0x5d 0000 0000 45 69 0x5e TxSta4: 0100 0101 00 0 0x5f 0000 0000 c0 192 0x60 TxSta2: 1100 0000 00 0 0x61 0000 0000 45 69 0x62 TxSta0: 0100 0101 2f 47 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 00 0 28 40 Reset_hard: Done holding Eth. Ctrl. reset pin ------------ 50 80 IRQ: INT0 0001_0000 - Oscillator init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 35 53 29 41 Reset_hard: Done! Wrote to all Eth. Ctrl. config. regs 25 37 state: 101 - Transmitter: S-Packet 40 64 2d 45 Transmitter: Beginning Tx status check... 00 0 0x57 TxEnd: 0000 0000 40 64 0x58 0100 0000 00 0 0x59 TxStart: 0000 0000 40 64 0x5a 0100 0000 f1 241 0x5b ->0x78-Phy1111 0001 00 0 0x5c TxSta6: 0000 0000 00 0 0x5d 0000 0000 45 69 0x5e TxSta4: 0100 0101 00 0 0x5f 0000 0000 c0 192 0x60 TxSta2: 1100 0000 00 0 0x61 0000 0000 45 69 0x62 TxSta0: 0100 0101 2f 47 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 00 0 28 40 Reset_hard: Done holding Eth. Ctrl. reset pin ------------ 50 80 IRQ: INT0 0001_0000 - Oscillator init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 35 53 29 41 Reset_hard: Done! Wrote to all Eth. Ctrl. config. regs 25 37 state: 101 - Transmitter: S-Packet 40 64 2d 45 Transmitter: Beginning Tx status check... 00 0 0x57 TxEnd: 0000 0000 40 64 0x58 0100 0000 00 0 0x59 TxStart: 0000 0000 40 64 0x5a 0100 0000 f1 241 0x5b ->0x78-Phy1111 0001 00 0 0x5c TxSta6: 0000 0000 00 0 0x5d 0000 0000 45 69 0x5e TxSta4: 0100 0101 00 0 0x5f 0000 0000 c0 192 0x60 TxSta2: 1100 0000 00 0 0x61 0000 0000 45 69 0x62 TxSta0: 0100 0101 2f 47 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 4d 77 4d 77 4d 77 4d 77 4d 77 4d 77 4d 77 4d 77 4d 77 4d 77 4d 77 4d 77 4d 77 4d 77 4d 77 4d 77 4d 77 4d 77 4d 77 4d 77 4d 77 4d 77 4d 77 4d 77 4d 77 4d 77 4d 77 4d 77 4d 77 4d 77 4d 77 4d 77 4d 77 4d 77 4d 77 4d 77 4d 77 4d 77 4d 77 4d 77 4d 77 4d 77 4d 77 4d 77 4d 77 4d 77 4d 77 4d 77 4d 77 4d 77 4d 77 4d 77 4d 77 4d 77 4d 77 4d 77 4d 77 4d 77 4d 77 4d 77 4d 77 4d 77 4d 77 4d 77 4d 77 4d 77 4d 77 4d 77 4d 77 4d 77 4d 77 4d 77 4d 77 4d 77 4d 77 4d 77 4d 77 4d 77 4d 77 4d 77 4d 77 4d 77 4d 77 4d 77 4d 77 4d 77 4d 77 4d 77 4d 77 4d 77 4d 77 4d 77 4d 77 4d 77 4d 77 4d 77 4d 77 4d 77 4d 77 4d 77 4d 77 4d 77 4d 77 4d 77 4d 77 4d 77 4d 77 4d 77 4d 77 4d 77 4d 77 4d 77 4d 77 4d 77 4d 77 4d 77 4d 77 4d 77 4d 77 4d 77 4d 77 4d 77 4d 77 4d 77 4d 77 4d 77 4d 77 4d 77 4d 77 4d 77 4d 77 4d 77 4d 77 4d 77 4d 77 4d 77 4d 77 4d 77 4d 77 4d 77 4d 77 4d 77 4d 77 4d 77 4d 77 4d 77 4d 77 4d 77 4d 77 4d 77 4d 77 4d 77 4d 77 4d 77 4d 77 4d 77 4d 77 4d 77 4d 77 4d 77 4d 77 4d 77 4d 77 4d 77 4d 77 4d 77 4d 77 4d 77 4d 77 4d 77 4d 77 4d 77 4d 77 4d 77 4d 77 4d 77 4d 77 4d 77 4d 77 4d 77 4d 77 4d 77 4d 77 4d 77 4d 77 4d 77 4d 77 4d 77 4d 77 4d 77 4d 77 4d 77 4d 77 4d 77 4d 77 4d 77 4d 77 4d 77 4d 77 4d 77 4d 77 4d 77 4d 77 4d 77 4d 77 4d 77 4d 77 4d 77 4d 77 4d 77 4d 77 4d 77 4d 77 4d 77 4d 77 4d 77 4d 77 4d 77 4d 77 4d 77 4d 77 4d 77 4d 77 4d 77 4d 77 4d 77 4d 77 4d 77 4d 77 4d 77 4d 77 4d 77 4d 77 4d 77 4d 77 4d 77 4d 77 4d 77 4d 77 4d 77 4d 77 4d 77 4d 77 4d 77 4d 77 4d 77 4d 77 4d 77 4d 77 4d 77 4d 77 4d 77 4d 77 4d 77 4d 77 4d 77 ff 255 ff 255 ff 255 ff 255 ff 255 ff 255 ff 255 ff 255 ff 255 ff 255 ff 255 ff 255 ff 255 ff 255 ff 255 ff 255 ff 255 ff 255 ff 255 ff 255 ff 255 ff 255 ff 255 ff 255 ff 255 ff 255 ff 255 ff 255 ff 255 ff 255 ff 255 ff 255 ff 255 ff 255 ff 255 ff 255 ff 255 ff 255 ff 255 ff 255 ff 255 ff 255 ff 255 ff 255 ff 255 ff 255 ff 255 ff 255 ff 255 ff 255 ff 255 ff 255 ff 255 ff 255 ff 255 ff 255 ff 255 ff 255 ff 255 ff 255 ff 255 ff 255 ff 255 ff 255 ff 255 ff 255 ff 255 ff 255 ff 255 ff 255 ff 255 ff 255 ff 255 ff 255 ff 255 ff 255 ff 255 ff 255 ff 255 ff 255 ff 255 ff 255 ff 255 ff 255 ff 255 ff 255 ff 255 ff 255 ff 255 ff 255 ff 255 ff 255 ff 255 ff 255 ff 255 ff 255 ff 255 ff 255 ff 255 ff 255 ff 255 ff 255 ff 255 ff 255 ff 255 ff 255 ff 255 ff 255 ff 255 ff 255 ff 255 ff 255 ff 255 ff 255 ff 255 ff 255 ff 255 ff 255 ff 255 ff 255 ff 255 ff 255 ff 255 ff 255 ff 255 ff 255 ff 255 ff 255 ff 255 ff 255 ff 255 ff 255 ff 255 ff 255 ff 255 ff 255 ff 255 ff 255 ff 255 ff 255 ff 255 ff 255 ff 255 ff 255 ff 255 ff 255 ff 255 ff 255 ff 255 ff 255 ff 255 ff 255 ff 255 ff 255 ff 255 ff 255 ff 255 ff 255 ff 255 ff 255 ff 255 ff 255 ff 255 ff 255 ff 255 ff 255 ff 255 ff 255 ff 255 ff 255 ff 255 ff 255 ff 255 ff 255 ff 255 ff 255 ff 255 ff 255 ff 255 ff 255 ff 255 ff 255 ff 255 ff 255 ff 255 ff 255 ff 255 ff 255 ff 255 ff 255 ff 255 ff 255 ff 255 ff 255 ff 255 ff 255 ff 255 ff 255 ff 255 ff 255 ff 255 ff 255 ff 255 ff 255 ff 255 ff 255 ff 255 ff 255 ff 255 ff 255 ff 255 ff 255 ff 255 ff 255 ff 255 ff 255 ff 255 ff 255 ff 255 ff 255 ff 255 ff 255 ff 255 ff 255 ff 255 ff 255 ff 255 ff 255 ff 255 ff 255 ff 255 ff 255 ff 255 ff 255 ff 255 ff 255 ff 255 ff 255 ff 255 ff 255 ff 255 ff 255 ff 255 ff 255 ff 255 ff 255 ff 255 ff 255 ff 255 ff 255 ff 255 ff 255 ff 255 ff 255 ff 255 ff 255 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 41 65 IRQ: INT0 0000_0001 - Packet received 41 65 IRQ: INT0 0000_0001 - Packet received 41 65 IRQ: INT0 0000_0001 - Packet received 41 65 IRQ: INT0 0000_0001 - Packet received 41 65 IRQ: INT0 0000_0001 - Packet received 41 65 IRQ: INT0 0000_0001 - Packet received 41 65 IRQ: INT0 0000_0001 - Packet received 41 65 IRQ: INT0 0000_0001 - Packet received 41 65 IRQ: INT0 0000_0001 - Packet received 41 65 IRQ: INT0 0000_0001 - Packet received 41 65 IRQ: INT0 0000_0001 - Packet received 41 65 IRQ: INT0 0000_0001 - Packet received 41 65 IRQ: INT0 0000_0001 - Packet received 41 65 IRQ: INT0 0000_0001 - Packet received 41 65 IRQ: INT0 0000_0001 - Packet received 41 65 IRQ: INT0 0000_0001 - Packet received 41 65 IRQ: INT0 0000_0001 - Packet received 41 65 IRQ: INT0 0000_0001 - Packet received 41 65 IRQ: INT0 0000_0001 - Packet received 41 65 IRQ: INT0 0000_0001 - Packet received 41 65 IRQ: INT0 0000_0001 - Packet received 41 65 IRQ: INT0 0000_0001 - Packet received 41 65 IRQ: INT0 0000_0001 - Packet received 41 65 IRQ: INT0 0000_0001 - Packet received 41 65 IRQ: INT0 0000_0001 - Packet received 41 65 IRQ: INT0 0000_0001 - Packet received 41 65 IRQ: INT0 0000_0001 - Packet received 41 65 IRQ: INT0 0000_0001 - Packet received 41 65 IRQ: INT0 0000_0001 - Packet received 41 65 IRQ: INT0 0000_0001 - Packet received 41 65 IRQ: INT0 0000_0001 - Packet received 41 65 IRQ: INT0 0000_0001 - Packet received 41 65 IRQ: INT0 0000_0001 - Packet received 41 65 IRQ: INT0 0000_0001 - Packet received 41 65 IRQ: INT0 0000_0001 - Packet received 41 65 IRQ: INT0 0000_0001 - Packet received 41 65 IRQ: INT0 0000_0001 - Packet received 41 65 IRQ: INT0 0000_0001 - Packet received 41 65 IRQ: INT0 0000_0001 - Packet received 41 65 IRQ: INT0 0000_0001 - Packet received 41 65 IRQ: INT0 0000_0001 - Packet received 41 65 IRQ: INT0 0000_0001 - Packet received 41 65 IRQ: INT0 0000_0001 - Packet received 41 65 IRQ: INT0 0000_0001 - Packet received 41 65 IRQ: INT0 0000_0001 - Packet received 41 65 IRQ: INT0 0000_0001 - Packet received 41 65 IRQ: INT0 0000_0001 - Packet received 41 65 IRQ: INT0 0000_0001 - Packet received 41 65 IRQ: INT0 0000_0001 - Packet received 41 65 IRQ: INT0 0000_0001 - Packet received 41 65 IRQ: INT0 0000_0001 - Packet received 41 65 IRQ: INT0 0000_0001 - Packet received 41 65 IRQ: INT0 0000_0001 - Packet received 41 65 IRQ: INT0 0000_0001 - Packet received 41 65 IRQ: INT0 0000_0001 - Packet received 41 65 IRQ: INT0 0000_0001 - Packet received 41 65 IRQ: INT0 0000_0001 - Packet received 41 65 IRQ: INT0 0000_0001 - Packet received 41 65 IRQ: INT0 0000_0001 - Packet received 41 65 IRQ: INT0 0000_0001 - Packet received 41 65 IRQ: INT0 0000_0001 - Packet received 41 65 IRQ: INT0 0000_0001 - Packet received 41 65 IRQ: INT0 0000_0001 - Packet received 41 65 IRQ: INT0 0000_0001 - Packet received 41 65 IRQ: INT0 0000_0001 - Packet received 41 65 IRQ: INT0 0000_0001 - Packet received 41 65 IRQ: INT0 0000_0001 - Packet received 41 65 IRQ: INT0 0000_0001 - Packet received 41 65 IRQ: INT0 0000_0001 - Packet received 41 65 IRQ: INT0 0000_0001 - Packet received 41 65 IRQ: INT0 0000_0001 - Packet received 41 65 IRQ: INT0 0000_0001 - Packet received 41 65 IRQ: INT0 0000_0001 - Packet received 41 65 IRQ: INT0 0000_0001 - Packet received 41 65 IRQ: INT0 0000_0001 - Packet received 41 65 IRQ: INT0 0000_0001 - Packet received 41 65 IRQ: INT0 0000_0001 - Packet received 41 65 IRQ: INT0 0000_0001 - Packet received 41 65 IRQ: INT0 0000_0001 - Packet received 41 65 IRQ: INT0 0000_0001 - Packet received 41 65 IRQ: INT0 0000_0001 - Packet received 41 65 IRQ: INT0 0000_0001 - Packet received 41 65 IRQ: INT0 0000_0001 - Packet received 41 65 IRQ: INT0 0000_0001 - Packet received 41 65 IRQ: INT0 0000_0001 - Packet received 41 65 IRQ: INT0 0000_0001 - Packet received 41 65 IRQ: INT0 0000_0001 - Packet received 41 65 IRQ: INT0 0000_0001 - Packet received 41 65 IRQ: INT0 0000_0001 - Packet received 41 65 IRQ: INT0 0000_0001 - Packet received 41 65 IRQ: INT0 0000_0001 - Packet received 41 65 IRQ: INT0 0000_0001 - Packet received 41 65 IRQ: INT0 0000_0001 - Packet received 41 65 IRQ: INT0 0000_0001 - Packet received 41 65 IRQ: INT0 0000_0001 - Packet received 41 65 IRQ: INT0 0000_0001 - Packet received 41 65 IRQ: INT0 0000_0001 - Packet received 41 65 IRQ: INT0 0000_0001 - Packet received 41 65 IRQ: INT0 0000_0001 - Packet received 41 65 IRQ: INT0 0000_0001 - Packet received 41 65 IRQ: INT0 0000_0001 - Packet received 41 65 IRQ: INT0 0000_0001 - Packet received 41 65 IRQ: INT0 0000_0001 - Packet received 41 65 IRQ: INT0 0000_0001 - Packet received 41 65 IRQ: INT0 0000_0001 - Packet received 41 65 IRQ: INT0 0000_0001 - Packet received 41 65 IRQ: INT0 0000_0001 - Packet received 41 65 IRQ: INT0 0000_0001 - Packet received 41 65 IRQ: INT0 0000_0001 - Packet received 41 65 IRQ: INT0 0000_0001 - Packet received 41 65 IRQ: INT0 0000_0001 - Packet received 41 65 IRQ: INT0 0000_0001 - Packet received 41 65 IRQ: INT0 0000_0001 - Packet received 41 65 IRQ: INT0 0000_0001 - Packet received 41 65 IRQ: INT0 0000_0001 - Packet received 41 65 IRQ: INT0 0000_0001 - Packet received 41 65 IRQ: INT0 0000_0001 - Packet received 41 65 IRQ: INT0 0000_0001 - Packet received 41 65 IRQ: INT0 0000_0001 - Packet received 41 65 IRQ: INT0 0000_0001 - Packet received 41 65 IRQ: INT0 0000_0001 - Packet received 41 65 IRQ: INT0 0000_0001 - Packet received 41 65 IRQ: INT0 0000_0001 - Packet received 41 65 IRQ: INT0 0000_0001 - Packet received 41 65 IRQ: INT0 0000_0001 - Packet received 41 65 IRQ: INT0 0000_0001 - Packet received 41 65 IRQ: INT0 0000_0001 - Packet received 41 65 IRQ: INT0 0000_0001 - Packet received 41 65 IRQ: INT0 0000_0001 - Packet received 41 65 IRQ: INT0 0000_0001 - Packet received 41 65 IRQ: INT0 0000_0001 - Packet received 41 65 IRQ: INT0 0000_0001 - Packet received 41 65 IRQ: INT0 0000_0001 - Packet received 41 65 IRQ: INT0 0000_0001 - Packet received 41 65 IRQ: INT0 0000_0001 - Packet received 41 65 IRQ: INT0 0000_0001 - Packet received 41 65 IRQ: INT0 0000_0001 - Packet received 41 65 IRQ: INT0 0000_0001 - Packet received 41 65 IRQ: INT0 0000_0001 - Packet received 41 65 IRQ: INT0 0000_0001 - Packet received 41 65 IRQ: INT0 0000_0001 - Packet received 41 65 IRQ: INT0 0000_0001 - Packet received 41 65 IRQ: INT0 0000_0001 - Packet received 41 65 IRQ: INT0 0000_0001 - Packet received 41 65 IRQ: INT0 0000_0001 - Packet received 41 65 IRQ: INT0 0000_0001 - Packet received 41 65 IRQ: INT0 0000_0001 - Packet received 41 65 IRQ: INT0 0000_0001 - Packet received 41 65 IRQ: INT0 0000_0001 - Packet received 41 65 IRQ: INT0 0000_0001 - Packet received 41 65 IRQ: INT0 0000_0001 - Packet received 41 65 IRQ: INT0 0000_0001 - Packet received 41 65 IRQ: INT0 0000_0001 - Packet received 41 65 IRQ: INT0 0000_0001 - Packet received 41 65 IRQ: INT0 0000_0001 - Packet received 41 65 IRQ: INT0 0000_0001 - Packet received 41 65 IRQ: INT0 0000_0001 - Packet received 41 65 IRQ: INT0 0000_0001 - Packet received 41 65 IRQ: INT0 0000_0001 - Packet received 41 65 IRQ: INT0 0000_0001 - Packet received 41 65 IRQ: INT0 0000_0001 - Packet received 41 65 IRQ: INT0 0000_0001 - Packet received 41 65 IRQ: INT0 0000_0001 - Packet received 41 65 IRQ: INT0 0000_0001 - Packet received 41 65 IRQ: INT0 0000_0001 - Packet received 41 65 IRQ: INT0 0000_0001 - Packet received 41 65 IRQ: INT0 0000_0001 - Packet received 41 65 IRQ: INT0 0000_0001 - Packet received 41 65 IRQ: INT0 0000_0001 - Packet received 41 65 IRQ: INT0 0000_0001 - Packet received 41 65 IRQ: INT0 0000_0001 - Packet received 41 65 IRQ: INT0 0000_0001 - Packet received 41 65 IRQ: INT0 0000_0001 - Packet received 41 65 IRQ: INT0 0000_0001 - Packet received 41 65 IRQ: INT0 0000_0001 - Packet received 41 65 IRQ: INT0 0000_0001 - Packet received 41 65 IRQ: INT0 0000_0001 - Packet received 41 65 IRQ: INT0 0000_0001 - Packet received 41 65 IRQ: INT0 0000_0001 - Packet received 41 65 IRQ: INT0 0000_0001 - Packet received 41 65 IRQ: INT0 0000_0001 - Packet received 41 65 IRQ: INT0 0000_0001 - Packet received 41 65 IRQ: INT0 0000_0001 - Packet received 41 65 IRQ: INT0 0000_0001 - Packet received 41 65 IRQ: INT0 0000_0001 - Packet received 41 65 IRQ: INT0 0000_0001 - Packet received 41 65 IRQ: INT0 0000_0001 - Packet received 41 65 IRQ: INT0 0000_0001 - Packet received 41 65 IRQ: INT0 0000_0001 - Packet received 41 65 IRQ: INT0 0000_0001 - Packet received 41 65 IRQ: INT0 0000_0001 - Packet received 41 65 IRQ: INT0 0000_0001 - Packet received 41 65 IRQ: INT0 0000_0001 - Packet received 41 65 IRQ: INT0 0000_0001 - Packet received 41 65 IRQ: INT0 0000_0001 - Packet received 41 65 IRQ: INT0 0000_0001 - Packet received 41 65 IRQ: INT0 0000_0001 - Packet received 41 65 IRQ: INT0 0000_0001 - Packet received 41 65 IRQ: INT0 0000_0001 - Packet received 41 65 IRQ: INT0 0000_0001 - Packet received 41 65 IRQ: INT0 0000_0001 - Packet received 41 65 IRQ: INT0 0000_0001 - Packet received 41 65 IRQ: INT0 0000_0001 - Packet received 41 65 IRQ: INT0 0000_0001 - Packet received 41 65 IRQ: INT0 0000_0001 - Packet received 41 65 IRQ: INT0 0000_0001 - Packet received 41 65 IRQ: INT0 0000_0001 - Packet received 41 65 IRQ: INT0 0000_0001 - Packet received 41 65 IRQ: INT0 0000_0001 - Packet received 41 65 IRQ: INT0 0000_0001 - Packet received 41 65 IRQ: INT0 0000_0001 - Packet received 41 65 IRQ: INT0 0000_0001 - Packet received 41 65 IRQ: INT0 0000_0001 - Packet received 41 65 IRQ: INT0 0000_0001 - Packet received 41 65 IRQ: INT0 0000_0001 - Packet received 41 65 IRQ: INT0 0000_0001 - Packet received 41 65 IRQ: INT0 0000_0001 - Packet received 41 65 IRQ: INT0 0000_0001 - Packet received 41 65 IRQ: INT0 0000_0001 - Packet received 41 65 IRQ: INT0 0000_0001 - Packet received 41 65 IRQ: INT0 0000_0001 - Packet received 41 65 IRQ: INT0 0000_0001 - Packet received 41 65 IRQ: INT0 0000_0001 - Packet received 41 65 IRQ: INT0 0000_0001 - Packet received 41 65 IRQ: INT0 0000_0001 - Packet received 41 65 IRQ: INT0 0000_0001 - Packet received 41 65 IRQ: INT0 0000_0001 - Packet received 41 65 IRQ: INT0 0000_0001 - Packet received 41 65 IRQ: INT0 0000_0001 - Packet received 41 65 IRQ: INT0 0000_0001 - Packet received 41 65 IRQ: INT0 0000_0001 - Packet received 41 65 IRQ: INT0 0000_0001 - Packet received 41 65 IRQ: INT0 0000_0001 - Packet received 41 65 IRQ: INT0 0000_0001 - Packet received 41 65 IRQ: INT0 0000_0001 - Packet received 41 65 IRQ: INT0 0000_0001 - Packet received 41 65 IRQ: INT0 0000_0001 - Packet received 41 65 IRQ: INT0 0000_0001 - Packet received 41 65 IRQ: INT0 0000_0001 - Packet received 41 65 IRQ: INT0 0000_0001 - Packet received 41 65 IRQ: INT0 0000_0001 - Packet received 41 65 IRQ: INT0 0000_0001 - Packet received 41 65 IRQ: INT0 0000_0001 - Packet received 41 65 IRQ: INT0 0000_0001 - Packet received 41 65 IRQ: INT0 0000_0001 - Packet received 41 65 IRQ: INT0 0000_0001 - Packet received 41 65 IRQ: INT0 0000_0001 - Packet received 41 65 IRQ: INT0 0000_0001 - Packet received 41 65 IRQ: INT0 0000_0001 - Packet received 41 65 IRQ: INT0 0000_0001 - Packet received 41 65 IRQ: INT0 0000_0001 - Packet received 41 65 IRQ: INT0 0000_0001 - Packet received 41 65 IRQ: INT0 0000_0001 - Packet received 41 65 IRQ: INT0 0000_0001 - Packet received 41 65 IRQ: INT0 0000_0001 - Packet received 41 65 IRQ: INT0 0000_0001 - Packet received 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 be 190 be 190 be 190 be 190 be 190 be 190 be 190 be 190 be 190 be 190 be 190 be 190 be 190 be 190 be 190 be 190 be 190 be 190 be 190 be 190 be 190 be 190 be 190 be 190 be 190 be 190 be 190 be 190 be 190 be 190 be 190 be 190 be 190 be 190 be 190 be 190 be 190 be 190 be 190 be 190 be 190 be 190 be 190 be 190 be 190 be 190 be 190 be 190 be 190 be 190 be 190 be 190 be 190 be 190 be 190 be 190 be 190 be 190 be 190 be 190 be 190 be 190 be 190 be 190 be 190 be 190 be 190 be 190 be 190 be 190 be 190 be 190 be 190 be 190 be 190 be 190 be 190 be 190 be 190 be 190 be 190 be 190 be 190 be 190 be 190 be 190 be 190 be 190 be 190 be 190 be 190 be 190 be 190 be 190 be 190 be 190 be 190 be 190 be 190 be 190 be 190 be 190 be 190 be 190 be 190 be 190 be 190 be 190 be 190 be 190 be 190 be 190 be 190 be 190 be 190 be 190 be 190 be 190 be 190 be 190 be 190 be 190 be 190 be 190 be 190 be 190 be 190 be 190 be 190 be 190 be 190 be 190 be 190 be 190 be 190 be 190 be 190 be 190 be 190 be 190 be 190 be 190 be 190 be 190 be 190 be 190 be 190 be 190 be 190 be 190 be 190 be 190 be 190 be 190 be 190 be 190 be 190 be 190 be 190 be 190 be 190 be 190 be 190 be 190 be 190 be 190 be 190 be 190 be 190 be 190 be 190 be 190 be 190 be 190 be 190 be 190 be 190 be 190 be 190 be 190 be 190 be 190 be 190 be 190 be 190 be 190 be 190 be 190 be 190 be 190 be 190 be 190 be 190 be 190 be 190 be 190 be 190 be 190 be 190 be 190 be 190 be 190 be 190 be 190 be 190 be 190 be 190 be 190 be 190 be 190 be 190 be 190 be 190 be 190 be 190 be 190 be 190 be 190 be 190 be 190 be 190 be 190 be 190 be 190 be 190 be 190 be 190 be 190 be 190 be 190 be 190 be 190 be 190 be 190 be 190 be 190 be 190 be 190 be 190 be 190 be 190 be 190 be 190 be 190 be 190 be 190 be 190 be 190 be 190 be 190 be 190 be 190 be 190 be 190 22 34 state: 010 - Idler be 190 00 0 28 40 Reset_hard: Done holding Eth. Ctrl. reset pin ------------ 50 80 IRQ: INT0 0001_0000 - Oscillator init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 35 53 29 41 Reset_hard: Done! Wrote to all Eth. Ctrl. config. regs 25 37 state: 101 - Transmitter: S-Packet 40 64 2d 45 Transmitter: Beginning Tx status check... 00 0 0x57 TxEnd: 0000 0000 40 64 0x58 0100 0000 00 0 0x59 TxStart: 0000 0000 00 0 0x5a 0000 0000 28 40 0x5b ->0x78-Phy0010 1000 50 80 0x5c TxSta6: 0101 0000 60 96 0x5d 0110 0000 35 53 0x5e TxSta4: 0011 0101 29 41 0x5f 0010 1001 25 37 0x60 TxSta2: 0010 0101 40 64 0x61 0100 0000 2d 45 0x62 TxSta0: 0010 1101 00 0 40 64 00 0 40 64 f1 241 00 0 00 0 45 69 00 0 c0 192 00 0 45 69 2f 47 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 4c 76 4c 76 4c 76 4c 76 4c 76 4c 76 4c 76 4c 76 4c 76 4c 76 4c 76 4c 76 4c 76 4c 76 4c 76 4c 76 4c 76 4c 76 4c 76 4c 76 4c 76 4c 76 4c 76 4c 76 4c 76 4c 76 4c 76 4c 76 4c 76 4c 76 4c 76 4c 76 4c 76 4c 76 4c 76 4c 76 4c 76 4c 76 4c 76 4c 76 4c 76 4c 76 4c 76 4c 76 4c 76 4c 76 4c 76 4c 76 4c 76 4c 76 4c 76 4c 76 4c 76 4c 76 4c 76 4c 76 4c 76 4c 76 4c 76 4c 76 4c 76 4c 76 4c 76 4c 76 4c 76 4c 76 4c 76 4c 76 4c 76 4c 76 4c 76 4c 76 4c 76 4c 76 4c 76 4c 76 4c 76 4c 76 4c 76 4c 76 4c 76 4c 76 4c 76 4c 76 4c 76 4c 76 4c 76 4c 76 4c 76 4c 76 4c 76 4c 76 4c 76 4c 76 4c 76 4c 76 4c 76 4c 76 4c 76 4c 76 4c 76 4c 76 4c 76 4c 76 4c 76 4c 76 4c 76 4c 76 4c 76 4c 76 4c 76 4c 76 4c 76 4c 76 4c 76 4c 76 4c 76 4c 76 4c 76 4c 76 4c 76 4c 76 4c 76 4c 76 4c 76 4c 76 4c 76 4c 76 4c 76 4c 76 4c 76 4c 76 4c 76 4c 76 4c 76 4c 76 4c 76 4c 76 4c 76 4c 76 4c 76 4c 76 4c 76 4c 76 4c 76 4c 76 4c 76 4c 76 4c 76 4c 76 4c 76 4c 76 4c 76 4c 76 4c 76 4c 76 4c 76 4c 76 4c 76 4c 76 4c 76 4c 76 4c 76 4c 76 4c 76 4c 76 4c 76 4c 76 4c 76 4c 76 4c 76 4c 76 4c 76 4c 76 4c 76 4c 76 4c 76 4c 76 4c 76 4c 76 4c 76 4c 76 4c 76 4c 76 4c 76 4c 76 4c 76 4c 76 4c 76 4c 76 4c 76 4c 76 4c 76 4c 76 4c 76 4c 76 4c 76 4c 76 4c 76 4c 76 4c 76 4c 76 4c 76 4c 76 4c 76 4c 76 4c 76 4c 76 4c 76 4c 76 4c 76 4c 76 4c 76 4c 76 4c 76 4c 76 4c 76 4c 76 4c 76 4c 76 4c 76 4c 76 4c 76 4c 76 4c 76 4c 76 4c 76 4c 76 4c 76 4c 76 4c 76 4c 76 4c 76 4c 76 4c 76 4c 76 4c 76 4c 76 4c 76 4c 76 4c 76 4c 76 4c 76 4c 76 4c 76 4c 76 4c 76 4c 76 4c 76 4c 76 4c 76 4c 76 4c 76 4c 76 4c 76 4c 76 bb 187 bb 187 bb 187 bb 187 bb 187 bb 187 bb 187 bb 187 bb 187 bb 187 bb 187 bb 187 bb 187 bb 187 bb 187 bb 187 bb 187 bb 187 bb 187 bb 187 bb 187 bb 187 bb 187 bb 187 bb 187 bb 187 bb 187 bb 187 bb 187 bb 187 bb 187 bb 187 bb 187 bb 187 bb 187 bb 187 bb 187 bb 187 bb 187 bb 187 bb 187 bb 187 bb 187 bb 187 bb 187 bb 187 bb 187 bb 187 bb 187 bb 187 bb 187 bb 187 bb 187 bb 187 bb 187 bb 187 bb 187 bb 187 bb 187 bb 187 bb 187 bb 187 bb 187 bb 187 bb 187 bb 187 bb 187 bb 187 bb 187 bb 187 bb 187 bb 187 bb 187 bb 187 bb 187 bb 187 bb 187 bb 187 bb 187 bb 187 bb 187 bb 187 bb 187 bb 187 bb 187 bb 187 bb 187 bb 187 bb 187 bb 187 bb 187 bb 187 bb 187 bb 187 bb 187 bb 187 bb 187 bb 187 bb 187 bb 187 bb 187 bb 187 bb 187 bb 187 bb 187 bb 187 bb 187 bb 187 bb 187 bb 187 bb 187 bb 187 bb 187 bb 187 bb 187 bb 187 bb 187 bb 187 bb 187 bb 187 bb 187 bb 187 bb 187 bb 187 bb 187 bb 187 bb 187 bb 187 bb 187 bb 187 bb 187 bb 187 bb 187 bb 187 bb 187 bb 187 bb 187 bb 187 bb 187 bb 187 bb 187 bb 187 bb 187 bb 187 bb 187 bb 187 bb 187 bb 187 bb 187 bb 187 bb 187 bb 187 bb 187 bb 187 bb 187 bb 187 bb 187 bb 187 bb 187 bb 187 bb 187 bb 187 bb 187 bb 187 bb 187 bb 187 bb 187 bb 187 bb 187 bb 187 bb 187 bb 187 bb 187 bb 187 bb 187 bb 187 bb 187 bb 187 bb 187 bb 187 bb 187 bb 187 bb 187 bb 187 bb 187 bb 187 bb 187 bb 187 bb 187 bb 187 bb 187 bb 187 bb 187 bb 187 bb 187 bb 187 bb 187 bb 187 bb 187 bb 187 bb 187 bb 187 bb 187 bb 187 bb 187 bb 187 bb 187 bb 187 bb 187 bb 187 bb 187 bb 187 bb 187 bb 187 bb 187 bb 187 bb 187 bb 187 bb 187 bb 187 bb 187 bb 187 bb 187 bb 187 bb 187 bb 187 bb 187 bb 187 bb 187 bb 187 bb 187 bb 187 bb 187 bb 187 bb 187 bb 187 bb 187 bb 187 bb 187 bb 187 bb 187 bb 187 bb 187 bb 187 bb 187 bb 187 bb 187 bb 187 bb 187 bb 187 bb 187 bb 187 bb 187 bb 187 bb 187 bb 187 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 3e 62 c1 193 c1 193 c1 193 c1 193 c1 193 c1 193 c1 193 c1 193 c1 193 c1 193 c1 193 c1 193 c1 193 c1 193 c1 193 c1 193 c1 193 c1 193 c1 193 c1 193 c1 193 c1 193 c1 193 c1 193 c1 193 c1 193 c1 193 c1 193 c1 193 c1 193 c1 193 c1 193 c1 193 c1 193 c1 193 c1 193 c1 193 c1 193 c1 193 c1 193 c1 193 c1 193 c1 193 c1 193 c1 193 c1 193 c1 193 c1 193 c1 193 c1 193 c1 193 c1 193 c1 193 c1 193 c1 193 c1 193 c1 193 c1 193 c1 193 c1 193 c1 193 c1 193 c1 193 c1 193 c1 193 c1 193 c1 193 c1 193 c1 193 c1 193 c1 193 c1 193 c1 193 c1 193 c1 193 c1 193 c1 193 c1 193 c1 193 c1 193 c1 193 c1 193 c1 193 c1 193 c1 193 c1 193 c1 193 c1 193 c1 193 c1 193 c1 193 c1 193 c1 193 c1 193 c1 193 c1 193 c1 193 c1 193 c1 193 c1 193 c1 193 c1 193 c1 193 c1 193 c1 193 c1 193 c1 193 c1 193 c1 193 c1 193 c1 193 c1 193 c1 193 c1 193 c1 193 c1 193 c1 193 c1 193 c1 193 c1 193 c1 193 c1 193 c1 193 c1 193 c1 193 c1 193 c1 193 c1 193 c1 193 c1 193 c1 193 c1 193 c1 193 c1 193 c1 193 c1 193 c1 193 c1 193 c1 193 c1 193 c1 193 c1 193 c1 193 c1 193 c1 193 c1 193 c1 193 c1 193 c1 193 c1 193 c1 193 c1 193 c1 193 c1 193 c1 193 c1 193 c1 193 c1 193 c1 193 c1 193 c1 193 c1 193 c1 193 c1 193 c1 193 c1 193 c1 193 c1 193 c1 193 c1 193 c1 193 c1 193 c1 193 c1 193 c1 193 c1 193 c1 193 c1 193 c1 193 c1 193 c1 193 c1 193 c1 193 c1 193 c1 193 c1 193 c1 193 c1 193 c1 193 c1 193 c1 193 c1 193 c1 193 c1 193 c1 193 c1 193 c1 193 c1 193 c1 193 c1 193 c1 193 c1 193 c1 193 c1 193 c1 193 c1 193 c1 193 c1 193 c1 193 c1 193 c1 193 c1 193 c1 193 c1 193 c1 193 c1 193 c1 193 c1 193 c1 193 c1 193 c1 193 c1 193 c1 193 c1 193 c1 193 c1 193 c1 193 c1 193 c1 193 c1 193 c1 193 c1 193 c1 193 c1 193 c1 193 c1 193 c1 193 c1 193 c1 193 c1 193 c1 193 c1 193 c1 193 c1 193 c1 193 c1 193 c1 193 c1 193 c1 193 c1 193 c1 193 c1 193 c1 193 c1 193 c1 193 c1 193 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 ba 186 ba 186 ba 186 ba 186 ba 186 ba 186 ba 186 ba 186 ba 186 ba 186 ba 186 ba 186 ba 186 ba 186 ba 186 ba 186 ba 186 ba 186 ba 186 ba 186 ba 186 ba 186 ba 186 ba 186 ba 186 ba 186 ba 186 ba 186 ba 186 ba 186 ba 186 ba 186 ba 186 ba 186 ba 186 ba 186 ba 186 ba 186 ba 186 ba 186 ba 186 ba 186 ba 186 ba 186 ba 186 ba 186 ba 186 ba 186 ba 186 ba 186 ba 186 ba 186 ba 186 ba 186 ba 186 ba 186 ba 186 ba 186 ba 186 ba 186 ba 186 ba 186 ba 186 ba 186 ba 186 ba 186 ba 186 ba 186 ba 186 ba 186 ba 186 ba 186 ba 186 ba 186 ba 186 ba 186 ba 186 ba 186 ba 186 ba 186 ba 186 ba 186 ba 186 ba 186 ba 186 ba 186 ba 186 ba 186 ba 186 ba 186 ba 186 ba 186 ba 186 ba 186 ba 186 ba 186 ba 186 ba 186 ba 186 ba 186 ba 186 ba 186 ba 186 ba 186 ba 186 ba 186 ba 186 ba 186 ba 186 ba 186 ba 186 ba 186 ba 186 ba 186 ba 186 ba 186 ba 186 ba 186 ba 186 ba 186 ba 186 ba 186 ba 186 ba 186 ba 186 ba 186 ba 186 ba 186 ba 186 ba 186 ba 186 ba 186 ba 186 ba 186 ba 186 ba 186 ba 186 ba 186 ba 186 ba 186 ba 186 ba 186 ba 186 ba 186 ba 186 ba 186 ba 186 ba 186 ba 186 ba 186 ba 186 ba 186 ba 186 ba 186 ba 186 ba 186 ba 186 ba 186 ba 186 ba 186 ba 186 ba 186 ba 186 ba 186 ba 186 ba 186 ba 186 ba 186 ba 186 ba 186 ba 186 ba 186 ba 186 ba 186 ba 186 ba 186 ba 186 ba 186 ba 186 ba 186 ba 186 ba 186 ba 186 ba 186 ba 186 ba 186 ba 186 ba 186 ba 186 ba 186 ba 186 ba 186 ba 186 ba 186 ba 186 ba 186 ba 186 ba 186 ba 186 ba 186 ba 186 ba 186 ba 186 ba 186 ba 186 ba 186 ba 186 ba 186 ba 186 ba 186 ba 186 ba 186 ba 186 ba 186 ba 186 ba 186 ba 186 ba 186 ba 186 ba 186 ba 186 ba 186 ba 186 ba 186 ba 186 ba 186 ba 186 ba 186 ba 186 ba 186 ba 186 ba 186 ba 186 ba 186 ba 186 ba 186 ba 186 ba 186 ba 186 ba 186 ba 186 ba 186 ba 186 ba 186 ba 186 ba 186 ba 186 ba 186 ba 186 ba 186 ba 186 ba 186 ba 186 ba 186 22 34 state: 010 - Idler ba 186 00 0 28 40 Reset_hard: Done holding Eth. Ctrl. reset pin ------------ 50 80 IRQ: INT0 0001_0000 - Oscillator init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 35 53 29 41 Reset_hard: Done! Wrote to all Eth. Ctrl. config. regs 25 37 state: 101 - Transmitter: S-Packet 40 64 2d 45 Transmitter: Beginning Tx status check... 00 0 0x57 TxEnd: 0000 0000 40 64 0x58 0100 0000 00 0 0x59 TxStart: 0000 0000 40 64 0x5a 0100 0000 f1 241 0x5b ->0x78-Phy1111 0001 00 0 0x5c TxSta6: 0000 0000 00 0 0x5d 0000 0000 45 69 0x5e TxSta4: 0100 0101 00 0 0x5f 0000 0000 c0 192 0x60 TxSta2: 1100 0000 00 0 0x61 0000 0000 45 69 0x62 TxSta0: 0100 0101 2f 47 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 00 0 28 40 Reset_hard: Done holding Eth. Ctrl. reset pin ------------ 50 80 IRQ: INT0 0001_0000 - Oscillator init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 35 53 29 41 Reset_hard: Done! Wrote to all Eth. Ctrl. config. regs 25 37 state: 101 - Transmitter: S-Packet 40 64 2d 45 Transmitter: Beginning Tx status check... 00 0 0x57 TxEnd: 0000 0000 40 64 0x58 0100 0000 00 0 0x59 TxStart: 0000 0000 40 64 0x5a 0100 0000 00 0 0x5b ->0x78-Phy0000 0000 28 40 0x5c TxSta6: 0010 1000 50 80 0x5d 0101 0000 60 96 0x5e TxSta4: 0110 0000 35 53 0x5f 0011 0101 29 41 0x60 TxSta2: 0010 1001 25 37 0x61 0010 0101 40 64 0x62 TxSta0: 0100 0000 2d 45 Transmitter: Beginning Tx status check... 00 0 0x57 TxEnd: 0000 0000 28 40 0x58 0010 1000 50 80 0x59 TxStart: 0101 0000 60 96 0x5a 0110 0000 35 53 0x5b ->0x78-Phy0011 0101 29 41 0x5c TxSta6: 0010 1001 25 37 0x5d 0010 0101 40 64 0x5e TxSta4: 0100 0000 2d 45 0x5f 0010 1101 00 0 0x60 TxSta2: 0000 0000 40 64 0x61 0100 0000 00 0 0x62 TxSta0: 0000 0000 40 64 f1 241 00 0 28 40 Reset_hard: Done holding Eth. Ctrl. reset pin ------------ 50 80 IRQ: INT0 0001_0000 - Oscillator init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 35 53 29 41 Reset_hard: Done! Wrote to all Eth. Ctrl. config. regs 25 37 state: 101 - Transmitter: S-Packet 40 64 2d 45 Transmitter: Beginning Tx status check... 00 0 0x57 TxEnd: 0000 0000 40 64 0x58 0100 0000 00 0 0x59 TxStart: 0000 0000 00 0 0x5a 0000 0000 28 40 0x5b ->0x78-Phy0010 1000 50 80 0x5c TxSta6: 0101 0000 60 96 0x5d 0110 0000 35 53 0x5e TxSta4: 0011 0101 29 41 0x5f 0010 1001 25 37 0x60 TxSta2: 0010 0101 40 64 0x61 0100 0000 2d 45 0x62 TxSta0: 0010 1101 00 0 28 40 Reset_hard: Done holding Eth. Ctrl. reset pin ------------ 50 80 IRQ: INT0 0001_0000 - Oscillator init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 35 53 29 41 Reset_hard: Done! Wrote to all Eth. Ctrl. config. regs 25 37 state: 101 - Transmitter: S-Packet 40 64 2d 45 Transmitter: Beginning Tx status check... 00 0 0x57 TxEnd: 0000 0000 40 64 0x58 0100 0000 00 0 0x59 TxStart: 0000 0000 40 64 0x5a 0100 0000 f1 241 0x5b ->0x78-Phy1111 0001 00 0 0x5c TxSta6: 0000 0000 00 0 0x5d 0000 0000 45 69 0x5e TxSta4: 0100 0101 00 0 0x5f 0000 0000 00 0 0x60 TxSta2: 0000 0000 28 40 0x61 0010 1000 50 80 0x62 TxSta0: 0101 0000 60 96 IRQ: INT0 0010_0000 - Self-init. complete 35 53 29 41 Reset_hard: Done! Wrote to all Eth. Ctrl. config. regs 25 37 state: 101 - Transmitter: S-Packet 40 64 2d 45 Transmitter: Beginning Tx status check... 00 0 0x57 TxEnd: 0000 0000 40 64 0x58 0100 0000 00 0 0x59 TxStart: 0000 0000 40 64 0x5a 0100 0000 f1 241 0x5b ->0x78-Phy1111 0001 00 0 0x5c TxSta6: 0000 0000 00 0 0x5d 0000 0000 45 69 0x5e TxSta4: 0100 0101 00 0 0x5f 0000 0000 c0 192 0x60 TxSta2: 1100 0000 00 0 0x61 0000 0000 45 69 0x62 TxSta0: 0100 0101 2f 47 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 00 0 28 40 Reset_hard: Done holding Eth. Ctrl. reset pin ------------ 50 80 IRQ: INT0 0001_0000 - Oscillator init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 35 53 29 41 Reset_hard: Done! Wrote to all Eth. Ctrl. config. regs 25 37 state: 101 - Transmitter: S-Packet 40 64 2d 45 Transmitter: Beginning Tx status check... 00 0 0x57 TxEnd: 0000 0000 40 64 0x58 0100 0000 00 0 0x59 TxStart: 0000 0000 40 64 0x5a 0100 0000 f1 241 0x5b ->0x78-Phy1111 0001 00 0 0x5c TxSta6: 0000 0000 00 0 0x5d 0000 0000 45 69 0x5e TxSta4: 0100 0101 00 0 0x5f 0000 0000 00 0 0x60 TxSta2: 0000 0000 28 40 0x61 0010 1000 50 80 0x62 TxSta0: 0101 0000 60 96 IRQ: INT0 0010_0000 - Self-init. complete 35 53 29 41 Reset_hard: Done! Wrote to all Eth. Ctrl. config. regs 25 37 state: 101 - Transmitter: S-Packet 40 64 2d 45 Transmitter: Beginning Tx status check... 00 0 0x57 TxEnd: 0000 0000 40 64 0x58 0100 0000 00 0 0x59 TxStart: 0000 0000 40 64 0x5a 0100 0000 f1 241 0x5b ->0x78-Phy1111 0001 00 0 0x5c TxSta6: 0000 0000 00 0 0x5d 0000 0000 45 69 0x5e TxSta4: 0100 0101 00 0 0x5f 0000 0000 c0 192 0x60 TxSta2: 1100 0000 00 0 0x61 0000 0000 45 69 0x62 TxSta0: 0100 0101 2f 47 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 00 0 28 40 Reset_hard: Done holding Eth. Ctrl. reset pin ------------ 50 80 IRQ: INT0 0001_0000 - Oscillator init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 35 53 29 41 Reset_hard: Done! Wrote to all Eth. Ctrl. config. regs 25 37 state: 101 - Transmitter: S-Packet 40 64 2d 45 Transmitter: Beginning Tx status check... 00 0 0x57 TxEnd: 0000 0000 40 64 0x58 0100 0000 00 0 0x59 TxStart: 0000 0000 40 64 0x5a 0100 0000 f1 241 0x5b ->0x78-Phy1111 0001 00 0 0x5c TxSta6: 0000 0000 00 0 0x5d 0000 0000 45 69 0x5e TxSta4: 0100 0101 00 0 0x5f 0000 0000 c0 192 0x60 TxSta2: 1100 0000 00 0 0x61 0000 0000 45 69 0x62 TxSta0: 0100 0101 2f 47 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 08 8 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 00 0 28 40 Reset_hard: Done holding Eth. Ctrl. reset pin ------------ 50 80 IRQ: INT0 0001_0000 - Oscillator init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 35 53 29 41 Reset_hard: Done! Wrote to all Eth. Ctrl. config. regs 25 37 state: 101 - Transmitter: S-Packet 40 64 2d 45 Transmitter: Beginning Tx status check... 00 0 0x57 TxEnd: 0000 0000 40 64 0x58 0100 0000 00 0 0x59 TxStart: 0000 0000 40 64 0x5a 0100 0000 f1 241 0x5b ->0x78-Phy1111 0001 00 0 0x5c TxSta6: 0000 0000 00 0 0x5d 0000 0000 45 69 0x5e TxSta4: 0100 0101 03 3 0x5f 0000 0011 a0 160 0x60 TxSta2: 1010 0000 00 0 0x61 0000 0000 45 69 0x62 TxSta0: 0100 0101 2f 47 ff 255 ff 255 ff 255 ff 255 ff 255 ff 255 00 0 0b 11 3c 60 02 2 dc 220 bd 189 00 0 32 50 bf 191 53 83 00 0 00 0 00 0 08 8 00 0 07 7 00 0 06 6 00 0 05 5 00 0 04 4 00 0 03 3 00 0 02 2 00 0 01 1 00 0 08 8 00 0 07 7 00 0 06 6 00 0 05 5 00 0 04 4 00 0 03 3 bf 191 53 83 00 0 00 0 00 0 08 8 00 0 07 7 00 0 06 6 00 0 05 5 00 0 04 4 00 0 03 3 00 0 02 2 00 0 01 1 00 0 08 8 00 0 07 7 00 0 06 6 00 0 05 5 00 0 04 4 00 0 03 3 bf 191 53 83 00 0 00 0 00 0 08 8 00 0 07 7 00 0 06 6 00 0 05 5 00 0 04 4 00 0 03 3 00 0 02 2 00 0 01 1 00 0 08 8 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 fe 254 00 0 28 40 Reset_hard: Done holding Eth. Ctrl. reset pin ------------ 50 80 IRQ: INT0 0001_0000 - Oscillator init. complete 60 96 IRQ: INT0 0010_0000 - Self-init. complete 35 53 29 41 Reset_hard: Done! Wrote to all Eth. Ctrl. config. regs 25 37 state: 101 - Transmitter: S-Packet 40 64 2d 45 Transmitter: Beginning Tx status check... 00 0 0x57 TxEnd: 0000 0000 40 64 0x58 0100 0000 00 0 0x59 TxStart: 0000 0000 40 64 0x5a 0100 0000 f1 241 0x5b ->0x78-Phy1111 0001 00 0 0x5c TxSta6: 0000 0000 00 0 0x5d 0000 0000 45 69 0x5e TxSta4: 0100 0101 03 3 0x5f 0000 0011 a0 160 0x60 TxSta2: 1010 0000 00 0 0x61 0000 0000 45 69 0x62 TxSta0: 0100 0101 2f 47 ff 255 ff 255 ff 255 ff 255 ff 255 ff 255 00 0 0b 11 3c 60 02 2 dc 220 bd 189 00 0 32 50 bf 191 53 83 00 0 00 0 00 0 08 8 00 0 07 7 00 0 06 6 00 0 05 5 00 0 04 4 00 0 03 3 00 0 02 2 00 0 01 1 00 0 08 8 00 0 07 7 00 0 06 6 00 0 05 5 00 0 04 4 00 0 03 3 bf 191 53 83 00 0 00 0 00 0 08 8 00 0 07 7 00 0 06 6 00 0 05 5 00 0 04 4 00 0 03 3 00 0 02 2 00 0 01 1 00 0 08 8 00 0 07 7 00 0 06 6 00 0 05 5 00 0