| T | Map Messages - Errors, Warnings, and Infos | New |
| INFO | Map:110 - output buffer 'DAC_serData_OBUF' driving design level port 'DAC_serData' is being pushed into module 'u10/u2' to enable I/O register usage. The buffer has been renamed as 'u10/u2/DAC_serData_OBUF'. | |
| INFO | Map:110 - output buffer 'SPI_A_iCS_OBUF' driving design level port 'SPI_A_iCS' is being pushed into module 'u8/u3/u1' to enable I/O register usage. The buffer has been renamed as 'u8/u3/u1/SPI_A_iCS_OBUF'. | |
| INFO | Map:113 - input buffer 'SPI_SDO_IBUF' driving design level port 'SPI_SDO' is being pushed into module 'u8/u6' to enable I/O register usage. The buffer has been renamed as 'u8/u6/SPI_SDO_IBUF'. | |
| INFO | Map:110 - output buffer 'db_serial_OBUF' driving design level port 'db_serial' is being pushed into module 'db0/u0' to enable I/O register usage. The buffer has been renamed as 'db0/u0/db_serial_OBUF'. | |
| WARNING | LIT:243 - Logical network N228 has no load. | |
| WARNING | LIT:243 - Logical network N229 has no load. | |
| WARNING | LIT:243 - Logical network N230 has no load. | |
| WARNING | LIT:243 - Logical network N231 has no load. | |
| WARNING | LIT:243 - Logical network N232 has no load. | |
| WARNING | LIT:243 - Logical network N233 has no load. | |
| WARNING | LIT:243 - Logical network N234 has no load. | |
| WARNING | LIT:243 - Logical network N235 has no load. | |
| WARNING | LIT:243 - Logical network STARTUP_SPARTAN3A_inst/GSR_INT has no load. | |
| WARNING | LIT:243 - Logical network STARTUP_SPARTAN3A_inst/GTS_INT has no load. | |
| INFO | MapLib:562 - No environment variables are currently set. | |
| INFO | LIT:244 - All of the single ended outputs in this design are using slew rate limited output drivers. The delay on speed critical single ended outputs can be dramatically reduced by designating them as fast outputs. | |
| INFO | Pack:1716 - Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000 Celsius) | |
| INFO | Pack:1720 - Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.260 Volts) | |
| ERROR | Place:543 - This design does not fit into the number of slices available in this device due to the complexity of the design and/or constraints.
Unplaced instances by type:
FF 94 (8.9)
Please evaluate the following:
- If there are user-defined constraints or area groups:
Please look at the "User-defined constraints" section below to determine
what constraints might be impacting the fitting of this design.
Evaluate if they can be moved, removed or resized to allow for fitting.
Verify that they do not overlap or conflict with clock region restrictions.
See the clock region reports in the MAP log file (*map) for more details
on clock region usage.
- If there is difficulty in placing FFs:
Evaluate the number and configuration of the control sets in your design.
The following instances are the last set of instances that failed to place:
0. FF r2/reg_0_6
1. FF r2/reg_1_2
2. FF r2/reg_0_7
3. FF r2/reg_1_3
4. FF r2/reg_2_0
5. FF r2/reg_1_4
6. FF r2/reg_2_1
7. FF r2/reg_1_5
8. FF r2/reg_2_2
9. FF r2/reg_1_6
10. FF r2/reg_2_3
11. FF r2/reg_1_7
12. FF r2/reg_3_0
13. FF r2/reg_2_4
14. FF r2/reg_3_1
15. FF r2/reg_2_5
16. FF r2/reg_3_2
17. FF r2/reg_2_6
18. FF r2/reg_3_3
19. FF r2/reg_2_7
20. FF r2/reg_4_0
21. FF r2/reg_3_4
22. FF r2/reg_4_1
23. FF r2/reg_3_5
24. FF r2/reg_4_2
25. FF r2/reg_3_6
26. FF r2/reg_4_3
27. FF r2/reg_3_7
28. FF r2/reg_5_0
29. FF r2/reg_4_4
30. FF r2/reg_5_1
31. FF r2/reg_4_5
32. FF r2/reg_5_2
33. FF r2/reg_4_6
34. FF r2/reg_5_3
35. FF r2/reg_4_7
36. FF r2/reg_6_0
37. FF r2/reg_5_4
38. FF r2/reg_6_1
39. FF r2/reg_5_5
40. FF r2/reg_6_2
41. FF r2/reg_5_6
42. FF r2/reg_6_3
43. FF r2/reg_5_7
44. FF r2/reg_6_4
45. FF r2/reg_7_0
46. FF r2/reg_6_5
47. FF r2/reg_7_1
48. FF r2/reg_6_6
49. FF r2/reg_7_2
50. FF r2/reg_6_7
51. FF r2/reg_7_3
52. FF r2/reg_8_0
53. FF r2/reg_7_4
54. FF r2/reg_8_1
55. FF r2/reg_7_5
56. FF r2/reg_8_2
57. FF r2/reg_7_6
58. FF r2/reg_8_3
59. FF r2/reg_7_7
60. FF r2/reg_9_0
61. FF r2/reg_8_4
62. FF r2/reg_9_1
63. FF r2/reg_8_5
64. FF r2/reg_9_2
65. FF r2/reg_8_6
66. FF r2/reg_9_3
67. FF r2/reg_8_7
68. FF r2/reg_9_4
69. FF r2/reg_9_5
70. FF r2/reg_9_6
71. FF r2/reg_9_7
72. FF u2/m6/m/m2/AddrL_reg<2>
73. FF u2/m6/m/m2/AddrL_reg<3>
74. FF u4/uTxS2/AddrL_reg<1>
75. FF u4/uTxS2/AddrL_reg<3>
76. FF u4/uTxS2/AddrL_reg<4>
77. FF u4/uTxS2/AddrL_reg<6>
78. FF u4/uCheck2/ra1/aH/En
79. FF u4/uSpack/uTxSt1/AddrL_reg<4>
80. FF u4/uSpack/uTxSt1/AddrL_reg<6>
81. FF db0/db
82. FF u2/m6/m/m2/Data<0>
83. FF u2/m6/m/m2/Data<1>
84. FF u2/m6/m/m2/Data<2>
85. FF u2/m6/m/m2/Data<3>
86. FF u2/m6/m/m2/Data<4>
87. FF u2/m6/m/m2/Data<5>
88. FF u2/m6/m/m2/Data<6>
89. FF u2/m6/m/m2/Data<7>
90. FF u2/g1/Qb
91. FF u0/INTdelayed
92. FF INT_Done
93. FF u4/Done_TxStart2 | |
| ERROR | Place:120 - There were not enough sites to place all selected components.
Some of these failures can be circumvented by using an alternate algorithm (though it may take longer run time). If you would like to enable this algorithm please set the environment variable XIL_PAR_ENABLE_LEGALIZER to 1 and try again | |
| ERROR | Pack:1654 - The timing-driven placement phase encountered an error. | |