****** PlanAhead v11.1
  **** Build 44534 by hdbuild on Thu Mar  5 11:02:58 PST 2009
    ** Copyright 1986-1999, 2001-2009 Xilinx, Inc. All Rights Reserved.

INFO: [HD-Licensing 0] Attempting to get a license: PlanAhead
INFO: [HD-Licensing 1] Got a license: PlanAhead
INFO: [HD-ArchReader 10] Loading parts and site information from C:\Xilinx\11.1\PlanAhead\parts\arch.xml
INFO: [HD-RTPRIM 0] Parsing RTL primitives file 'C:\Xilinx\11.1\PlanAhead\parts\xilinx\rtl\prims\rtl_prims.xml'
INFO: [HD-RTPRIM 1] Finished Parsing RTL primitives file 'C:\Xilinx\11.1\PlanAhead\parts\xilinx\rtl\prims\rtl_prims.xml'
INFO: [HD-Application 1] Opened log file C:\Work\GlueX\Tagger\Electronics\FPGA\TotalTest\planAhead.log
INFO: [HD-Application 2] Opened journal file C:\Work\GlueX\Tagger\Electronics\FPGA\TotalTest\planAhead.jou
INFO: [HD-RTPRIM 0] Parsing template file 'C:\Xilinx\11.1\ISE\data\projnav\templates\verilog.xml'
INFO: [HD-RTPRIM 1] Finished parsing template file 'C:\Xilinx\11.1\ISE\data\projnav\templates\verilog.xml'
INFO: [HD-RTPRIM 0] Parsing template file 'C:\Xilinx\11.1\ISE\data\projnav\templates\vhdl.xml'
INFO: [HD-RTPRIM 1] Finished parsing template file 'C:\Xilinx\11.1\ISE\data\projnav\templates\vhdl.xml'
INFO: [HD-RTPRIM 0] Parsing template file 'C:\Xilinx\11.1\ISE\data\projnav\templates\ucf.xml'
INFO: [HD-RTPRIM 1] Finished parsing template file 'C:\Xilinx\11.1\ISE\data\projnav\templates\ucf.xml'
ngc2edif part name xc5vlx30ff676-2
Release 11.1 - ngc2edif L.33 (nt)
Copyright (c) 1995-2009 Xilinx, Inc.  All rights reserved.

Release 11.1 - ngc2edif L.33 (nt)
Copyright (c) 1995-2009 Xilinx, Inc.  All rights reserved.
Reading design FPGA_ctrl.ngc ...
WARNING:NetListWriters:298 - No output is written to FPGA_ctrl.xncf, ignored.
Processing design ...
   Preping design's networks ...
   Preping design's macros ...
WARNING:NetListWriters:306 - Signal bus state_D<2 : 0> on block FPGA_ctrl is not
   reconstructed, because there are some missing bus signals.
WARNING:NetListWriters:306 - Signal bus u8/Mtridata_DAC_D<10 : 0> on block
   FPGA_ctrl is not reconstructed, because there are some missing bus signals.
WARNING:NetListWriters:306 - Signal bus u8/Mtridata_DAC_D_mux0000<10 : 0> on
   block FPGA_ctrl is not reconstructed, because there are some missing bus
   signals.
WARNING:NetListWriters:306 - Signal bus u8/VoltData<9 : 7> on block FPGA_ctrl is
   not reconstructed, because there are some missing bus signals.
  finished :Prep
Writing EDIF netlist file FPGA_ctrl.edif ...
ngc2edif: Total memory usage is 38112 kilobytes

INFO: [HD-Application 0] Exiting PlanAhead...
INFO: [HD-Licensing 2] Releasing license: PlanAhead