--------------------------------------------------------------------------------
-- Company: 
-- Engineer:
--
-- Create Date:   12:11:05 10/07/2009
-- Design Name:   
-- Module Name:   C:/work/GlueX/Tagger/Electronics/FPGA/TotalTest/SPI_test.vhd
-- Project Name:  TotalTest
-- Target Device:  
-- Tool versions:  
-- Description:   
-- 
-- VHDL Test Bench Created by ISE for module: SPIctrl
-- 
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes: 
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation 
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
 
ENTITY SPI_test IS
END SPI_test;
 
ARCHITECTURE behavior OF SPI_test IS 
 
    -- Component Declaration for the Unit Under Test (UUT)
 
    COMPONENT SPIctrl
    PORT(
         Clk : IN  std_logic;
         iRst_in : IN  std_logic;
         T_iA : IN  std_logic;
         Go : IN  std_logic;
         Addr : IN  std_logic_vector(2 downto 0);
         SDO : IN  std_logic;
         SCLK : OUT  std_logic;
         iRst_out : OUT  std_logic;
         SDI : OUT  std_logic;
         T_CE : OUT  std_logic;
         A_iCS : OUT  std_logic;
         Done : OUT  std_logic;
         T_Q : OUT  std_logic_vector(9 downto 0);
         A_A : OUT  std_logic_vector(2 downto 0);
         A_Q : OUT  std_logic_vector(11 downto 0);
         ser_Go : OUT  std_logic;
         ser_D : OUT  std_logic_vector(7 downto 0);
         db : OUT  std_logic
        );
    END COMPONENT;
    

   --Inputs
   signal Clk : std_logic := '0';
   signal iRst_in : std_logic := '0';
   signal T_iA : std_logic := '0';
   signal Go : std_logic := '0';
   signal Addr : std_logic_vector(2 downto 0) := (others => '0');
   signal SDO : std_logic := '0';

 	--Outputs
   signal SCLK : std_logic;
   signal iRst_out : std_logic;
   signal SDI : std_logic;
   signal T_CE : std_logic;
   signal A_iCS : std_logic;
   signal Done : std_logic;
   signal T_Q : std_logic_vector(9 downto 0);
   signal A_A : std_logic_vector(2 downto 0);
   signal A_Q : std_logic_vector(11 downto 0);
   signal ser_Go : std_logic;
   signal ser_D : std_logic_vector(7 downto 0);
   signal db : std_logic;

   -- Clock period definitions
   constant Clk_period : time := 0.2us;
   --constant SCLK_period : time := 1us;
 
BEGIN
 
	-- Instantiate the Unit Under Test (UUT)
   uut: SPIctrl PORT MAP (
          Clk => Clk,
          iRst_in => iRst_in,
          T_iA => T_iA,
          Go => Go,
          Addr => Addr,
          SDO => SDO,
          SCLK => SCLK,
          iRst_out => iRst_out,
          SDI => SDI,
          T_CE => T_CE,
          A_iCS => A_iCS,
          Done => Done,
          T_Q => T_Q,
          A_A => A_A,
          A_Q => A_Q,
          ser_Go => ser_Go,
          ser_D => ser_D,
          db => db
        );

   -- Clock process definitions
   Clk_process :process
   begin
		Clk <= '0';
		wait for Clk_period/2;
		Clk <= '1';
		wait for Clk_period/2;
   end process;
 

 

   -- Stimulus process
   stim_proc: process
   begin
		iRst_in <= '0';
      wait for Clk_period*2;
		iRst_in <= '1';
		wait for Clk_period*40;
		Go <= '1'; Addr <= "111";
		wait for Clk_period;
		Go <= '0'; Addr <= "000";

		wait for Clk_period*40;
		Go <= '1'; Addr <= "111";
		wait for Clk_period;
		Go <= '0'; Addr <= "000";
		
      wait;
   end process;

END;