----------------------------------------------------------------------------------
-- Company: University of Connecticut
-- Engineer: Igor Senderovich
-- 
-- Create Date:    10:22:32 09/24/2007 
-- Design Name:    Multiplexed Registers for DAC voltage values
-- Module Name:    RxRegs - Behavioral 
-- Description:    32 x 14bit muxed register bank with 16bit (0-padded) output
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity RxRegs is
    Port ( Clk : in  STD_LOGIC;
           Rst : in  STD_LOGIC;
           Wr : in  STD_LOGIC;
           A : in  STD_LOGIC_VECTOR (7 downto 0);
           D : in  STD_LOGIC_VECTOR (7 downto 0);
           Q : out  STD_LOGIC_VECTOR (7 downto 0)
	 );
end RxRegs;

architecture Behavioral of RxRegs is
	
	type registers8bit is array (integer range <>) of STD_LOGIC_VECTOR (7 downto 0);
	signal reg : registers8bit (255 downto 0);
	signal intAddr :  integer range 255 downto 0;
	--signal AddrChecked : STD_LOGIC_VECTOR (7 downto 0);

begin

	intAddr <= conv_integer(A);

	RxRegs : process (Clk, Rst, Wr, D, intAddr, A)
	begin
		if (Rst = '1') then
			for i in 255 downto 0 loop
				reg(i) <= X"FF";
			end loop;
		else
			if falling_edge(Clk) then
				if (Wr = '1') then
					reg(intAddr) <= D;
				else
					reg <= reg;
				end if;
			else
				reg <= reg;
			end if;
		end if;
	end process RxRegs;

	Q <= reg(intAddr);

end Behavioral;