----------------------------------------------------------------------------------
-- Company: University of Connecticut
-- Engineer: Igor Senderovich
-- 
-- Create Date:    04:14:41 10/01/2007 
-- Design Name: 
-- Module Name:    InspectReg - Behavioral 
-- Description:    Checks the transmit status registers of the Eth. Ctrl.
----------------------------------------------------------------------------------

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

library FPGA_BasicComp;
use FPGA_BasicComp.BasicComp.all;

entity InspectReg is
    Port ( Clk : in  STD_LOGIC;
	   Rst : in STD_LOGIC;
           Go : in STD_LOGIC;
	   Addr : in STD_LOGIC_VECTOR (7 downto 0);
	   Done : out STD_LOGIC;

	   -- Transceiver control lines
	   TxRx_Go : out  STD_LOGIC;
           TxRx_RiW : out  STD_LOGIC;
           TxRx_A : out  STD_LOGIC_VECTOR (7 downto 0);
	   TxRx_Q : in STD_LOGIC_VECTOR (7 downto 0);
           TxRx_Done : in  STD_LOGIC;

	   -- Serial log output lines
 	   ser_Go : out STD_LOGIC;
  	   ser_D : out STD_LOGIC_VECTOR (7 downto 0);
	   db : out STD_LOGIC
	 );
end InspectReg;

architecture Behavioral of InspectReg is
	
	signal Go_late : STD_LOGIC;
	signal Done_read : STD_LOGIC;
	signal Data : STD_LOGIC_VECTOR (7 downto 0);
	
begin

	u0: Counter16bit port map (Clk, Rst, Go, Go_late);

	u1: getByte
	port map (Clk, Rst, Go_late, Addr, Data, Done_read,
		  TxRx_Go, TxRx_RiW, TxRx_A, TxRx_Q, TxRx_Done);
	ser_Go <= Done_read;
	ser_D <= Data when Done_read='1' else "ZZZZZZZZ";

	Done <= Done_read;
	
end Behavioral;