| TotalTest Project Status (05/17/2010 - 20:19:20) | |||
| Project File: | TotalTest.ise | Implementation State: | Placed and Routed |
| Module Name: | FPGA_ctrl |
|
No Errors |
| Target Device: | xc3s50a-4vq100 |
|
439 Warnings (0 new) |
| Product Version: | ISE 11.3 |
|
All Signals Completely Routed |
| Design Goal: | Balanced |
|
All Constraints Met |
| Design Strategy: | Xilinx Default (unlocked) |
|
0 (Setup: 0, Hold: 0) (Timing Report) |
| Device Utilization Summary | [-] | ||||
| Logic Utilization | Used | Available | Utilization | Note(s) | |
| Total Number Slice Registers | 762 | 1,408 | 54% | ||
| Number used as Flip Flops | 761 | ||||
| Number used as Latches | 1 | ||||
| Number of 4 input LUTs | 1,197 | 1,408 | 85% | ||
| Number of occupied Slices | 689 | 704 | 97% | ||
| Number of Slices containing only related logic | 689 | 689 | 100% | ||
| Number of Slices containing unrelated logic | 0 | 689 | 0% | ||
| Total Number of 4 input LUTs | 1,237 | 1,408 | 87% | ||
| Number used as logic | 1,077 | ||||
| Number used as a route-thru | 40 | ||||
| Number used for Dual Port RAMs | 120 | ||||
| Number of bonded IOBs | 38 | 68 | 55% | ||
| IOB Flip Flops | 12 | ||||
| IOB Latches | 1 | ||||
| Number of BUFGMUXs | 2 | 24 | 8% | ||
| Number of DCMs | 1 | 2 | 50% | ||
| Number of STARTUPs | 1 | 1 | 100% | ||
| Number of STARTUP_SPARTAN3As | 1 | 1 | 100% | ||
| Number of STARTUP_SPARTAN3Es | 1 | 1 | 100% | ||
| Average Fanout of Non-Clock Nets | 3.35 | ||||
| Performance Summary | [-] | |||
| Final Timing Score: | 0 (Setup: 0, Hold: 0) | Pinout Data: | Pinout Report | |
| Routing Results: | All Signals Completely Routed | Clock Data: | Clock Report | |
| Timing Constraints: | All Constraints Met | |||
| Detailed Reports | [-] | |||||
| Report Name | Status | Generated | Errors | Warnings | Infos | |
| Synthesis Report | Current | Fri Nov 1 12:05:37 2013 | 0 | 354 Warnings (0 new) | 2 Infos (0 new) | |
| Translation Report | Current | Fri Nov 1 12:05:44 2013 | 0 | 0 | 0 | |
| Map Report | Current | Fri Nov 1 12:06:05 2013 | 0 | 73 Warnings (0 new) | 7 Infos (0 new) | |
| Place and Route Report | Current | Fri Nov 1 12:06:18 2013 | 0 | 12 Warnings (0 new) | 6 Infos (0 new) | |
| Power Report | ||||||
| Post-PAR Static Timing Report | Current | Fri Nov 1 12:06:23 2013 | 0 | 0 | 3 Infos (0 new) | |
| Bitgen Report | Out of Date | Mon Oct 21 15:50:27 2013 | 0 | 7 Warnings (0 new) | 0 | |
| Secondary Reports | [-] | ||
| Report Name | Status | Generated | |
| ISIM Simulator Log | Out of Date | Tue Oct 13 19:45:14 2009 | |
| Post-Synthesis Simulation Model Report | Out of Date | Thu Oct 31 14:33:54 2013 | |
| Guide Results Report | Current | Fri Nov 1 12:06:17 2013 | |