Release 11.3 Map L.57 (nt) Xilinx Map Application Log File for Design 'FPGA_ctrl' Design Information ------------------ Command Line : map -ise TotalTest.ise -intstyle ise -p xc3s50a-vq100-4 -timing -logic_opt on -ol std -t 1 -register_duplication off -cm speed -detail -ir all -ignore_keep_hierarchy -pr b -l -ntd -bp -smartguide FPGA_ctrl_guide.ncd -power off -o FPGA_ctrl_map.ncd FPGA_ctrl.ngd FPGA_ctrl.pcf Target Device : xc3s50a Target Package : vq100 Target Speed : -4 Mapper Version : spartan3a -- $Revision: 1.51.18.1 $ Mapped Date : Fri Nov 01 12:05:46 2013 WARNING:Map:246 - The MAP option "No logic replication" (-l) is being deprecated in the next major software release. Loading device for application Rf_Device from file '3s50a.nph' in environment E:\Xilinx\11.1\ISE. "FPGA_ctrl" is an NCD, version 3.2, device xc3s50a, package vq100, speed -4 WARNING:Map:267 - There will be a smaller percentage of guiding when using SmartGuide with the some of the physical synthesis options. These options include: "Combinatorial Logic Optimization"(-logic_opt),"Global Optimization"(-global_opt), and "Register Duplication"(-register_duplication). The command line used to create the guide file is: -ise TotalTest.ise -intstyle ise -p xc3s50a-vq100-4 -timing -logic_opt on -ol std -t 1 -register_duplication off -cm speed -detail -ir all -ignore_keep_hierarchy -pr b -l -ntd -bp -smartguide FPGA_ctrl_guide.ncd -power off -o FPGA_ctrl_map.ncd FPGA_ctrl.ngd FPGA_ctrl.pcf The command line used for this run is: -ise TotalTest.ise -intstyle ise -p xc3s50a-vq100-4 -timing -logic_opt on -ol std -t 1 -register_duplication off -cm speed -detail -ir all -ignore_keep_hierarchy -pr b -l -ntd -bp -smartguide FPGA_ctrl_guide.ncd -power off -o FPGA_ctrl_map.ncd FPGA_ctrl.ngd FPGA_ctrl.pcf If one or more of the above physical synthesis options is being used, SmartGuide will have a lower guide percentage, possibly longer runtimes and possibly worse timing scores. If the physical synthesis option is required to meet timing, it is suggested that SmartGuide is not used. If the physical synthesis option is not required, it is suggested to re-create the guide without the physical synthesis option and re-run SmartGuide WARNING:LIT:243 - Logical network STARTUP_SPARTAN3A_inst/GSR_INT has no load. WARNING:LIT:243 - Logical network STARTUP_SPARTAN3A_inst/GTS_INT has no load. WARNING:LIT:243 - Logical network r6/u1/r0/reg1bit_0/SPO has no load. WARNING:LIT:243 - Logical network r6/u1/r0/reg1bit_1/SPO has no load. WARNING:LIT:243 - Logical network r6/u1/r0/reg1bit_2/SPO has no load. WARNING:LIT:243 - Logical network r6/u1/r0/reg1bit_3/SPO has no load. WARNING:LIT:243 - Logical network r6/u1/r0/reg1bit_4/SPO has no load. WARNING:LIT:243 - Logical network r6/u1/r0/reg1bit_5/SPO has no load. WARNING:LIT:243 - Logical network r6/u1/r0/reg1bit_6/SPO has no load. WARNING:LIT:243 - Logical network r6/u1/r0/reg1bit_7/SPO has no load. WARNING:LIT:243 - Logical network r6/u1/r0/reg1bit_8/SPO has no load. WARNING:LIT:243 - Logical network r6/u1/r0/reg1bit_9/SPO has no load. WARNING:LIT:243 - Logical network r6/u1/r0/reg1bit_10/SPO has no load. WARNING:LIT:243 - Logical network r6/u1/r0/reg1bit_11/SPO has no load. WARNING:LIT:243 - Logical network r6/u1/r0/reg1bit_12/SPO has no load. WARNING:LIT:243 - Logical network r6/u1/r0/reg1bit_13/SPO has no load. WARNING:LIT:243 - Logical network r6/u1/r1/reg1bit_0/SPO has no load. WARNING:LIT:243 - Logical network r6/u1/r1/reg1bit_1/SPO has no load. WARNING:LIT:243 - Logical network r6/u1/r1/reg1bit_2/SPO has no load. WARNING:LIT:243 - Logical network r6/u1/r1/reg1bit_3/SPO has no load. WARNING:LIT:243 - Logical network r6/u1/r1/reg1bit_4/SPO has no load. WARNING:LIT:243 - Logical network r6/u1/r1/reg1bit_5/SPO has no load. WARNING:LIT:243 - Logical network r6/u1/r1/reg1bit_6/SPO has no load. WARNING:LIT:243 - Logical network r6/u1/r1/reg1bit_7/SPO has no load. WARNING:LIT:243 - Logical network r6/u1/r1/reg1bit_8/SPO has no load. WARNING:LIT:243 - Logical network r6/u1/r1/reg1bit_9/SPO has no load. WARNING:LIT:243 - Logical network r6/u1/r1/reg1bit_10/SPO has no load. WARNING:LIT:243 - Logical network r6/u1/r1/reg1bit_11/SPO has no load. WARNING:LIT:243 - Logical network r6/u1/r1/reg1bit_12/SPO has no load. WARNING:LIT:243 - Logical network r6/u1/r1/reg1bit_13/SPO has no load. WARNING:LIT:243 - Logical network db0/r1/r3/reg1bit_7/SPO has no load. WARNING:LIT:243 - Logical network db0/r1/r3/reg1bit_6/SPO has no load. WARNING:LIT:243 - Logical network db0/r1/r3/reg1bit_5/SPO has no load. WARNING:LIT:243 - Logical network db0/r1/r3/reg1bit_4/SPO has no load. WARNING:LIT:243 - Logical network db0/r1/r3/reg1bit_3/SPO has no load. WARNING:LIT:243 - Logical network db0/r1/r3/reg1bit_2/SPO has no load. WARNING:LIT:243 - Logical network db0/r1/r3/reg1bit_1/SPO has no load. WARNING:LIT:243 - Logical network db0/r1/r3/reg1bit_0/SPO has no load. WARNING:LIT:243 - Logical network db0/r1/r2/reg1bit_7/SPO has no load. WARNING:LIT:243 - Logical network db0/r1/r2/reg1bit_6/SPO has no load. WARNING:LIT:243 - Logical network db0/r1/r2/reg1bit_5/SPO has no load. WARNING:LIT:243 - Logical network db0/r1/r2/reg1bit_4/SPO has no load. WARNING:LIT:243 - Logical network db0/r1/r2/reg1bit_3/SPO has no load. WARNING:LIT:243 - Logical network db0/r1/r2/reg1bit_2/SPO has no load. WARNING:LIT:243 - Logical network db0/r1/r2/reg1bit_1/SPO has no load. WARNING:LIT:243 - Logical network db0/r1/r2/reg1bit_0/SPO has no load. WARNING:LIT:243 - Logical network db0/r1/r1/reg1bit_7/SPO has no load. WARNING:LIT:243 - Logical network db0/r1/r1/reg1bit_6/SPO has no load. WARNING:LIT:243 - Logical network db0/r1/r1/reg1bit_5/SPO has no load. WARNING:LIT:243 - Logical network db0/r1/r1/reg1bit_4/SPO has no load. WARNING:LIT:243 - Logical network db0/r1/r1/reg1bit_3/SPO has no load. WARNING:LIT:243 - Logical network db0/r1/r1/reg1bit_2/SPO has no load. WARNING:LIT:243 - Logical network db0/r1/r1/reg1bit_1/SPO has no load. WARNING:LIT:243 - Logical network db0/r1/r1/reg1bit_0/SPO has no load. WARNING:LIT:243 - Logical network db0/r1/r0/reg1bit_7/SPO has no load. WARNING:LIT:243 - Logical network db0/r1/r0/reg1bit_6/SPO has no load. WARNING:LIT:243 - Logical network db0/r1/r0/reg1bit_5/SPO has no load. WARNING:LIT:243 - Logical network db0/r1/r0/reg1bit_4/SPO has no load. WARNING:LIT:243 - Logical network db0/r1/r0/reg1bit_3/SPO has no load. WARNING:LIT:243 - Logical network db0/r1/r0/reg1bit_2/SPO has no load. WARNING:LIT:243 - Logical network db0/r1/r0/reg1bit_1/SPO has no load. WARNING:LIT:243 - Logical network db0/r1/r0/reg1bit_0/SPO has no load. Mapping design into LUTs... Running directed packing... WARNING:Pack:266 - The function generator TxRx_D<7>LogicTrst62_SW0_SW0 failed to merge with F5 multiplexer TxRx_A<7>LogicTrst1_SW4. There is a conflict for the FXMUX. The design will exhibit suboptimal timing. Constraining slice packing based on guide NCD. Running delay-based LUT packing... Updating timing models... Running timing-driven placement... Total REAL time at the beginning of Placer: 12 secs Total CPU time at the beginning of Placer: 6 secs Phase 1.7 Design Feasibility Check Phase 1.7 Design Feasibility Check (Checksum:496c6b1a) REAL time: 13 secs Phase 2.31 Local Placement Optimization Phase 2.31 Local Placement Optimization (Checksum:73c41790) REAL time: 13 secs Phase 3.2 Initial Clock and IO Placement WARNING:Place:1019 - A clock IOB / clock component pair have been found that are not placed at an optimal clock IOB / clock site pair. The clock component is placed at site . The IO component is placed at site . This will not allow the use of the fast path between the IO and the Clock buffer. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint was applied on COMP.PIN allowing your design to continue. This constraint disables all clock placer rules related to the specified COMP.PIN. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. WARNING:Place:1013 - A clock IOB / DCM component pair have been found that are not placed at an optimal clock IOB / DCM site pair. The clock component is placed at site . The clock IO/DCM site can be paired if they are placed/locked in the same quadrant. The IO component is placed at site . This will not allow the use of the fast path between the IO and the Clock buffer. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint was applied on COMP.PIN allowing your design to continue. This constraint disables all clock placer rules related to the specified COMP.PIN. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. Phase 3.2 Initial Clock and IO Placement (Checksum:73c41790) REAL time: 13 secs Phase 4.30 Global Clock Region Assignment Phase 4.30 Global Clock Region Assignment (Checksum:73c41790) REAL time: 13 secs Phase 5.36 Local Placement Optimization Phase 5.36 Local Placement Optimization (Checksum:73c41790) REAL time: 13 secs Phase 6.8 Global Placement ..... Phase 6.8 Global Placement (Checksum:ade0a195) REAL time: 13 secs Phase 7.5 Local Placement Optimization Phase 7.5 Local Placement Optimization (Checksum:ade0a195) REAL time: 13 secs Phase 8.18 Placement Optimization Phase 8.18 Placement Optimization (Checksum:ade0a195) REAL time: 13 secs Phase 9.5 Local Placement Optimization Phase 9.5 Local Placement Optimization (Checksum:ade0a195) REAL time: 13 secs Total REAL time to Placer completion: 13 secs Total CPU time to Placer completion: 6 secs Running physical synthesis... Physical synthesis completed. Running post-placement packing... Updating route info ... WARNING:PhysDesignRules:372 - Gated clock. Clock net Rst_int is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. WARNING:PhysDesignRules:372 - Gated clock. Clock net uXmit/uDpack/w/C_0_0_not0000 is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. WARNING:PhysDesignRules:372 - Gated clock. Clock net ser_Go_uINT is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. WARNING:PhysDesignRules:372 - Gated clock. Clock net uResS/Done_Byte is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. WARNING:PhysDesignRules:372 - Gated clock. Clock net uXmit/uSpack/Done_Word is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. WARNING:PhysDesignRules:372 - Gated clock. Clock net uXmit/uDpack/Done_Word is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. Design Summary -------------- Design Summary: Number of errors: 0 Number of warnings: 73 Logic Utilization: Total Number Slice Registers: 762 out of 1,408 54% Number used as Flip Flops: 761 Number used as Latches: 1 Number of 4 input LUTs: 1,197 out of 1,408 85% Logic Distribution: Number of occupied Slices: 689 out of 704 97% Number of Slices containing only related logic: 689 out of 689 100% Number of Slices containing unrelated logic: 0 out of 689 0% *See NOTES below for an explanation of the effects of unrelated logic. Total Number of 4 input LUTs: 1,237 out of 1,408 87% Number used as logic: 1,077 Number used as a route-thru: 40 Number used for Dual Port RAMs: 120 (Two LUTs used per Dual Port RAM) The Slice Logic Distribution report is not meaningful if the design is over-mapped for a non-slice resource or if Placement fails. Number of bonded IOBs: 38 out of 68 55% IOB Flip Flops: 12 IOB Latches: 1 Number of BUFGMUXs: 2 out of 24 8% Number of DCMs: 1 out of 2 50% Number of STARTUPs: 1 out of 1 100% Number of STARTUP_SPARTAN3As: 1 out of 1 100% Number of STARTUP_SPARTAN3Es: 1 out of 1 100% Average Fanout of Non-Clock Nets: 3.35 Peak Memory Usage: 224 MB Total REAL time to MAP completion: 18 secs Total CPU time to MAP completion: 11 secs Mapping completed. See MAP report file "FPGA_ctrl_map.mrp" for details.