# ======================================================= # XDL NCD CONVERSION MODE $Revision: 1.01$ # time: Wed Jul 15 13:47:30 2009 # ======================================================= # ======================================================= # The syntax for the design statement is: # design ; # or # design # ======================================================= design "FPGA_ctrl" xc3s50avq100-4 v3.2 , cfg " _DESIGN_PROP::BUS_INFO:6:INPUT:LocStamp<5:0> _DESIGN_PROP::BUS_INFO:8:INOUT:AD<7:0> _DESIGN_PROP::PIN_INFO:AD<0>:/FPGA_ctrl/PACKED/FPGA_ctrl/AD<0>/AD<0>/PAD:OUTPUT:7:AD<7\:0> _DESIGN_PROP::PIN_INFO:AD<1>:/FPGA_ctrl/PACKED/FPGA_ctrl/AD<1>/AD<1>/PAD:OUTPUT:6:AD<7\:0> _DESIGN_PROP::PIN_INFO:AD<2>:/FPGA_ctrl/PACKED/FPGA_ctrl/AD<2>/AD<2>/PAD:OUTPUT:5:AD<7\:0> _DESIGN_PROP::PIN_INFO:AD<3>:/FPGA_ctrl/PACKED/FPGA_ctrl/AD<3>/AD<3>/PAD:OUTPUT:4:AD<7\:0> _DESIGN_PROP::PIN_INFO:AD<4>:/FPGA_ctrl/PACKED/FPGA_ctrl/AD<4>/AD<4>/PAD:OUTPUT:3:AD<7\:0> _DESIGN_PROP::PIN_INFO:AD<5>:/FPGA_ctrl/PACKED/FPGA_ctrl/AD<5>/AD<5>/PAD:OUTPUT:2:AD<7\:0> _DESIGN_PROP::PIN_INFO:AD<6>:/FPGA_ctrl/PACKED/FPGA_ctrl/AD<6>/AD<6>/PAD:OUTPUT:1:AD<7\:0> _DESIGN_PROP::PIN_INFO:AD<7>:/FPGA_ctrl/PACKED/FPGA_ctrl/AD<7>/AD<7>/PAD:OUTPUT:0:AD<7\:0> _DESIGN_PROP::PIN_INFO:LocStamp<0>:/FPGA_ctrl/PACKED/FPGA_ctrl/LocStamp<0>/LocStamp<0>/PAD:INPUT:5:LocStamp<5\:0> _DESIGN_PROP::PIN_INFO:LocStamp<1>:/FPGA_ctrl/PACKED/FPGA_ctrl/LocStamp<1>/LocStamp<1>/PAD:INPUT:4:LocStamp<5\:0> _DESIGN_PROP::PIN_INFO:LocStamp<2>:/FPGA_ctrl/PACKED/FPGA_ctrl/LocStamp<2>/LocStamp<2>/PAD:INPUT:3:LocStamp<5\:0> _DESIGN_PROP::PIN_INFO:LocStamp<3>:/FPGA_ctrl/PACKED/FPGA_ctrl/LocStamp<3>/LocStamp<3>/PAD:INPUT:2:LocStamp<5\:0> _DESIGN_PROP::PIN_INFO:LocStamp<4>:/FPGA_ctrl/PACKED/FPGA_ctrl/LocStamp<4>/LocStamp<4>/PAD:INPUT:1:LocStamp<5\:0> _DESIGN_PROP::PIN_INFO:LocStamp<5>:/FPGA_ctrl/PACKED/FPGA_ctrl/LocStamp<5>/LocStamp<5>/PAD:INPUT:0:LocStamp<5\:0> _DESIGN_PROP::PK_NGMTIMESTAMP:1245863140"; # ======================================================= # The syntax for instances is: # instance , placed , cfg ; # or # instance , unplaced, cfg ; # # For typing convenience you can abbreviate instance to inst. # # For IOs there are two special keywords: bonded and unbonded # that can be used to designate whether the PAD of an unplaced IO is # bonded out. If neither keyword is specified, bonded is assumed. # # The bonding of placed IOs is determined by the site they are placed in. # # If you specify bonded or unbonded for an instance that is not an # IOB it is ignored. # # Shown below are three examples for IOs. # instance IO1 IOB, unplaced ; # This will be bonded # instance IO1 IOB, unplaced bonded ; # This will be bonded # instance IO1 IOB, unplaced unbonded ; # This will be unbonded # ======================================================= inst "u1/Result<0>1" "SLICEL",placed CLB_X16Y8 SLICE_X23Y15 , cfg " BXINV::BX BYINV::#OFF CEINV::#OFF CLKINV::#OFF COUTUSED::0 CY0F::1 CY0G::0 CYINIT::BX CYSELF::F CYSELG::G DXMUX::#OFF DYMUX::#OFF F:u1/p5/Mcount_count_lut<0>_INV_0:#LUT:D=~A4 F5USED::#OFF FFX::#OFF FFX_INIT_ATTR::#OFF FFX_SR_ATTR::#OFF FFY::#OFF FFY_INIT_ATTR::#OFF FFY_SR_ATTR::#OFF FXMUX::FXOR FXUSED::#OFF G:u1/p5/count<1>_rt:#LUT:D=A4 _BEL_PROP::G:PK_PACKTHRU: GYMUX::GXOR REVUSED::#OFF SRINV::#OFF SYNC_ATTR::#OFF XBUSED::#OFF XUSED::0 YBUSED::#OFF YUSED::0 C1VDD:ProtoComp0.C1VDD: CYMUXF:u1/p5/Mcount_count_cy<0>: CYMUXG:u1/p5/Mcount_count_cy<1>: GNDG:ProtoComp0.GNDG: XORF:u1/p5/Mcount_count_xor<0>: XORG:u1/p5/Mcount_count_xor<1>: _INST_PROP::XDL_SHAPE_DESC:Shape_0:CARRY,A\ carry\ chain\ starting\ with\ carry\ mux\ \"u1/p5/Mcount_count_cy<0>\" _INST_PROP::XDL_SHAPE_MEMBER:Shape_0:0,0 " ; inst "u1/Result<2>" "SLICEL",placed CLB_X16Y9 SLICE_X23Y16 , cfg " BXINV::#OFF BYINV::#OFF CEINV::#OFF CLKINV::#OFF COUTUSED::0 CY0F::0 CY0G::0 CYINIT::CIN CYSELF::F CYSELG::G DXMUX::#OFF DYMUX::#OFF F:u1/p5/count<2>_rt:#LUT:D=A4 _BEL_PROP::F:PK_PACKTHRU: F5USED::#OFF FFX::#OFF FFX_INIT_ATTR::#OFF FFX_SR_ATTR::#OFF FFY::#OFF FFY_INIT_ATTR::#OFF FFY_SR_ATTR::#OFF FXMUX::FXOR FXUSED::#OFF G:u1/p5/count<3>_rt:#LUT:D=A1 _BEL_PROP::G:PK_PACKTHRU: GYMUX::GXOR REVUSED::#OFF SRINV::#OFF SYNC_ATTR::#OFF XBUSED::#OFF XUSED::0 YBUSED::#OFF YUSED::0 CYMUXF:u1/p5/Mcount_count_cy<2>: CYMUXG:u1/p5/Mcount_count_cy<3>: GNDF:ProtoComp1.GNDF: GNDG:ProtoComp1.GNDG: XORF:u1/p5/Mcount_count_xor<2>: XORG:u1/p5/Mcount_count_xor<3>: _INST_PROP::XDL_SHAPE_MEMBER:Shape_0:0,1 " ; inst "u1/Result<4>" "SLICEL",placed CLB_X16Y9 SLICE_X23Y17 , cfg " BXINV::#OFF BYINV::#OFF CEINV::#OFF CLKINV::#OFF COUTUSED::0 CY0F::0 CY0G::0 CYINIT::CIN CYSELF::F CYSELG::G DXMUX::#OFF DYMUX::#OFF F:u1/p5/count<4>_rt:#LUT:D=A3 _BEL_PROP::F:PK_PACKTHRU: F5USED::#OFF FFX::#OFF FFX_INIT_ATTR::#OFF FFX_SR_ATTR::#OFF FFY::#OFF FFY_INIT_ATTR::#OFF FFY_SR_ATTR::#OFF FXMUX::FXOR FXUSED::#OFF G:u1/p5/count<5>_rt:#LUT:D=A2 _BEL_PROP::G:PK_PACKTHRU: GYMUX::GXOR REVUSED::#OFF SRINV::#OFF SYNC_ATTR::#OFF XBUSED::#OFF XUSED::0 YBUSED::#OFF YUSED::0 CYMUXF:u1/p5/Mcount_count_cy<4>: CYMUXG:u1/p5/Mcount_count_cy<5>: GNDF:ProtoComp1.GNDF.1: GNDG:ProtoComp1.GNDG.1: XORF:u1/p5/Mcount_count_xor<4>: XORG:u1/p5/Mcount_count_xor<5>: _INST_PROP::XDL_SHAPE_MEMBER:Shape_0:0,2 " ; inst "u1/Result<6>" "SLICEL",placed CLB_X16Y10 SLICE_X23Y18 , cfg " BXINV::#OFF BYINV::#OFF CEINV::#OFF CLKINV::#OFF COUTUSED::0 CY0F::0 CY0G::0 CYINIT::CIN CYSELF::F CYSELG::G DXMUX::#OFF DYMUX::#OFF F:u1/p5/count<6>_rt:#LUT:D=A3 _BEL_PROP::F:PK_PACKTHRU: F5USED::#OFF FFX::#OFF FFX_INIT_ATTR::#OFF FFX_SR_ATTR::#OFF FFY::#OFF FFY_INIT_ATTR::#OFF FFY_SR_ATTR::#OFF FXMUX::FXOR FXUSED::#OFF G:u1/p5/count<7>_rt:#LUT:D=A2 _BEL_PROP::G:PK_PACKTHRU: GYMUX::GXOR REVUSED::#OFF SRINV::#OFF SYNC_ATTR::#OFF XBUSED::#OFF XUSED::0 YBUSED::#OFF YUSED::0 CYMUXF:u1/p5/Mcount_count_cy<6>: CYMUXG:u1/p5/Mcount_count_cy<7>: GNDF:ProtoComp1.GNDF.2: GNDG:ProtoComp1.GNDG.2: XORF:u1/p5/Mcount_count_xor<6>: XORG:u1/p5/Mcount_count_xor<7>: _INST_PROP::XDL_SHAPE_MEMBER:Shape_0:0,3 " ; inst "u1/Result<8>" "SLICEL",placed CLB_X16Y10 SLICE_X23Y19 , cfg " BXINV::#OFF BYINV::#OFF CEINV::#OFF CLKINV::#OFF COUTUSED::0 CY0F::0 CY0G::0 CYINIT::CIN CYSELF::F CYSELG::G DXMUX::#OFF DYMUX::#OFF F:u1/p5/count<8>_rt:#LUT:D=A4 _BEL_PROP::F:PK_PACKTHRU: F5USED::#OFF FFX::#OFF FFX_INIT_ATTR::#OFF FFX_SR_ATTR::#OFF FFY::#OFF FFY_INIT_ATTR::#OFF FFY_SR_ATTR::#OFF FXMUX::FXOR FXUSED::#OFF G:u1/p5/count<9>_rt:#LUT:D=A1 _BEL_PROP::G:PK_PACKTHRU: GYMUX::GXOR REVUSED::#OFF SRINV::#OFF SYNC_ATTR::#OFF XBUSED::#OFF XUSED::0 YBUSED::#OFF YUSED::0 CYMUXF:u1/p5/Mcount_count_cy<8>: CYMUXG:u1/p5/Mcount_count_cy<9>: GNDF:ProtoComp1.GNDF.3: GNDG:ProtoComp1.GNDG.3: XORF:u1/p5/Mcount_count_xor<8>: XORG:u1/p5/Mcount_count_xor<9>: _INST_PROP::XDL_SHAPE_MEMBER:Shape_0:0,4 " ; inst "u1/Result<10>" "SLICEL",placed CLB_X16Y11 SLICE_X23Y20 , cfg " BXINV::#OFF BYINV::#OFF CEINV::#OFF CLKINV::#OFF COUTUSED::#OFF CY0F::0 CY0G::#OFF CYINIT::CIN CYSELF::F CYSELG::#OFF DXMUX::#OFF DYMUX::#OFF F:u1/p5/count<10>_rt:#LUT:D=A1 _BEL_PROP::F:PK_PACKTHRU: F5USED::#OFF FFX::#OFF FFX_INIT_ATTR::#OFF FFX_SR_ATTR::#OFF FFY::#OFF FFY_INIT_ATTR::#OFF FFY_SR_ATTR::#OFF FXMUX::FXOR FXUSED::#OFF G:u1/p5/count<11>_rt:#LUT:D=A4 _BEL_PROP::G:PK_PACKTHRU: GYMUX::GXOR REVUSED::#OFF SRINV::#OFF SYNC_ATTR::#OFF XBUSED::#OFF XUSED::0 YBUSED::#OFF YUSED::0 CYMUXF:u1/p5/Mcount_count_cy<10>: GNDF:ProtoComp2.GNDF: XORF:u1/p5/Mcount_count_xor<10>: XORG:u1/p5/Mcount_count_xor<11>: _INST_PROP::XDL_SHAPE_MEMBER:Shape_0:0,5 " ; inst "u8/Mcompar_En_cmp_ne0000_cy<1>" "SLICEL",placed CLB_X5Y9 SLICE_X9Y16 , cfg " BXINV::BX BYINV::#OFF CEINV::#OFF CLKINV::#OFF COUTUSED::0 CY0F::1 CY0G::1 CYINIT::BX CYSELF::F CYSELG::G DXMUX::#OFF DYMUX::#OFF F:u8/Mcompar_En_cmp_ne0000_lut<0>1:#LUT:D=((~A2*(~A1*~A3))+(A2*(A1*A3))) F5USED::#OFF FFX::#OFF FFX_INIT_ATTR::#OFF FFX_SR_ATTR::#OFF FFY::#OFF FFY_INIT_ATTR::#OFF FFY_SR_ATTR::#OFF FXMUX::#OFF FXUSED::#OFF G:u8/Mcompar_En_cmp_ne0000_lut<1>1:#LUT:D=((~A1*(~A4*~A2))+(A1*(A4*A2))) GYMUX::#OFF REVUSED::#OFF SRINV::#OFF SYNC_ATTR::#OFF XBUSED::#OFF XUSED::#OFF YBUSED::#OFF YUSED::#OFF C1VDD:ProtoComp3.C1VDD: C2VDD:ProtoComp3.C2VDD: CYMUXF:u8/Mcompar_En_cmp_ne0000_cy<0>: CYMUXG:u8/Mcompar_En_cmp_ne0000_cy<1>: _INST_PROP::XDL_SHAPE_DESC:Shape_1:CARRY,A\ carry\ chain\ starting\ with\ carry\ mux\ \"u8/Mcompar_En_cmp_ne0000_cy<0>\" _INST_PROP::XDL_SHAPE_MEMBER:Shape_1:0,0 " ; inst "u8/Mcompar_En_cmp_ne0000_cy<3>" "SLICEL",placed CLB_X5Y9 SLICE_X9Y17 , cfg " BXINV::#OFF BYINV::#OFF CEINV::#OFF CLKINV::#OFF COUTUSED::0 CY0F::1 CY0G::1 CYINIT::CIN CYSELF::F CYSELG::G DXMUX::#OFF DYMUX::#OFF F:u8/Mcompar_En_cmp_ne0000_lut<2>1:#LUT:D=((~A2*(~A1*~A4))+(A2*(A1*A4))) F5USED::#OFF FFX::#OFF FFX_INIT_ATTR::#OFF FFX_SR_ATTR::#OFF FFY::#OFF FFY_INIT_ATTR::#OFF FFY_SR_ATTR::#OFF FXMUX::#OFF FXUSED::#OFF G:u8/Mcompar_En_cmp_ne0000_lut<3>1:#LUT:D=((~A1*(~A2*~A4))+(A1*(A2*A4))) GYMUX::#OFF REVUSED::#OFF SRINV::#OFF SYNC_ATTR::#OFF XBUSED::#OFF XUSED::#OFF YBUSED::#OFF YUSED::#OFF C1VDD:ProtoComp4.C1VDD: C2VDD:ProtoComp4.C2VDD: CYMUXF:u8/Mcompar_En_cmp_ne0000_cy<2>: CYMUXG:u8/Mcompar_En_cmp_ne0000_cy<3>: _INST_PROP::XDL_SHAPE_MEMBER:Shape_1:0,1 " ; inst "u8/Mcompar_En_cmp_ne0000_cy<5>" "SLICEL",placed CLB_X5Y10 SLICE_X9Y18 , cfg " BXINV::#OFF BYINV::#OFF CEINV::#OFF CLKINV::#OFF COUTUSED::0 CY0F::1 CY0G::1 CYINIT::CIN CYSELF::F CYSELG::G DXMUX::#OFF DYMUX::#OFF F:u8/Mcompar_En_cmp_ne0000_lut<4>1:#LUT:D=((~A2*(~A1*~A3))+(A2*(A1*A3))) F5USED::#OFF FFX::#OFF FFX_INIT_ATTR::#OFF FFX_SR_ATTR::#OFF FFY::#OFF FFY_INIT_ATTR::#OFF FFY_SR_ATTR::#OFF FXMUX::#OFF FXUSED::#OFF G:u8/Mcompar_En_cmp_ne0000_lut<5>1:#LUT:D=((~A3*(~A2*~A4))+(A3*(A2*A4))) GYMUX::#OFF REVUSED::#OFF SRINV::#OFF SYNC_ATTR::#OFF XBUSED::#OFF XUSED::#OFF YBUSED::#OFF YUSED::#OFF C1VDD:ProtoComp4.C1VDD.1: C2VDD:ProtoComp4.C2VDD.1: CYMUXF:u8/Mcompar_En_cmp_ne0000_cy<4>: CYMUXG:u8/Mcompar_En_cmp_ne0000_cy<5>: _INST_PROP::XDL_SHAPE_MEMBER:Shape_1:0,2 " ; inst "u8/Mcompar_En_cmp_ne0000_cy<7>" "SLICEL",placed CLB_X5Y10 SLICE_X9Y19 , cfg " BXINV::#OFF BYINV::#OFF CEINV::#OFF CLKINV::#OFF COUTUSED::0 CY0F::1 CY0G::1 CYINIT::CIN CYSELF::F CYSELG::G DXMUX::#OFF DYMUX::#OFF F:u8/Mcompar_En_cmp_ne0000_lut<6>1:#LUT:D=((~A3*(~A4*~A2))+(A3*(A4*A2))) F5USED::#OFF FFX::#OFF FFX_INIT_ATTR::#OFF FFX_SR_ATTR::#OFF FFY::#OFF FFY_INIT_ATTR::#OFF FFY_SR_ATTR::#OFF FXMUX::#OFF FXUSED::#OFF G:u8/Mcompar_En_cmp_ne0000_lut<7>1:#LUT:D=((~A2*(~A1*~A4))+(A2*(A1*A4))) GYMUX::#OFF REVUSED::#OFF SRINV::#OFF SYNC_ATTR::#OFF XBUSED::#OFF XUSED::#OFF YBUSED::#OFF YUSED::#OFF C1VDD:ProtoComp4.C1VDD.2: C2VDD:ProtoComp4.C2VDD.2: CYMUXF:u8/Mcompar_En_cmp_ne0000_cy<6>: CYMUXG:u8/Mcompar_En_cmp_ne0000_cy<7>: _INST_PROP::XDL_SHAPE_MEMBER:Shape_1:0,3 _ROUTETHROUGH:COUT:YB " ; inst "u8/ByteCount<0>" "SLICEL",placed CLB_X4Y9 SLICE_X7Y16 , cfg " BXINV::BX BYINV::#OFF CEINV::#OFF CLKINV::CLK_B COUTUSED::0 CY0F::1 CY0G::0 CYINIT::BX CYSELF::F CYSELG::G DXMUX::1 DYMUX::1 F:u8/Mcount_ByteCount_lut<0>_INV_0:#LUT:D=~A3 F5USED::#OFF FFX:u8/ByteCount_0:#FF FFX_INIT_ATTR::INIT0 FFX_SR_ATTR::SRLOW FFY:u8/ByteCount_1:#FF FFY_INIT_ATTR::INIT0 FFY_SR_ATTR::SRLOW FXMUX::FXOR FXUSED::#OFF G:u8/ByteCount<1>_rt:#LUT:D=A1 _BEL_PROP::G:PK_PACKTHRU: GYMUX::GXOR REVUSED::#OFF SRINV::SR SYNC_ATTR::ASYNC XBUSED::#OFF XUSED::#OFF YBUSED::#OFF YUSED::#OFF C1VDD:ProtoComp5.C1VDD: CYMUXF:u8/Mcount_ByteCount_cy<0>: CYMUXG:u8/Mcount_ByteCount_cy<1>: GNDG:ProtoComp5.GNDG: XORF:u8/Mcount_ByteCount_xor<0>: XORG:u8/Mcount_ByteCount_xor<1>: _INST_PROP::XDL_SHAPE_DESC:Shape_2:CARRY,A\ carry\ chain\ starting\ with\ carry\ mux\ \"u8/Mcount_ByteCount_cy<0>\" _INST_PROP::XDL_SHAPE_MEMBER:Shape_2:0,0 " ; inst "u8/ByteCount<2>" "SLICEL",placed CLB_X4Y9 SLICE_X7Y17 , cfg " BXINV::#OFF BYINV::#OFF CEINV::#OFF CLKINV::CLK_B COUTUSED::0 CY0F::0 CY0G::0 CYINIT::CIN CYSELF::F CYSELG::G DXMUX::1 DYMUX::1 F:u8/ByteCount<2>_rt:#LUT:D=A2 _BEL_PROP::F:PK_PACKTHRU: F5USED::#OFF FFX:u8/ByteCount_2:#FF FFX_INIT_ATTR::INIT1 FFX_SR_ATTR::SRHIGH FFY:u8/ByteCount_3:#FF FFY_INIT_ATTR::INIT0 FFY_SR_ATTR::SRLOW FXMUX::FXOR FXUSED::#OFF G:u8/ByteCount<3>_rt:#LUT:D=A3 _BEL_PROP::G:PK_PACKTHRU: GYMUX::GXOR REVUSED::#OFF SRINV::SR SYNC_ATTR::ASYNC XBUSED::#OFF XUSED::#OFF YBUSED::#OFF YUSED::#OFF CYMUXF:u8/Mcount_ByteCount_cy<2>: CYMUXG:u8/Mcount_ByteCount_cy<3>: GNDF:ProtoComp6.GNDF: GNDG:ProtoComp6.GNDG: XORF:u8/Mcount_ByteCount_xor<2>: XORG:u8/Mcount_ByteCount_xor<3>: _INST_PROP::XDL_SHAPE_MEMBER:Shape_2:0,1 " ; inst "u8/ByteCount<4>" "SLICEL",placed CLB_X4Y10 SLICE_X7Y18 , cfg " BXINV::#OFF BYINV::#OFF CEINV::#OFF CLKINV::CLK_B COUTUSED::0 CY0F::0 CY0G::0 CYINIT::CIN CYSELF::F CYSELG::G DXMUX::1 DYMUX::1 F:u8/ByteCount<4>_rt:#LUT:D=A2 _BEL_PROP::F:PK_PACKTHRU: F5USED::#OFF FFX:u8/ByteCount_4:#FF FFX_INIT_ATTR::INIT1 FFX_SR_ATTR::SRHIGH FFY:u8/ByteCount_5:#FF FFY_INIT_ATTR::INIT0 FFY_SR_ATTR::SRLOW FXMUX::FXOR FXUSED::#OFF G:u8/ByteCount<5>_rt:#LUT:D=A1 _BEL_PROP::G:PK_PACKTHRU: GYMUX::GXOR REVUSED::#OFF SRINV::SR SYNC_ATTR::ASYNC XBUSED::#OFF XUSED::#OFF YBUSED::#OFF YUSED::#OFF CYMUXF:u8/Mcount_ByteCount_cy<4>: CYMUXG:u8/Mcount_ByteCount_cy<5>: GNDF:ProtoComp6.GNDF.1: GNDG:ProtoComp6.GNDG.1: XORF:u8/Mcount_ByteCount_xor<4>: XORG:u8/Mcount_ByteCount_xor<5>: _INST_PROP::XDL_SHAPE_MEMBER:Shape_2:0,2 " ; inst "u8/ByteCount<6>" "SLICEL",placed CLB_X4Y10 SLICE_X7Y19 , cfg " BXINV::#OFF BYINV::#OFF CEINV::#OFF CLKINV::CLK_B COUTUSED::0 CY0F::0 CY0G::0 CYINIT::CIN CYSELF::F CYSELG::G DXMUX::1 DYMUX::1 F:u8/ByteCount<6>_rt:#LUT:D=A4 _BEL_PROP::F:PK_PACKTHRU: F5USED::#OFF FFX:u8/ByteCount_6:#FF FFX_INIT_ATTR::INIT0 FFX_SR_ATTR::SRLOW FFY:u8/ByteCount_7:#FF FFY_INIT_ATTR::INIT0 FFY_SR_ATTR::SRLOW FXMUX::FXOR FXUSED::#OFF G:u8/ByteCount<7>_rt:#LUT:D=A4 _BEL_PROP::G:PK_PACKTHRU: GYMUX::GXOR REVUSED::#OFF SRINV::SR SYNC_ATTR::ASYNC XBUSED::#OFF XUSED::#OFF YBUSED::#OFF YUSED::#OFF CYMUXF:u8/Mcount_ByteCount_cy<6>: CYMUXG:u8/Mcount_ByteCount_cy<7>: GNDF:ProtoComp7.GNDF: GNDG:ProtoComp7.GNDG: XORF:u8/Mcount_ByteCount_xor<6>: XORG:u8/Mcount_ByteCount_xor<7>: _INST_PROP::XDL_SHAPE_MEMBER:Shape_2:0,3 " ; inst "u8/ByteCount<8>" "SLICEL",placed CLB_X4Y11 SLICE_X7Y20 , cfg " BXINV::#OFF BYINV::#OFF CEINV::#OFF CLKINV::CLK_B COUTUSED::0 CY0F::0 CY0G::0 CYINIT::CIN CYSELF::F CYSELG::G DXMUX::1 DYMUX::1 F:u8/ByteCount<8>_rt:#LUT:D=A4 _BEL_PROP::F:PK_PACKTHRU: F5USED::#OFF FFX:u8/ByteCount_8:#FF FFX_INIT_ATTR::INIT0 FFX_SR_ATTR::SRLOW FFY:u8/ByteCount_9:#FF FFY_INIT_ATTR::INIT0 FFY_SR_ATTR::SRLOW FXMUX::FXOR FXUSED::#OFF G:u8/ByteCount<9>_rt:#LUT:D=A1 _BEL_PROP::G:PK_PACKTHRU: GYMUX::GXOR REVUSED::#OFF SRINV::SR SYNC_ATTR::ASYNC XBUSED::#OFF XUSED::#OFF YBUSED::#OFF YUSED::#OFF CYMUXF:u8/Mcount_ByteCount_cy<8>: CYMUXG:u8/Mcount_ByteCount_cy<9>: GNDF:ProtoComp7.GNDF.1: GNDG:ProtoComp7.GNDG.1: XORF:u8/Mcount_ByteCount_xor<8>: XORG:u8/Mcount_ByteCount_xor<9>: _INST_PROP::XDL_SHAPE_MEMBER:Shape_2:0,4 " ; inst "u8/ByteCount<10>" "SLICEL",placed CLB_X4Y11 SLICE_X7Y21 , cfg " BXINV::#OFF BYINV::#OFF CEINV::#OFF CLKINV::CLK_B COUTUSED::0 CY0F::0 CY0G::0 CYINIT::CIN CYSELF::F CYSELG::G DXMUX::1 DYMUX::1 F:u8/ByteCount<10>_rt:#LUT:D=A3 _BEL_PROP::F:PK_PACKTHRU: F5USED::#OFF FFX:u8/ByteCount_10:#FF FFX_INIT_ATTR::INIT0 FFX_SR_ATTR::SRLOW FFY:u8/ByteCount_11:#FF FFY_INIT_ATTR::INIT0 FFY_SR_ATTR::SRLOW FXMUX::FXOR FXUSED::#OFF G:u8/ByteCount<11>_rt:#LUT:D=A2 _BEL_PROP::G:PK_PACKTHRU: GYMUX::GXOR REVUSED::#OFF SRINV::SR SYNC_ATTR::ASYNC XBUSED::#OFF XUSED::#OFF YBUSED::#OFF YUSED::#OFF CYMUXF:u8/Mcount_ByteCount_cy<10>: CYMUXG:u8/Mcount_ByteCount_cy<11>: GNDF:ProtoComp7.GNDF.2: GNDG:ProtoComp7.GNDG.2: XORF:u8/Mcount_ByteCount_xor<10>: XORG:u8/Mcount_ByteCount_xor<11>: _INST_PROP::XDL_SHAPE_MEMBER:Shape_2:0,5 " ; inst "u8/ByteCount<12>" "SLICEL",placed CLB_X4Y12 SLICE_X7Y22 , cfg " BXINV::#OFF BYINV::#OFF CEINV::#OFF CLKINV::CLK_B COUTUSED::0 CY0F::0 CY0G::0 CYINIT::CIN CYSELF::F CYSELG::G DXMUX::1 DYMUX::1 F:u8/ByteCount<12>_rt:#LUT:D=A2 _BEL_PROP::F:PK_PACKTHRU: F5USED::#OFF FFX:u8/ByteCount_12:#FF FFX_INIT_ATTR::INIT0 FFX_SR_ATTR::SRLOW FFY:u8/ByteCount_13:#FF FFY_INIT_ATTR::INIT0 FFY_SR_ATTR::SRLOW FXMUX::FXOR FXUSED::#OFF G:u8/ByteCount<13>_rt:#LUT:D=A3 _BEL_PROP::G:PK_PACKTHRU: GYMUX::GXOR REVUSED::#OFF SRINV::SR SYNC_ATTR::ASYNC XBUSED::#OFF XUSED::#OFF YBUSED::#OFF YUSED::#OFF CYMUXF:u8/Mcount_ByteCount_cy<12>: CYMUXG:u8/Mcount_ByteCount_cy<13>: GNDF:ProtoComp7.GNDF.3: GNDG:ProtoComp7.GNDG.3: XORF:u8/Mcount_ByteCount_xor<12>: XORG:u8/Mcount_ByteCount_xor<13>: _INST_PROP::XDL_SHAPE_MEMBER:Shape_2:0,6 " ; inst "u8/ByteCount<14>" "SLICEL",placed CLB_X4Y12 SLICE_X7Y23 , cfg " BXINV::#OFF BYINV::#OFF CEINV::#OFF CLKINV::CLK_B COUTUSED::#OFF CY0F::0 CY0G::#OFF CYINIT::CIN CYSELF::F CYSELG::#OFF DXMUX::1 DYMUX::1 F:u8/ByteCount<14>_rt:#LUT:D=A4 _BEL_PROP::F:PK_PACKTHRU: F5USED::#OFF FFX:u8/ByteCount_14:#FF FFX_INIT_ATTR::INIT0 FFX_SR_ATTR::SRLOW FFY:u8/ByteCount_15:#FF FFY_INIT_ATTR::INIT0 FFY_SR_ATTR::SRLOW FXMUX::FXOR FXUSED::#OFF G:u8/ByteCount<15>_rt:#LUT:D=A1 _BEL_PROP::G:PK_PACKTHRU: GYMUX::GXOR REVUSED::#OFF SRINV::SR SYNC_ATTR::ASYNC XBUSED::#OFF XUSED::#OFF YBUSED::#OFF YUSED::#OFF CYMUXF:u8/Mcount_ByteCount_cy<14>: GNDF:ProtoComp8.GNDF: XORF:u8/Mcount_ByteCount_xor<14>: XORG:u8/Mcount_ByteCount_xor<15>: _INST_PROP::XDL_SHAPE_MEMBER:Shape_2:0,7 " ; inst "u1/Result<0>2" "SLICEL",placed CLB_X16Y3 SLICE_X23Y5 , cfg " BXINV::BX BYINV::#OFF CEINV::#OFF CLKINV::#OFF COUTUSED::0 CY0F::1 CY0G::0 CYINIT::BX CYSELF::F CYSELG::G DXMUX::#OFF DYMUX::#OFF F:u1/p4/Mcount_count_lut<0>_INV_0:#LUT:D=~A4 F5USED::#OFF FFX::#OFF FFX_INIT_ATTR::#OFF FFX_SR_ATTR::#OFF FFY::#OFF FFY_INIT_ATTR::#OFF FFY_SR_ATTR::#OFF FXMUX::FXOR FXUSED::#OFF G:u1/p4/count<1>_rt:#LUT:D=A4 _BEL_PROP::G:PK_PACKTHRU: GYMUX::GXOR REVUSED::#OFF SRINV::#OFF SYNC_ATTR::#OFF XBUSED::#OFF XUSED::0 YBUSED::#OFF YUSED::0 C1VDD:ProtoComp0.C1VDD.1: CYMUXF:u1/p4/Mcount_count_cy<0>: CYMUXG:u1/p4/Mcount_count_cy<1>: GNDG:ProtoComp0.GNDG.1: XORF:u1/p4/Mcount_count_xor<0>: XORG:u1/p4/Mcount_count_xor<1>: _INST_PROP::XDL_SHAPE_DESC:Shape_3:CARRY,A\ carry\ chain\ starting\ with\ carry\ mux\ \"u1/p4/Mcount_count_cy<0>\" _INST_PROP::XDL_SHAPE_MEMBER:Shape_3:0,0 " ; inst "u1/Result<2>1" "SLICEL",placed CLB_X16Y4 SLICE_X23Y6 , cfg " BXINV::#OFF BYINV::#OFF CEINV::#OFF CLKINV::#OFF COUTUSED::0 CY0F::0 CY0G::0 CYINIT::CIN CYSELF::F CYSELG::G DXMUX::#OFF DYMUX::#OFF F:u1/p4/count<2>_rt:#LUT:D=A1 _BEL_PROP::F:PK_PACKTHRU: F5USED::#OFF FFX::#OFF FFX_INIT_ATTR::#OFF FFX_SR_ATTR::#OFF FFY::#OFF FFY_INIT_ATTR::#OFF FFY_SR_ATTR::#OFF FXMUX::FXOR FXUSED::#OFF G:u1/p4/count<3>_rt:#LUT:D=A4 _BEL_PROP::G:PK_PACKTHRU: GYMUX::GXOR REVUSED::#OFF SRINV::#OFF SYNC_ATTR::#OFF XBUSED::#OFF XUSED::0 YBUSED::#OFF YUSED::0 CYMUXF:u1/p4/Mcount_count_cy<2>: CYMUXG:u1/p4/Mcount_count_cy<3>: GNDF:ProtoComp1.GNDF.4: GNDG:ProtoComp1.GNDG.4: XORF:u1/p4/Mcount_count_xor<2>: XORG:u1/p4/Mcount_count_xor<3>: _INST_PROP::XDL_SHAPE_MEMBER:Shape_3:0,1 " ; inst "u1/Result<4>1" "SLICEL",placed CLB_X16Y4 SLICE_X23Y7 , cfg " BXINV::#OFF BYINV::#OFF CEINV::#OFF CLKINV::#OFF COUTUSED::0 CY0F::0 CY0G::0 CYINIT::CIN CYSELF::F CYSELG::G DXMUX::#OFF DYMUX::#OFF F:u1/p4/count<4>_rt:#LUT:D=A2 _BEL_PROP::F:PK_PACKTHRU: F5USED::#OFF FFX::#OFF FFX_INIT_ATTR::#OFF FFX_SR_ATTR::#OFF FFY::#OFF FFY_INIT_ATTR::#OFF FFY_SR_ATTR::#OFF FXMUX::FXOR FXUSED::#OFF G:u1/p4/count<5>_rt:#LUT:D=A3 _BEL_PROP::G:PK_PACKTHRU: GYMUX::GXOR REVUSED::#OFF SRINV::#OFF SYNC_ATTR::#OFF XBUSED::#OFF XUSED::0 YBUSED::#OFF YUSED::0 CYMUXF:u1/p4/Mcount_count_cy<4>: CYMUXG:u1/p4/Mcount_count_cy<5>: GNDF:ProtoComp1.GNDF.5: GNDG:ProtoComp1.GNDG.5: XORF:u1/p4/Mcount_count_xor<4>: XORG:u1/p4/Mcount_count_xor<5>: _INST_PROP::XDL_SHAPE_MEMBER:Shape_3:0,2 " ; inst "u1/Result<6>1" "SLICEL",placed CLB_X16Y5 SLICE_X23Y8 , cfg " BXINV::#OFF BYINV::#OFF CEINV::#OFF CLKINV::#OFF COUTUSED::0 CY0F::0 CY0G::0 CYINIT::CIN CYSELF::F CYSELG::G DXMUX::#OFF DYMUX::#OFF F:u1/p4/count<6>_rt:#LUT:D=A4 _BEL_PROP::F:PK_PACKTHRU: F5USED::#OFF FFX::#OFF FFX_INIT_ATTR::#OFF FFX_SR_ATTR::#OFF FFY::#OFF FFY_INIT_ATTR::#OFF FFY_SR_ATTR::#OFF FXMUX::FXOR FXUSED::#OFF G:u1/p4/count<7>_rt:#LUT:D=A1 _BEL_PROP::G:PK_PACKTHRU: GYMUX::GXOR REVUSED::#OFF SRINV::#OFF SYNC_ATTR::#OFF XBUSED::#OFF XUSED::0 YBUSED::#OFF YUSED::0 CYMUXF:u1/p4/Mcount_count_cy<6>: CYMUXG:u1/p4/Mcount_count_cy<7>: GNDF:ProtoComp1.GNDF.6: GNDG:ProtoComp1.GNDG.6: XORF:u1/p4/Mcount_count_xor<6>: XORG:u1/p4/Mcount_count_xor<7>: _INST_PROP::XDL_SHAPE_MEMBER:Shape_3:0,3 " ; inst "u1/Result<8>1" "SLICEL",placed CLB_X16Y5 SLICE_X23Y9 , cfg " BXINV::#OFF BYINV::#OFF CEINV::#OFF CLKINV::#OFF COUTUSED::0 CY0F::0 CY0G::0 CYINIT::CIN CYSELF::F CYSELG::G DXMUX::#OFF DYMUX::#OFF F:u1/p4/count<8>_rt:#LUT:D=A3 _BEL_PROP::F:PK_PACKTHRU: F5USED::#OFF FFX::#OFF FFX_INIT_ATTR::#OFF FFX_SR_ATTR::#OFF FFY::#OFF FFY_INIT_ATTR::#OFF FFY_SR_ATTR::#OFF FXMUX::FXOR FXUSED::#OFF G:u1/p4/count<9>_rt:#LUT:D=A1 _BEL_PROP::G:PK_PACKTHRU: GYMUX::GXOR REVUSED::#OFF SRINV::#OFF SYNC_ATTR::#OFF XBUSED::#OFF XUSED::0 YBUSED::#OFF YUSED::0 CYMUXF:u1/p4/Mcount_count_cy<8>: CYMUXG:u1/p4/Mcount_count_cy<9>: GNDF:ProtoComp1.GNDF.7: GNDG:ProtoComp1.GNDG.7: XORF:u1/p4/Mcount_count_xor<8>: XORG:u1/p4/Mcount_count_xor<9>: _INST_PROP::XDL_SHAPE_MEMBER:Shape_3:0,4 " ; inst "u1/Result<10>1" "SLICEL",placed CLB_X16Y6 SLICE_X23Y10 , cfg " BXINV::#OFF BYINV::#OFF CEINV::#OFF CLKINV::#OFF COUTUSED::#OFF CY0F::0 CY0G::#OFF CYINIT::CIN CYSELF::F CYSELG::#OFF DXMUX::#OFF DYMUX::#OFF F:u1/p4/count<10>_rt:#LUT:D=A4 _BEL_PROP::F:PK_PACKTHRU: F5USED::#OFF FFX::#OFF FFX_INIT_ATTR::#OFF FFX_SR_ATTR::#OFF FFY::#OFF FFY_INIT_ATTR::#OFF FFY_SR_ATTR::#OFF FXMUX::FXOR FXUSED::#OFF G:u1/p4/count<11>_rt:#LUT:D=A1 _BEL_PROP::G:PK_PACKTHRU: GYMUX::GXOR REVUSED::#OFF SRINV::#OFF SYNC_ATTR::#OFF XBUSED::#OFF XUSED::0 YBUSED::#OFF YUSED::0 CYMUXF:u1/p4/Mcount_count_cy<10>: GNDF:ProtoComp2.GNDF.1: XORF:u1/p4/Mcount_count_xor<10>: XORG:u1/p4/Mcount_count_xor<11>: _INST_PROP::XDL_SHAPE_MEMBER:Shape_3:0,5 " ; inst "SPI_SDI" "IOB",placed TIOIS_X10Y17 P84 , cfg " DELAY_ADJ_ATTRBOX::#OFF DRIVEATTRBOX::12 DRIVE_0MA::#OFF GTSATTRBOX::#OFF IBUF_DELAY_VALUE::#OFF ICEINV::#OFF ICLK1INV::#OFF ICLK2INV::#OFF IDDRIN_MUX::#OFF IFD_DELAY_VALUE::#OFF IFF1::#OFF IFF1_INIT_ATTR::#OFF IFF1_SR_ATTR::#OFF IFF2::#OFF IFF2_INIT_ATTR::#OFF IFF2_SR_ATTR::#OFF IFFATTRBOX::#OFF IFFDMUX::#OFF IMUX::#OFF IOATTRBOX::LVCMOS33 IREV_USED::#OFF ISR_USED::#OFF MISRATTRBOX::#OFF MISR_CLK_SELECT::#OFF O1INV::O1 O1_DDRMUX::#OFF O2INV::#OFF O2_DDRMUX::#OFF OCEINV::#OFF ODDROUT1_MUX::#OFF ODDROUT2_MUX::#OFF OFF1::#OFF OFF1_INIT_ATTR::#OFF OFF1_SR_ATTR::#OFF OFF2::#OFF OFF2_INIT_ATTR::#OFF OFF2_SR_ATTR::#OFF OFFATTRBOX::#OFF OMUX::O1 OREV_USED::#OFF OSR_USED::#OFF OTCLK1INV::#OFF OTCLK2INV::#OFF PCICE_MUX::#OFF PCIRDY_MUX::#OFF PULL::#OFF REVINV::#OFF SEL_MUX::#OFF SLEW::SLOW SRINV::#OFF SUSPEND::3STATE T1INV::#OFF T2INV::#OFF TCEINV::#OFF TFF1::#OFF TFF1_INIT_ATTR::#OFF TFF1_SR_ATTR::#OFF TFF2::#OFF TFF2_INIT_ATTR::#OFF TFF2_SR_ATTR::#OFF TFFATTRBOX::#OFF TMUX::#OFF TREV_USED::#OFF TSMUX::#OFF TSR_USED::#OFF T_USED::#OFF OUTBUF:SPI_SDI_OBUF: PAD:SPI_SDI: " ; inst "SPI_SDO" "IBUF",placed LIOIS_X0Y16 P4 , cfg " DELAY_ADJ_ATTRBOX::FIXED GTSATTRBOX::#OFF IBUF_DELAY_VALUE::DLY0 ICEINV::#OFF ICLK1INV::#OFF ICLK2INV::#OFF IDDRIN_MUX::#OFF IFD_DELAY_VALUE::DLY0 IFF1::#OFF IFF1_INIT_ATTR::#OFF IFF1_SR_ATTR::#OFF IFF2::#OFF IFF2_INIT_ATTR::#OFF IFF2_SR_ATTR::#OFF IFFATTRBOX::#OFF IFFDMUX::#OFF IMUX::1 IOATTRBOX::LVCMOS33 IREV_USED::#OFF ISR_USED::#OFF MISRATTRBOX::#OFF MISR_CLK_SELECT::#OFF O1INV::#OFF O1_DDRMUX::#OFF O2INV::#OFF O2_DDRMUX::#OFF OCEINV::#OFF ODDROUT1_MUX::#OFF ODDROUT2_MUX::#OFF OFF1::#OFF OFF1_INIT_ATTR::#OFF OFF1_SR_ATTR::#OFF OFF2::#OFF OFF2_INIT_ATTR::#OFF OFF2_SR_ATTR::#OFF OFFATTRBOX::#OFF OMUX::#OFF OREV_USED::#OFF OSR_USED::#OFF OTCLK1INV::#OFF OTCLK2INV::#OFF PCICE_MUX::#OFF PCIRDY_MUX::#OFF PULL::#OFF REVINV::#OFF SEL_MUX::0 SLEW::#OFF SRINV::#OFF T1INV::#OFF T2INV::#OFF TCEINV::#OFF TFF1::#OFF TFF1_INIT_ATTR::#OFF TFF1_SR_ATTR::#OFF TFF2::#OFF TFF2_INIT_ATTR::#OFF TFF2_SR_ATTR::#OFF TFFATTRBOX::#OFF TMUX::#OFF TREV_USED::#OFF TSMUX::#OFF TSR_USED::#OFF T_USED::#OFF DELAY_ADJ_BBOX:SPI_SDO.DELAY_ADJ: INBUF:SPI_SDO_IBUF: PAD:SPI_SDO: " ; inst "SPI_A_iCS" "IOB",placed LIOIS_X0Y16 P3 , cfg " DELAY_ADJ_ATTRBOX::#OFF DRIVEATTRBOX::12 DRIVE_0MA::#OFF GTSATTRBOX::#OFF IBUF_DELAY_VALUE::#OFF ICEINV::#OFF ICLK1INV::#OFF ICLK2INV::#OFF IDDRIN_MUX::#OFF IFD_DELAY_VALUE::#OFF IFF1::#OFF IFF1_INIT_ATTR::#OFF IFF1_SR_ATTR::#OFF IFF2::#OFF IFF2_INIT_ATTR::#OFF IFF2_SR_ATTR::#OFF IFFATTRBOX::#OFF IFFDMUX::#OFF IMUX::#OFF IOATTRBOX::LVCMOS33 IREV_USED::#OFF ISR_USED::#OFF MISRATTRBOX::#OFF MISR_CLK_SELECT::#OFF O1INV::O1 O1_DDRMUX::#OFF O2INV::#OFF O2_DDRMUX::#OFF OCEINV::#OFF ODDROUT1_MUX::#OFF ODDROUT2_MUX::#OFF OFF1::#OFF OFF1_INIT_ATTR::#OFF OFF1_SR_ATTR::#OFF OFF2::#OFF OFF2_INIT_ATTR::#OFF OFF2_SR_ATTR::#OFF OFFATTRBOX::#OFF OMUX::O1 OREV_USED::#OFF OSR_USED::#OFF OTCLK1INV::#OFF OTCLK2INV::#OFF PCICE_MUX::#OFF PCIRDY_MUX::#OFF PULL::#OFF REVINV::#OFF SEL_MUX::#OFF SLEW::SLOW SRINV::#OFF SUSPEND::3STATE T1INV::#OFF T2INV::#OFF TCEINV::#OFF TFF1::#OFF TFF1_INIT_ATTR::#OFF TFF1_SR_ATTR::#OFF TFF2::#OFF TFF2_INIT_ATTR::#OFF TFF2_SR_ATTR::#OFF TFFATTRBOX::#OFF TMUX::#OFF TREV_USED::#OFF TSMUX::#OFF TSR_USED::#OFF T_USED::#OFF OUTBUF:SPI_A_iCS_OBUF: PAD:SPI_A_iCS: " ; inst "Eth_iINT" "IBUF",placed BIOIS_X6Y0 P35 , cfg " DELAY_ADJ_ATTRBOX::FIXED GTSATTRBOX::#OFF IBUF_DELAY_VALUE::DLY0 ICEINV::#OFF ICLK1INV::#OFF ICLK2INV::#OFF IDDRIN_MUX::#OFF IFD_DELAY_VALUE::DLY0 IFF1::#OFF IFF1_INIT_ATTR::#OFF IFF1_SR_ATTR::#OFF IFF2::#OFF IFF2_INIT_ATTR::#OFF IFF2_SR_ATTR::#OFF IFFATTRBOX::#OFF IFFDMUX::#OFF IMUX::1 IOATTRBOX::LVCMOS33 IREV_USED::#OFF ISR_USED::#OFF MISRATTRBOX::#OFF MISR_CLK_SELECT::#OFF O1INV::#OFF O1_DDRMUX::#OFF O2INV::#OFF O2_DDRMUX::#OFF OCEINV::#OFF ODDROUT1_MUX::#OFF ODDROUT2_MUX::#OFF OFF1::#OFF OFF1_INIT_ATTR::#OFF OFF1_SR_ATTR::#OFF OFF2::#OFF OFF2_INIT_ATTR::#OFF OFF2_SR_ATTR::#OFF OFFATTRBOX::#OFF OMUX::#OFF OREV_USED::#OFF OSR_USED::#OFF OTCLK1INV::#OFF OTCLK2INV::#OFF PCICE_MUX::#OFF PCIRDY_MUX::#OFF PULL::#OFF REVINV::#OFF SEL_MUX::0 SLEW::#OFF SRINV::#OFF T1INV::#OFF T2INV::#OFF TCEINV::#OFF TFF1::#OFF TFF1_INIT_ATTR::#OFF TFF1_SR_ATTR::#OFF TFF2::#OFF TFF2_INIT_ATTR::#OFF TFF2_SR_ATTR::#OFF TFFATTRBOX::#OFF TMUX::#OFF TREV_USED::#OFF TSMUX::#OFF TSR_USED::#OFF T_USED::#OFF DELAY_ADJ_BBOX:Eth_iINT.DELAY_ADJ: INBUF:Eth_iINT_IBUF: PAD:Eth_iINT: " ; inst "DAC_serISync" "IOB",placed TIOIS_X8Y17 P88 , cfg " DELAY_ADJ_ATTRBOX::#OFF DRIVEATTRBOX::12 DRIVE_0MA::#OFF GTSATTRBOX::#OFF IBUF_DELAY_VALUE::#OFF ICEINV::#OFF ICLK1INV::#OFF ICLK2INV::#OFF IDDRIN_MUX::#OFF IFD_DELAY_VALUE::#OFF IFF1::#OFF IFF1_INIT_ATTR::#OFF IFF1_SR_ATTR::#OFF IFF2::#OFF IFF2_INIT_ATTR::#OFF IFF2_SR_ATTR::#OFF IFFATTRBOX::#OFF IFFDMUX::#OFF IMUX::#OFF IOATTRBOX::LVCMOS33 IREV_USED::#OFF ISR_USED::#OFF MISRATTRBOX::#OFF MISR_CLK_SELECT::#OFF O1INV::O1 O1_DDRMUX::#OFF O2INV::#OFF O2_DDRMUX::#OFF OCEINV::#OFF ODDROUT1_MUX::#OFF ODDROUT2_MUX::#OFF OFF1::#OFF OFF1_INIT_ATTR::#OFF OFF1_SR_ATTR::#OFF OFF2::#OFF OFF2_INIT_ATTR::#OFF OFF2_SR_ATTR::#OFF OFFATTRBOX::#OFF OMUX::O1 OREV_USED::#OFF OSR_USED::#OFF OTCLK1INV::#OFF OTCLK2INV::#OFF PCICE_MUX::#OFF PCIRDY_MUX::#OFF PULL::#OFF REVINV::#OFF SEL_MUX::#OFF SLEW::SLOW SRINV::#OFF SUSPEND::3STATE T1INV::#OFF T2INV::#OFF TCEINV::#OFF TFF1::#OFF TFF1_INIT_ATTR::#OFF TFF1_SR_ATTR::#OFF TFF2::#OFF TFF2_INIT_ATTR::#OFF TFF2_SR_ATTR::#OFF TFFATTRBOX::#OFF TMUX::#OFF TREV_USED::#OFF TSMUX::#OFF TSR_USED::#OFF T_USED::#OFF OUTBUF:DAC_serISync_OBUF: PAD:DAC_serISync: " ; inst "SPI_iRst_out" "IOB",placed TIOIB_X5Y17 P94 , cfg " DELAY_ADJ_ATTRBOX::#OFF DRIVEATTRBOX::12 DRIVE_0MA::#OFF GTSATTRBOX::#OFF IBUF_DELAY_VALUE::#OFF ICEINV::#OFF ICLK1INV::#OFF ICLK2INV::#OFF IDDRIN_MUX::#OFF IFD_DELAY_VALUE::#OFF IFF1::#OFF IFF1_INIT_ATTR::#OFF IFF1_SR_ATTR::#OFF IFF2::#OFF IFF2_INIT_ATTR::#OFF IFF2_SR_ATTR::#OFF IFFATTRBOX::#OFF IFFDMUX::#OFF IMUX::#OFF IOATTRBOX::LVCMOS33 IREV_USED::#OFF ISR_USED::#OFF MISRATTRBOX::#OFF MISR_CLK_SELECT::#OFF O1INV::O1 O1_DDRMUX::#OFF O2INV::#OFF O2_DDRMUX::#OFF OCEINV::#OFF ODDROUT1_MUX::#OFF ODDROUT2_MUX::#OFF OFF1::#OFF OFF1_INIT_ATTR::#OFF OFF1_SR_ATTR::#OFF OFF2::#OFF OFF2_INIT_ATTR::#OFF OFF2_SR_ATTR::#OFF OFFATTRBOX::#OFF OMUX::O1 OREV_USED::#OFF OSR_USED::#OFF OTCLK1INV::#OFF OTCLK2INV::#OFF PCICE_MUX::#OFF PCIRDY_MUX::#OFF PULL::#OFF REVINV::#OFF SEL_MUX::#OFF SLEW::SLOW SRINV::#OFF SUSPEND::3STATE T1INV::#OFF T2INV::#OFF TCEINV::#OFF TFF1::#OFF TFF1_INIT_ATTR::#OFF TFF1_SR_ATTR::#OFF TFF2::#OFF TFF2_INIT_ATTR::#OFF TFF2_SR_ATTR::#OFF TFFATTRBOX::#OFF TMUX::#OFF TREV_USED::#OFF TSMUX::#OFF TSR_USED::#OFF T_USED::#OFF OUTBUF:SPI_iRst_out_OBUF: PAD:SPI_iRst_out: " ; inst "dbShort" "IBUF",placed TIOIS_X10Y17 P83 , cfg " DELAY_ADJ_ATTRBOX::FIXED GTSATTRBOX::#OFF IBUF_DELAY_VALUE::DLY0 ICEINV::#OFF ICLK1INV::#OFF ICLK2INV::#OFF IDDRIN_MUX::#OFF IFD_DELAY_VALUE::DLY0 IFF1::#OFF IFF1_INIT_ATTR::#OFF IFF1_SR_ATTR::#OFF IFF2::#OFF IFF2_INIT_ATTR::#OFF IFF2_SR_ATTR::#OFF IFFATTRBOX::#OFF IFFDMUX::#OFF IMUX::1 IOATTRBOX::LVCMOS33 IREV_USED::#OFF ISR_USED::#OFF MISRATTRBOX::#OFF MISR_CLK_SELECT::#OFF O1INV::#OFF O1_DDRMUX::#OFF O2INV::#OFF O2_DDRMUX::#OFF OCEINV::#OFF ODDROUT1_MUX::#OFF ODDROUT2_MUX::#OFF OFF1::#OFF OFF1_INIT_ATTR::#OFF OFF1_SR_ATTR::#OFF OFF2::#OFF OFF2_INIT_ATTR::#OFF OFF2_SR_ATTR::#OFF OFFATTRBOX::#OFF OMUX::#OFF OREV_USED::#OFF OSR_USED::#OFF OTCLK1INV::#OFF OTCLK2INV::#OFF PCICE_MUX::#OFF PCIRDY_MUX::#OFF PULL::#OFF REVINV::#OFF SEL_MUX::0 SLEW::#OFF SRINV::#OFF T1INV::#OFF T2INV::#OFF TCEINV::#OFF TFF1::#OFF TFF1_INIT_ATTR::#OFF TFF1_SR_ATTR::#OFF TFF2::#OFF TFF2_INIT_ATTR::#OFF TFF2_SR_ATTR::#OFF TFFATTRBOX::#OFF TMUX::#OFF TREV_USED::#OFF TSMUX::#OFF TSR_USED::#OFF T_USED::#OFF DELAY_ADJ_BBOX:dbShort.DELAY_ADJ: INBUF:dbShort_IBUF: PAD:dbShort: " ; inst "fClk" "IBUF",placed BIOIS_X2Y0 P27 , cfg " DELAY_ADJ_ATTRBOX::FIXED GTSATTRBOX::#OFF IBUF_DELAY_VALUE::DLY0 ICEINV::#OFF ICLK1INV::#OFF ICLK2INV::#OFF IDDRIN_MUX::#OFF IFD_DELAY_VALUE::DLY0 IFF1::#OFF IFF1_INIT_ATTR::#OFF IFF1_SR_ATTR::#OFF IFF2::#OFF IFF2_INIT_ATTR::#OFF IFF2_SR_ATTR::#OFF IFFATTRBOX::#OFF IFFDMUX::#OFF IMUX::1 IOATTRBOX::LVCMOS33 IREV_USED::#OFF ISR_USED::#OFF MISRATTRBOX::#OFF MISR_CLK_SELECT::#OFF O1INV::#OFF O1_DDRMUX::#OFF O2INV::#OFF O2_DDRMUX::#OFF OCEINV::#OFF ODDROUT1_MUX::#OFF ODDROUT2_MUX::#OFF OFF1::#OFF OFF1_INIT_ATTR::#OFF OFF1_SR_ATTR::#OFF OFF2::#OFF OFF2_INIT_ATTR::#OFF OFF2_SR_ATTR::#OFF OFFATTRBOX::#OFF OMUX::#OFF OREV_USED::#OFF OSR_USED::#OFF OTCLK1INV::#OFF OTCLK2INV::#OFF PCICE_MUX::#OFF PCIRDY_MUX::#OFF PULL::#OFF REVINV::#OFF SEL_MUX::0 SLEW::#OFF SRINV::#OFF T1INV::#OFF T2INV::#OFF TCEINV::#OFF TFF1::#OFF TFF1_INIT_ATTR::#OFF TFF1_SR_ATTR::#OFF TFF2::#OFF TFF2_INIT_ATTR::#OFF TFF2_SR_ATTR::#OFF TFFATTRBOX::#OFF TMUX::#OFF TREV_USED::#OFF TSMUX::#OFF TSR_USED::#OFF T_USED::#OFF DELAY_ADJ_BBOX:fClk.DELAY_ADJ: INBUF:fClk_BUFGP/IBUFG: PAD:fClk: " ; inst "Eth_iRst" "IOB",placed BIOIB_X11Y0 P46 , cfg " DELAY_ADJ_ATTRBOX::#OFF DRIVEATTRBOX::12 DRIVE_0MA::#OFF GTSATTRBOX::#OFF IBUF_DELAY_VALUE::#OFF ICEINV::#OFF ICLK1INV::#OFF ICLK2INV::#OFF IDDRIN_MUX::#OFF IFD_DELAY_VALUE::#OFF IFF1::#OFF IFF1_INIT_ATTR::#OFF IFF1_SR_ATTR::#OFF IFF2::#OFF IFF2_INIT_ATTR::#OFF IFF2_SR_ATTR::#OFF IFFATTRBOX::#OFF IFFDMUX::#OFF IMUX::#OFF IOATTRBOX::LVCMOS33 IREV_USED::#OFF ISR_USED::#OFF MISRATTRBOX::#OFF MISR_CLK_SELECT::#OFF O1INV::O1 O1_DDRMUX::#OFF O2INV::#OFF O2_DDRMUX::#OFF OCEINV::#OFF ODDROUT1_MUX::#OFF ODDROUT2_MUX::#OFF OFF1::#OFF OFF1_INIT_ATTR::#OFF OFF1_SR_ATTR::#OFF OFF2::#OFF OFF2_INIT_ATTR::#OFF OFF2_SR_ATTR::#OFF OFFATTRBOX::#OFF OMUX::O1 OREV_USED::#OFF OSR_USED::#OFF OTCLK1INV::#OFF OTCLK2INV::#OFF PCICE_MUX::#OFF PCIRDY_MUX::#OFF PULL::PULLUP REVINV::#OFF SEL_MUX::#OFF SLEW::SLOW SRINV::#OFF SUSPEND::3STATE T1INV::T1 T2INV::#OFF TCEINV::#OFF TFF1::#OFF TFF1_INIT_ATTR::#OFF TFF1_SR_ATTR::#OFF TFF2::#OFF TFF2_INIT_ATTR::#OFF TFF2_SR_ATTR::#OFF TFFATTRBOX::#OFF TMUX::T1 TREV_USED::#OFF TSMUX::#OFF TSR_USED::#OFF T_USED::#OFF OUTBUF:Eth_iRst_OBUFT: PAD:Eth_iRst: " ; inst "ALE" "IOB",placed BIOIB_X9Y0 P44 , cfg " DELAY_ADJ_ATTRBOX::#OFF DRIVEATTRBOX::12 DRIVE_0MA::#OFF GTSATTRBOX::#OFF IBUF_DELAY_VALUE::#OFF ICEINV::#OFF ICLK1INV::#OFF ICLK2INV::#OFF IDDRIN_MUX::#OFF IFD_DELAY_VALUE::#OFF IFF1::#OFF IFF1_INIT_ATTR::#OFF IFF1_SR_ATTR::#OFF IFF2::#OFF IFF2_INIT_ATTR::#OFF IFF2_SR_ATTR::#OFF IFFATTRBOX::#OFF IFFDMUX::#OFF IMUX::#OFF IOATTRBOX::LVCMOS33 IREV_USED::#OFF ISR_USED::#OFF MISRATTRBOX::#OFF MISR_CLK_SELECT::#OFF O1INV::O1 O1_DDRMUX::1 O2INV::#OFF O2_DDRMUX::#OFF OCEINV::#OFF ODDROUT1_MUX::#OFF ODDROUT2_MUX::#OFF OFF1:u0/u2/ALE:#LATCH OFF1_INIT_ATTR::INIT0 OFF1_SR_ATTR::#OFF OFF2::#OFF OFF2_INIT_ATTR::#OFF OFF2_SR_ATTR::#OFF OFFATTRBOX::#OFF OMUX::OFF1 OREV_USED::#OFF OSR_USED::#OFF OTCLK1INV::OTCLK1_B OTCLK2INV::#OFF PCICE_MUX::#OFF PCIRDY_MUX::#OFF PULL::#OFF REVINV::#OFF SEL_MUX::#OFF SLEW::SLOW SRINV::#OFF SUSPEND::3STATE T1INV::#OFF T2INV::#OFF TCEINV::#OFF TFF1::#OFF TFF1_INIT_ATTR::#OFF TFF1_SR_ATTR::#OFF TFF2::#OFF TFF2_INIT_ATTR::#OFF TFF2_SR_ATTR::#OFF TFFATTRBOX::#OFF TMUX::#OFF TREV_USED::#OFF TSMUX::#OFF TSR_USED::#OFF T_USED::#OFF OUTBUF:ALE_OBUF: PAD:ALE: " ; inst "LocStamp<0>" "IBUF",placed RIOIS_X17Y15 P73 , cfg " DELAY_ADJ_ATTRBOX::FIXED GTSATTRBOX::#OFF IBUF_DELAY_VALUE::DLY0 ICEINV::#OFF ICLK1INV::#OFF ICLK2INV::#OFF IDDRIN_MUX::#OFF IFD_DELAY_VALUE::DLY0 IFF1::#OFF IFF1_INIT_ATTR::#OFF IFF1_SR_ATTR::#OFF IFF2::#OFF IFF2_INIT_ATTR::#OFF IFF2_SR_ATTR::#OFF IFFATTRBOX::#OFF IFFDMUX::#OFF IMUX::1 IOATTRBOX::LVCMOS33 IREV_USED::#OFF ISR_USED::#OFF MISRATTRBOX::#OFF MISR_CLK_SELECT::#OFF O1INV::#OFF O1_DDRMUX::#OFF O2INV::#OFF O2_DDRMUX::#OFF OCEINV::#OFF ODDROUT1_MUX::#OFF ODDROUT2_MUX::#OFF OFF1::#OFF OFF1_INIT_ATTR::#OFF OFF1_SR_ATTR::#OFF OFF2::#OFF OFF2_INIT_ATTR::#OFF OFF2_SR_ATTR::#OFF OFFATTRBOX::#OFF OMUX::#OFF OREV_USED::#OFF OSR_USED::#OFF OTCLK1INV::#OFF OTCLK2INV::#OFF PCICE_MUX::#OFF PCIRDY_MUX::#OFF PULL::PULLUP REVINV::#OFF SEL_MUX::0 SLEW::#OFF SRINV::#OFF T1INV::#OFF T2INV::#OFF TCEINV::#OFF TFF1::#OFF TFF1_INIT_ATTR::#OFF TFF1_SR_ATTR::#OFF TFF2::#OFF TFF2_INIT_ATTR::#OFF TFF2_SR_ATTR::#OFF TFFATTRBOX::#OFF TMUX::#OFF TREV_USED::#OFF TSMUX::#OFF TSR_USED::#OFF T_USED::#OFF DELAY_ADJ_BBOX:LocStamp<0>.DELAY_ADJ: INBUF:LocStamp_0_IBUF: PAD:LocStamp<0>: " ; inst "LocStamp<1>" "IBUF",placed RIOIS_X17Y15 P72 , cfg " DELAY_ADJ_ATTRBOX::FIXED GTSATTRBOX::#OFF IBUF_DELAY_VALUE::DLY0 ICEINV::#OFF ICLK1INV::#OFF ICLK2INV::#OFF IDDRIN_MUX::#OFF IFD_DELAY_VALUE::DLY0 IFF1::#OFF IFF1_INIT_ATTR::#OFF IFF1_SR_ATTR::#OFF IFF2::#OFF IFF2_INIT_ATTR::#OFF IFF2_SR_ATTR::#OFF IFFATTRBOX::#OFF IFFDMUX::#OFF IMUX::1 IOATTRBOX::LVCMOS33 IREV_USED::#OFF ISR_USED::#OFF MISRATTRBOX::#OFF MISR_CLK_SELECT::#OFF O1INV::#OFF O1_DDRMUX::#OFF O2INV::#OFF O2_DDRMUX::#OFF OCEINV::#OFF ODDROUT1_MUX::#OFF ODDROUT2_MUX::#OFF OFF1::#OFF OFF1_INIT_ATTR::#OFF OFF1_SR_ATTR::#OFF OFF2::#OFF OFF2_INIT_ATTR::#OFF OFF2_SR_ATTR::#OFF OFFATTRBOX::#OFF OMUX::#OFF OREV_USED::#OFF OSR_USED::#OFF OTCLK1INV::#OFF OTCLK2INV::#OFF PCICE_MUX::#OFF PCIRDY_MUX::#OFF PULL::PULLUP REVINV::#OFF SEL_MUX::0 SLEW::#OFF SRINV::#OFF T1INV::#OFF T2INV::#OFF TCEINV::#OFF TFF1::#OFF TFF1_INIT_ATTR::#OFF TFF1_SR_ATTR::#OFF TFF2::#OFF TFF2_INIT_ATTR::#OFF TFF2_SR_ATTR::#OFF TFFATTRBOX::#OFF TMUX::#OFF TREV_USED::#OFF TSMUX::#OFF TSR_USED::#OFF T_USED::#OFF DELAY_ADJ_BBOX:LocStamp<1>.DELAY_ADJ: INBUF:LocStamp_1_IBUF: PAD:LocStamp<1>: " ; inst "LocStamp<2>" "IBUF",placed RIOIS_X17Y13 P71 , cfg " DELAY_ADJ_ATTRBOX::FIXED GTSATTRBOX::#OFF IBUF_DELAY_VALUE::DLY0 ICEINV::#OFF ICLK1INV::#OFF ICLK2INV::#OFF IDDRIN_MUX::#OFF IFD_DELAY_VALUE::DLY0 IFF1::#OFF IFF1_INIT_ATTR::#OFF IFF1_SR_ATTR::#OFF IFF2::#OFF IFF2_INIT_ATTR::#OFF IFF2_SR_ATTR::#OFF IFFATTRBOX::#OFF IFFDMUX::#OFF IMUX::1 IOATTRBOX::LVCMOS33 IREV_USED::#OFF ISR_USED::#OFF MISRATTRBOX::#OFF MISR_CLK_SELECT::#OFF O1INV::#OFF O1_DDRMUX::#OFF O2INV::#OFF O2_DDRMUX::#OFF OCEINV::#OFF ODDROUT1_MUX::#OFF ODDROUT2_MUX::#OFF OFF1::#OFF OFF1_INIT_ATTR::#OFF OFF1_SR_ATTR::#OFF OFF2::#OFF OFF2_INIT_ATTR::#OFF OFF2_SR_ATTR::#OFF OFFATTRBOX::#OFF OMUX::#OFF OREV_USED::#OFF OSR_USED::#OFF OTCLK1INV::#OFF OTCLK2INV::#OFF PCICE_MUX::#OFF PCIRDY_MUX::#OFF PULL::PULLUP REVINV::#OFF SEL_MUX::0 SLEW::#OFF SRINV::#OFF T1INV::#OFF T2INV::#OFF TCEINV::#OFF TFF1::#OFF TFF1_INIT_ATTR::#OFF TFF1_SR_ATTR::#OFF TFF2::#OFF TFF2_INIT_ATTR::#OFF TFF2_SR_ATTR::#OFF TFFATTRBOX::#OFF TMUX::#OFF TREV_USED::#OFF TSMUX::#OFF TSR_USED::#OFF T_USED::#OFF DELAY_ADJ_BBOX:LocStamp<2>.DELAY_ADJ: INBUF:LocStamp_2_IBUF: PAD:LocStamp<2>: " ; inst "LocStamp<3>" "IBUF",placed RIOIS_X17Y13 P70 , cfg " DELAY_ADJ_ATTRBOX::FIXED GTSATTRBOX::#OFF IBUF_DELAY_VALUE::DLY0 ICEINV::#OFF ICLK1INV::#OFF ICLK2INV::#OFF IDDRIN_MUX::#OFF IFD_DELAY_VALUE::DLY0 IFF1::#OFF IFF1_INIT_ATTR::#OFF IFF1_SR_ATTR::#OFF IFF2::#OFF IFF2_INIT_ATTR::#OFF IFF2_SR_ATTR::#OFF IFFATTRBOX::#OFF IFFDMUX::#OFF IMUX::1 IOATTRBOX::LVCMOS33 IREV_USED::#OFF ISR_USED::#OFF MISRATTRBOX::#OFF MISR_CLK_SELECT::#OFF O1INV::#OFF O1_DDRMUX::#OFF O2INV::#OFF O2_DDRMUX::#OFF OCEINV::#OFF ODDROUT1_MUX::#OFF ODDROUT2_MUX::#OFF OFF1::#OFF OFF1_INIT_ATTR::#OFF OFF1_SR_ATTR::#OFF OFF2::#OFF OFF2_INIT_ATTR::#OFF OFF2_SR_ATTR::#OFF OFFATTRBOX::#OFF OMUX::#OFF OREV_USED::#OFF OSR_USED::#OFF OTCLK1INV::#OFF OTCLK2INV::#OFF PCICE_MUX::#OFF PCIRDY_MUX::#OFF PULL::PULLUP REVINV::#OFF SEL_MUX::0 SLEW::#OFF SRINV::#OFF T1INV::#OFF T2INV::#OFF TCEINV::#OFF TFF1::#OFF TFF1_INIT_ATTR::#OFF TFF1_SR_ATTR::#OFF TFF2::#OFF TFF2_INIT_ATTR::#OFF TFF2_SR_ATTR::#OFF TFFATTRBOX::#OFF TMUX::#OFF TREV_USED::#OFF TSMUX::#OFF TSR_USED::#OFF T_USED::#OFF DELAY_ADJ_BBOX:LocStamp<3>.DELAY_ADJ: INBUF:LocStamp_3_IBUF: PAD:LocStamp<3>: " ; inst "LocStamp<4>" "IBUF",placed TIOIB_X15Y17 P77 , cfg " DELAY_ADJ_ATTRBOX::FIXED GTSATTRBOX::#OFF IBUF_DELAY_VALUE::DLY0 ICEINV::#OFF ICLK1INV::#OFF ICLK2INV::#OFF IDDRIN_MUX::#OFF IFD_DELAY_VALUE::DLY0 IFF1::#OFF IFF1_INIT_ATTR::#OFF IFF1_SR_ATTR::#OFF IFF2::#OFF IFF2_INIT_ATTR::#OFF IFF2_SR_ATTR::#OFF IFFATTRBOX::#OFF IFFDMUX::#OFF IMUX::1 IOATTRBOX::LVCMOS33 IREV_USED::#OFF ISR_USED::#OFF MISRATTRBOX::#OFF MISR_CLK_SELECT::#OFF O1INV::#OFF O1_DDRMUX::#OFF O2INV::#OFF O2_DDRMUX::#OFF OCEINV::#OFF ODDROUT1_MUX::#OFF ODDROUT2_MUX::#OFF OFF1::#OFF OFF1_INIT_ATTR::#OFF OFF1_SR_ATTR::#OFF OFF2::#OFF OFF2_INIT_ATTR::#OFF OFF2_SR_ATTR::#OFF OFFATTRBOX::#OFF OMUX::#OFF OREV_USED::#OFF OSR_USED::#OFF OTCLK1INV::#OFF OTCLK2INV::#OFF PCICE_MUX::#OFF PCIRDY_MUX::#OFF PULL::PULLUP REVINV::#OFF SEL_MUX::0 SLEW::#OFF SRINV::#OFF T1INV::#OFF T2INV::#OFF TCEINV::#OFF TFF1::#OFF TFF1_INIT_ATTR::#OFF TFF1_SR_ATTR::#OFF TFF2::#OFF TFF2_INIT_ATTR::#OFF TFF2_SR_ATTR::#OFF TFFATTRBOX::#OFF TMUX::#OFF TREV_USED::#OFF TSMUX::#OFF TSR_USED::#OFF T_USED::#OFF DELAY_ADJ_BBOX:LocStamp<4>.DELAY_ADJ: INBUF:LocStamp_4_IBUF: PAD:LocStamp<4>: " ; inst "LocStamp<5>" "IBUF",placed TIOIB_X15Y17 P78 , cfg " DELAY_ADJ_ATTRBOX::FIXED GTSATTRBOX::#OFF IBUF_DELAY_VALUE::DLY0 ICEINV::#OFF ICLK1INV::#OFF ICLK2INV::#OFF IDDRIN_MUX::#OFF IFD_DELAY_VALUE::DLY0 IFF1::#OFF IFF1_INIT_ATTR::#OFF IFF1_SR_ATTR::#OFF IFF2::#OFF IFF2_INIT_ATTR::#OFF IFF2_SR_ATTR::#OFF IFFATTRBOX::#OFF IFFDMUX::#OFF IMUX::1 IOATTRBOX::LVCMOS33 IREV_USED::#OFF ISR_USED::#OFF MISRATTRBOX::#OFF MISR_CLK_SELECT::#OFF O1INV::#OFF O1_DDRMUX::#OFF O2INV::#OFF O2_DDRMUX::#OFF OCEINV::#OFF ODDROUT1_MUX::#OFF ODDROUT2_MUX::#OFF OFF1::#OFF OFF1_INIT_ATTR::#OFF OFF1_SR_ATTR::#OFF OFF2::#OFF OFF2_INIT_ATTR::#OFF OFF2_SR_ATTR::#OFF OFFATTRBOX::#OFF OMUX::#OFF OREV_USED::#OFF OSR_USED::#OFF OTCLK1INV::#OFF OTCLK2INV::#OFF PCICE_MUX::#OFF PCIRDY_MUX::#OFF PULL::PULLUP REVINV::#OFF SEL_MUX::0 SLEW::#OFF SRINV::#OFF T1INV::#OFF T2INV::#OFF TCEINV::#OFF TFF1::#OFF TFF1_INIT_ATTR::#OFF TFF1_SR_ATTR::#OFF TFF2::#OFF TFF2_INIT_ATTR::#OFF TFF2_SR_ATTR::#OFF TFFATTRBOX::#OFF TMUX::#OFF TREV_USED::#OFF TSMUX::#OFF TSR_USED::#OFF T_USED::#OFF DELAY_ADJ_BBOX:LocStamp<5>.DELAY_ADJ: INBUF:LocStamp_5_IBUF: PAD:LocStamp<5>: " ; inst "SPI_SCLK" "IOB",placed LIOIS_X0Y14 P5 , cfg " DELAY_ADJ_ATTRBOX::#OFF DRIVEATTRBOX::12 DRIVE_0MA::#OFF GTSATTRBOX::#OFF IBUF_DELAY_VALUE::#OFF ICEINV::#OFF ICLK1INV::#OFF ICLK2INV::#OFF IDDRIN_MUX::#OFF IFD_DELAY_VALUE::#OFF IFF1::#OFF IFF1_INIT_ATTR::#OFF IFF1_SR_ATTR::#OFF IFF2::#OFF IFF2_INIT_ATTR::#OFF IFF2_SR_ATTR::#OFF IFFATTRBOX::#OFF IFFDMUX::#OFF IMUX::#OFF IOATTRBOX::LVCMOS33 IREV_USED::#OFF ISR_USED::#OFF MISRATTRBOX::#OFF MISR_CLK_SELECT::#OFF O1INV::O1 O1_DDRMUX::#OFF O2INV::#OFF O2_DDRMUX::#OFF OCEINV::#OFF ODDROUT1_MUX::#OFF ODDROUT2_MUX::#OFF OFF1::#OFF OFF1_INIT_ATTR::#OFF OFF1_SR_ATTR::#OFF OFF2::#OFF OFF2_INIT_ATTR::#OFF OFF2_SR_ATTR::#OFF OFFATTRBOX::#OFF OMUX::O1 OREV_USED::#OFF OSR_USED::#OFF OTCLK1INV::#OFF OTCLK2INV::#OFF PCICE_MUX::#OFF PCIRDY_MUX::#OFF PULL::#OFF REVINV::#OFF SEL_MUX::#OFF SLEW::SLOW SRINV::#OFF SUSPEND::3STATE T1INV::#OFF T2INV::#OFF TCEINV::#OFF TFF1::#OFF TFF1_INIT_ATTR::#OFF TFF1_SR_ATTR::#OFF TFF2::#OFF TFF2_INIT_ATTR::#OFF TFF2_SR_ATTR::#OFF TFFATTRBOX::#OFF TMUX::#OFF TREV_USED::#OFF TSMUX::#OFF TSR_USED::#OFF T_USED::#OFF OUTBUF:SPI_SCLK_OBUF: PAD:SPI_SCLK: " ; inst "DAC_serData" "IOB",placed TIOIB_X9Y17 P85 , cfg " DELAY_ADJ_ATTRBOX::#OFF DRIVEATTRBOX::12 DRIVE_0MA::#OFF GTSATTRBOX::#OFF IBUF_DELAY_VALUE::#OFF ICEINV::#OFF ICLK1INV::#OFF ICLK2INV::#OFF IDDRIN_MUX::#OFF IFD_DELAY_VALUE::#OFF IFF1::#OFF IFF1_INIT_ATTR::#OFF IFF1_SR_ATTR::#OFF IFF2::#OFF IFF2_INIT_ATTR::#OFF IFF2_SR_ATTR::#OFF IFFATTRBOX::#OFF IFFDMUX::#OFF IMUX::#OFF IOATTRBOX::LVCMOS33 IREV_USED::#OFF ISR_USED::#OFF MISRATTRBOX::#OFF MISR_CLK_SELECT::#OFF O1INV::O1 O1_DDRMUX::#OFF O2INV::#OFF O2_DDRMUX::#OFF OCEINV::#OFF ODDROUT1_MUX::#OFF ODDROUT2_MUX::#OFF OFF1::#OFF OFF1_INIT_ATTR::#OFF OFF1_SR_ATTR::#OFF OFF2::#OFF OFF2_INIT_ATTR::#OFF OFF2_SR_ATTR::#OFF OFFATTRBOX::#OFF OMUX::O1 OREV_USED::#OFF OSR_USED::#OFF OTCLK1INV::#OFF OTCLK2INV::#OFF PCICE_MUX::#OFF PCIRDY_MUX::#OFF PULL::#OFF REVINV::#OFF SEL_MUX::#OFF SLEW::SLOW SRINV::#OFF SUSPEND::3STATE T1INV::#OFF T2INV::#OFF TCEINV::#OFF TFF1::#OFF TFF1_INIT_ATTR::#OFF TFF1_SR_ATTR::#OFF TFF2::#OFF TFF2_INIT_ATTR::#OFF TFF2_SR_ATTR::#OFF TFFATTRBOX::#OFF TMUX::#OFF TREV_USED::#OFF TSMUX::#OFF TSR_USED::#OFF T_USED::#OFF OUTBUF:DAC_serData_OBUF: PAD:DAC_serData: " ; inst "iRD" "IOB",placed TIOIB_X9Y17 P86 , cfg " DELAY_ADJ_ATTRBOX::#OFF DRIVEATTRBOX::12 DRIVE_0MA::#OFF GTSATTRBOX::#OFF IBUF_DELAY_VALUE::#OFF ICEINV::#OFF ICLK1INV::#OFF ICLK2INV::#OFF IDDRIN_MUX::#OFF IFD_DELAY_VALUE::#OFF IFF1::#OFF IFF1_INIT_ATTR::#OFF IFF1_SR_ATTR::#OFF IFF2::#OFF IFF2_INIT_ATTR::#OFF IFF2_SR_ATTR::#OFF IFFATTRBOX::#OFF IFFDMUX::#OFF IMUX::#OFF IOATTRBOX::LVCMOS33 IREV_USED::#OFF ISR_USED::#OFF MISRATTRBOX::#OFF MISR_CLK_SELECT::#OFF O1INV::O1 O1_DDRMUX::#OFF O2INV::#OFF O2_DDRMUX::#OFF OCEINV::#OFF ODDROUT1_MUX::#OFF ODDROUT2_MUX::#OFF OFF1::#OFF OFF1_INIT_ATTR::#OFF OFF1_SR_ATTR::#OFF OFF2::#OFF OFF2_INIT_ATTR::#OFF OFF2_SR_ATTR::#OFF OFFATTRBOX::#OFF OMUX::O1 OREV_USED::#OFF OSR_USED::#OFF OTCLK1INV::#OFF OTCLK2INV::#OFF PCICE_MUX::#OFF PCIRDY_MUX::#OFF PULL::#OFF REVINV::#OFF SEL_MUX::#OFF SLEW::SLOW SRINV::#OFF SUSPEND::3STATE T1INV::#OFF T2INV::#OFF TCEINV::#OFF TFF1::#OFF TFF1_INIT_ATTR::#OFF TFF1_SR_ATTR::#OFF TFF2::#OFF TFF2_INIT_ATTR::#OFF TFF2_SR_ATTR::#OFF TFFATTRBOX::#OFF TMUX::#OFF TREV_USED::#OFF TSMUX::#OFF TSR_USED::#OFF T_USED::#OFF OUTBUF:iRD_OBUF: PAD:iRD: " ; inst "Rst" "IBUF",placed BIOIB_X7Y0 P36 , cfg " DELAY_ADJ_ATTRBOX::FIXED GTSATTRBOX::#OFF IBUF_DELAY_VALUE::DLY0 ICEINV::#OFF ICLK1INV::#OFF ICLK2INV::#OFF IDDRIN_MUX::#OFF IFD_DELAY_VALUE::DLY0 IFF1::#OFF IFF1_INIT_ATTR::#OFF IFF1_SR_ATTR::#OFF IFF2::#OFF IFF2_INIT_ATTR::#OFF IFF2_SR_ATTR::#OFF IFFATTRBOX::#OFF IFFDMUX::#OFF IMUX::1 IOATTRBOX::LVCMOS33 IREV_USED::#OFF ISR_USED::#OFF MISRATTRBOX::#OFF MISR_CLK_SELECT::#OFF O1INV::#OFF O1_DDRMUX::#OFF O2INV::#OFF O2_DDRMUX::#OFF OCEINV::#OFF ODDROUT1_MUX::#OFF ODDROUT2_MUX::#OFF OFF1::#OFF OFF1_INIT_ATTR::#OFF OFF1_SR_ATTR::#OFF OFF2::#OFF OFF2_INIT_ATTR::#OFF OFF2_SR_ATTR::#OFF OFFATTRBOX::#OFF OMUX::#OFF OREV_USED::#OFF OSR_USED::#OFF OTCLK1INV::#OFF OTCLK2INV::#OFF PCICE_MUX::#OFF PCIRDY_MUX::#OFF PULL::#OFF REVINV::#OFF SEL_MUX::0 SLEW::#OFF SRINV::#OFF T1INV::#OFF T2INV::#OFF TCEINV::#OFF TFF1::#OFF TFF1_INIT_ATTR::#OFF TFF1_SR_ATTR::#OFF TFF2::#OFF TFF2_INIT_ATTR::#OFF TFF2_SR_ATTR::#OFF TFFATTRBOX::#OFF TMUX::#OFF TREV_USED::#OFF TSMUX::#OFF TSR_USED::#OFF T_USED::#OFF DELAY_ADJ_BBOX:Rst.DELAY_ADJ: INBUF:Rst_IBUF: PAD:Rst: " ; inst "SPI_T_CE" "IOB",placed TIOIB_X5Y17 P93 , cfg " DELAY_ADJ_ATTRBOX::#OFF DRIVEATTRBOX::12 DRIVE_0MA::#OFF GTSATTRBOX::#OFF IBUF_DELAY_VALUE::#OFF ICEINV::#OFF ICLK1INV::#OFF ICLK2INV::#OFF IDDRIN_MUX::#OFF IFD_DELAY_VALUE::#OFF IFF1::#OFF IFF1_INIT_ATTR::#OFF IFF1_SR_ATTR::#OFF IFF2::#OFF IFF2_INIT_ATTR::#OFF IFF2_SR_ATTR::#OFF IFFATTRBOX::#OFF IFFDMUX::#OFF IMUX::#OFF IOATTRBOX::LVCMOS33 IREV_USED::#OFF ISR_USED::#OFF MISRATTRBOX::#OFF MISR_CLK_SELECT::#OFF O1INV::O1 O1_DDRMUX::#OFF O2INV::#OFF O2_DDRMUX::#OFF OCEINV::#OFF ODDROUT1_MUX::#OFF ODDROUT2_MUX::#OFF OFF1::#OFF OFF1_INIT_ATTR::#OFF OFF1_SR_ATTR::#OFF OFF2::#OFF OFF2_INIT_ATTR::#OFF OFF2_SR_ATTR::#OFF OFFATTRBOX::#OFF OMUX::O1 OREV_USED::#OFF OSR_USED::#OFF OTCLK1INV::#OFF OTCLK2INV::#OFF PCICE_MUX::#OFF PCIRDY_MUX::#OFF PULL::#OFF REVINV::#OFF SEL_MUX::#OFF SLEW::SLOW SRINV::#OFF SUSPEND::3STATE T1INV::#OFF T2INV::#OFF TCEINV::#OFF TFF1::#OFF TFF1_INIT_ATTR::#OFF TFF1_SR_ATTR::#OFF TFF2::#OFF TFF2_INIT_ATTR::#OFF TFF2_SR_ATTR::#OFF TFFATTRBOX::#OFF TMUX::#OFF TREV_USED::#OFF TSMUX::#OFF TSR_USED::#OFF T_USED::#OFF OUTBUF:SPI_T_CE_OBUF: PAD:SPI_T_CE: " ; inst "iWR" "IOB",placed BIOIS_X8Y0 P41 , cfg " DELAY_ADJ_ATTRBOX::#OFF DRIVEATTRBOX::12 DRIVE_0MA::#OFF GTSATTRBOX::#OFF IBUF_DELAY_VALUE::#OFF ICEINV::#OFF ICLK1INV::#OFF ICLK2INV::#OFF IDDRIN_MUX::#OFF IFD_DELAY_VALUE::#OFF IFF1::#OFF IFF1_INIT_ATTR::#OFF IFF1_SR_ATTR::#OFF IFF2::#OFF IFF2_INIT_ATTR::#OFF IFF2_SR_ATTR::#OFF IFFATTRBOX::#OFF IFFDMUX::#OFF IMUX::#OFF IOATTRBOX::LVCMOS33 IREV_USED::#OFF ISR_USED::#OFF MISRATTRBOX::#OFF MISR_CLK_SELECT::#OFF O1INV::O1 O1_DDRMUX::#OFF O2INV::#OFF O2_DDRMUX::#OFF OCEINV::#OFF ODDROUT1_MUX::#OFF ODDROUT2_MUX::#OFF OFF1::#OFF OFF1_INIT_ATTR::#OFF OFF1_SR_ATTR::#OFF OFF2::#OFF OFF2_INIT_ATTR::#OFF OFF2_SR_ATTR::#OFF OFFATTRBOX::#OFF OMUX::O1 OREV_USED::#OFF OSR_USED::#OFF OTCLK1INV::#OFF OTCLK2INV::#OFF PCICE_MUX::#OFF PCIRDY_MUX::#OFF PULL::#OFF REVINV::#OFF SEL_MUX::#OFF SLEW::SLOW SRINV::#OFF SUSPEND::3STATE T1INV::#OFF T2INV::#OFF TCEINV::#OFF TFF1::#OFF TFF1_INIT_ATTR::#OFF TFF1_SR_ATTR::#OFF TFF2::#OFF TFF2_INIT_ATTR::#OFF TFF2_SR_ATTR::#OFF TFFATTRBOX::#OFF TMUX::#OFF TREV_USED::#OFF TSMUX::#OFF TSR_USED::#OFF T_USED::#OFF OUTBUF:iWR_OBUF: PAD:iWR: " ; inst "DAC_iRst" "IOB",placed TIOIB_X1Y17 P98 , cfg " DELAY_ADJ_ATTRBOX::#OFF DRIVEATTRBOX::12 DRIVE_0MA::#OFF GTSATTRBOX::#OFF IBUF_DELAY_VALUE::#OFF ICEINV::#OFF ICLK1INV::#OFF ICLK2INV::#OFF IDDRIN_MUX::#OFF IFD_DELAY_VALUE::#OFF IFF1::#OFF IFF1_INIT_ATTR::#OFF IFF1_SR_ATTR::#OFF IFF2::#OFF IFF2_INIT_ATTR::#OFF IFF2_SR_ATTR::#OFF IFFATTRBOX::#OFF IFFDMUX::#OFF IMUX::#OFF IOATTRBOX::LVCMOS33 IREV_USED::#OFF ISR_USED::#OFF MISRATTRBOX::#OFF MISR_CLK_SELECT::#OFF O1INV::O1 O1_DDRMUX::#OFF O2INV::#OFF O2_DDRMUX::#OFF OCEINV::#OFF ODDROUT1_MUX::#OFF ODDROUT2_MUX::#OFF OFF1::#OFF OFF1_INIT_ATTR::#OFF OFF1_SR_ATTR::#OFF OFF2::#OFF OFF2_INIT_ATTR::#OFF OFF2_SR_ATTR::#OFF OFFATTRBOX::#OFF OMUX::O1 OREV_USED::#OFF OSR_USED::#OFF OTCLK1INV::#OFF OTCLK2INV::#OFF PCICE_MUX::#OFF PCIRDY_MUX::#OFF PULL::#OFF REVINV::#OFF SEL_MUX::#OFF SLEW::SLOW SRINV::#OFF SUSPEND::3STATE T1INV::#OFF T2INV::#OFF TCEINV::#OFF TFF1::#OFF TFF1_INIT_ATTR::#OFF TFF1_SR_ATTR::#OFF TFF2::#OFF TFF2_INIT_ATTR::#OFF TFF2_SR_ATTR::#OFF TFFATTRBOX::#OFF TMUX::#OFF TREV_USED::#OFF TSMUX::#OFF TSR_USED::#OFF T_USED::#OFF OUTBUF:DAC_iRst_OBUF: PAD:DAC_iRst: " ; inst "AD<0>" "IOB",placed BIOIB_X13Y0 P49 , cfg " DELAY_ADJ_ATTRBOX::#OFF DRIVEATTRBOX::12 DRIVE_0MA::#OFF GTSATTRBOX::#OFF IBUF_DELAY_VALUE::#OFF ICEINV::#OFF ICLK1INV::#OFF ICLK2INV::#OFF IDDRIN_MUX::#OFF IFD_DELAY_VALUE::#OFF IFF1::#OFF IFF1_INIT_ATTR::#OFF IFF1_SR_ATTR::#OFF IFF2::#OFF IFF2_INIT_ATTR::#OFF IFF2_SR_ATTR::#OFF IFFATTRBOX::#OFF IFFDMUX::#OFF IMUX::#OFF IOATTRBOX::LVCMOS33 IREV_USED::#OFF ISR_USED::#OFF MISRATTRBOX::#OFF MISR_CLK_SELECT::#OFF O1INV::O1 O1_DDRMUX::1 O2INV::#OFF O2_DDRMUX::#OFF OCEINV::#OFF ODDROUT1_MUX::#OFF ODDROUT2_MUX::#OFF OFF1:u0/u2/Mtridata_AD_3:#LATCH OFF1_INIT_ATTR::INIT0 OFF1_SR_ATTR::#OFF OFF2::#OFF OFF2_INIT_ATTR::#OFF OFF2_SR_ATTR::#OFF OFFATTRBOX::#OFF OMUX::OFF1 OREV_USED::#OFF OSR_USED::#OFF OTCLK1INV::OTCLK1_B OTCLK2INV::#OFF PCICE_MUX::#OFF PCIRDY_MUX::#OFF PULL::#OFF REVINV::#OFF SEL_MUX::#OFF SLEW::SLOW SRINV::#OFF SUSPEND::3STATE T1INV::T1 T2INV::#OFF TCEINV::#OFF TFF1:u0/u2/Mtrien_AD:#LATCH TFF1_INIT_ATTR::INIT0 TFF1_SR_ATTR::#OFF TFF2::#OFF TFF2_INIT_ATTR::#OFF TFF2_SR_ATTR::#OFF TFFATTRBOX::#OFF TMUX::TFF1 TREV_USED::#OFF TSMUX::#OFF TSR_USED::#OFF T_USED::#OFF OUTBUF:AD_0_OBUFT: PAD:AD<0>: " ; inst "AD<1>" "IOB",placed BIOIB_X15Y0 P50 , cfg " DELAY_ADJ_ATTRBOX::#OFF DRIVEATTRBOX::12 DRIVE_0MA::#OFF GTSATTRBOX::#OFF IBUF_DELAY_VALUE::#OFF ICEINV::#OFF ICLK1INV::#OFF ICLK2INV::#OFF IDDRIN_MUX::#OFF IFD_DELAY_VALUE::#OFF IFF1::#OFF IFF1_INIT_ATTR::#OFF IFF1_SR_ATTR::#OFF IFF2::#OFF IFF2_INIT_ATTR::#OFF IFF2_SR_ATTR::#OFF IFFATTRBOX::#OFF IFFDMUX::#OFF IMUX::#OFF IOATTRBOX::LVCMOS33 IREV_USED::#OFF ISR_USED::#OFF MISRATTRBOX::#OFF MISR_CLK_SELECT::#OFF O1INV::O1 O1_DDRMUX::#OFF O2INV::#OFF O2_DDRMUX::#OFF OCEINV::#OFF ODDROUT1_MUX::#OFF ODDROUT2_MUX::#OFF OFF1::#OFF OFF1_INIT_ATTR::#OFF OFF1_SR_ATTR::#OFF OFF2::#OFF OFF2_INIT_ATTR::#OFF OFF2_SR_ATTR::#OFF OFFATTRBOX::#OFF OMUX::O1 OREV_USED::#OFF OSR_USED::#OFF OTCLK1INV::OTCLK1_B OTCLK2INV::#OFF PCICE_MUX::#OFF PCIRDY_MUX::#OFF PULL::#OFF REVINV::#OFF SEL_MUX::#OFF SLEW::SLOW SRINV::#OFF SUSPEND::3STATE T1INV::T1 T2INV::#OFF TCEINV::#OFF TFF1:u0/u2/Mtrien_AD_7:#LATCH TFF1_INIT_ATTR::INIT0 TFF1_SR_ATTR::#OFF TFF2::#OFF TFF2_INIT_ATTR::#OFF TFF2_SR_ATTR::#OFF TFFATTRBOX::#OFF TMUX::TFF1 TREV_USED::#OFF TSMUX::#OFF TSR_USED::#OFF T_USED::#OFF OUTBUF:AD_1_OBUFT: PAD:AD<1>: " ; inst "AD<2>" "IOB",placed BIOIS_X16Y0 P52 , cfg " DELAY_ADJ_ATTRBOX::#OFF DRIVEATTRBOX::12 DRIVE_0MA::#OFF GTSATTRBOX::#OFF IBUF_DELAY_VALUE::#OFF ICEINV::#OFF ICLK1INV::#OFF ICLK2INV::#OFF IDDRIN_MUX::#OFF IFD_DELAY_VALUE::#OFF IFF1::#OFF IFF1_INIT_ATTR::#OFF IFF1_SR_ATTR::#OFF IFF2::#OFF IFF2_INIT_ATTR::#OFF IFF2_SR_ATTR::#OFF IFFATTRBOX::#OFF IFFDMUX::#OFF IMUX::#OFF IOATTRBOX::LVCMOS33 IREV_USED::#OFF ISR_USED::#OFF MISRATTRBOX::#OFF MISR_CLK_SELECT::#OFF O1INV::O1 O1_DDRMUX::#OFF O2INV::#OFF O2_DDRMUX::#OFF OCEINV::#OFF ODDROUT1_MUX::#OFF ODDROUT2_MUX::#OFF OFF1::#OFF OFF1_INIT_ATTR::#OFF OFF1_SR_ATTR::#OFF OFF2::#OFF OFF2_INIT_ATTR::#OFF OFF2_SR_ATTR::#OFF OFFATTRBOX::#OFF OMUX::O1 OREV_USED::#OFF OSR_USED::#OFF OTCLK1INV::OTCLK1_B OTCLK2INV::#OFF PCICE_MUX::#OFF PCIRDY_MUX::#OFF PULL::#OFF REVINV::#OFF SEL_MUX::#OFF SLEW::SLOW SRINV::#OFF SUSPEND::3STATE T1INV::T1 T2INV::#OFF TCEINV::#OFF TFF1:u0/u2/Mtrien_AD_6:#LATCH TFF1_INIT_ATTR::INIT0 TFF1_SR_ATTR::#OFF TFF2::#OFF TFF2_INIT_ATTR::#OFF TFF2_SR_ATTR::#OFF TFFATTRBOX::#OFF TMUX::TFF1 TREV_USED::#OFF TSMUX::#OFF TSR_USED::#OFF T_USED::#OFF OUTBUF:AD_2_OBUFT: PAD:AD<2>: " ; inst "AD<3>" "IOB",placed RIOIS_X17Y3 P56 , cfg " DELAY_ADJ_ATTRBOX::#OFF DRIVEATTRBOX::12 DRIVE_0MA::#OFF GTSATTRBOX::#OFF IBUF_DELAY_VALUE::#OFF ICEINV::#OFF ICLK1INV::#OFF ICLK2INV::#OFF IDDRIN_MUX::#OFF IFD_DELAY_VALUE::#OFF IFF1::#OFF IFF1_INIT_ATTR::#OFF IFF1_SR_ATTR::#OFF IFF2::#OFF IFF2_INIT_ATTR::#OFF IFF2_SR_ATTR::#OFF IFFATTRBOX::#OFF IFFDMUX::#OFF IMUX::#OFF IOATTRBOX::LVCMOS33 IREV_USED::#OFF ISR_USED::#OFF MISRATTRBOX::#OFF MISR_CLK_SELECT::#OFF O1INV::O1 O1_DDRMUX::1 O2INV::#OFF O2_DDRMUX::#OFF OCEINV::#OFF ODDROUT1_MUX::#OFF ODDROUT2_MUX::#OFF OFF1:u0/u2/Mtridata_AD_3_1:#LATCH OFF1_INIT_ATTR::INIT0 OFF1_SR_ATTR::#OFF OFF2::#OFF OFF2_INIT_ATTR::#OFF OFF2_SR_ATTR::#OFF OFFATTRBOX::#OFF OMUX::OFF1 OREV_USED::#OFF OSR_USED::#OFF OTCLK1INV::OTCLK1_B OTCLK2INV::#OFF PCICE_MUX::#OFF PCIRDY_MUX::#OFF PULL::#OFF REVINV::#OFF SEL_MUX::#OFF SLEW::SLOW SRINV::#OFF SUSPEND::3STATE T1INV::T1 T2INV::#OFF TCEINV::#OFF TFF1:u0/u2/Mtrien_AD_5:#LATCH TFF1_INIT_ATTR::INIT0 TFF1_SR_ATTR::#OFF TFF2::#OFF TFF2_INIT_ATTR::#OFF TFF2_SR_ATTR::#OFF TFFATTRBOX::#OFF TMUX::TFF1 TREV_USED::#OFF TSMUX::#OFF TSR_USED::#OFF T_USED::#OFF OUTBUF:AD_3_OBUFT: PAD:AD<3>: " ; inst "AD<4>" "IOB",placed RIOIS_X17Y3 P57 , cfg " DELAY_ADJ_ATTRBOX::#OFF DRIVEATTRBOX::12 DRIVE_0MA::#OFF GTSATTRBOX::#OFF IBUF_DELAY_VALUE::#OFF ICEINV::#OFF ICLK1INV::#OFF ICLK2INV::#OFF IDDRIN_MUX::#OFF IFD_DELAY_VALUE::#OFF IFF1::#OFF IFF1_INIT_ATTR::#OFF IFF1_SR_ATTR::#OFF IFF2::#OFF IFF2_INIT_ATTR::#OFF IFF2_SR_ATTR::#OFF IFFATTRBOX::#OFF IFFDMUX::#OFF IMUX::#OFF IOATTRBOX::LVCMOS33 IREV_USED::#OFF ISR_USED::#OFF MISRATTRBOX::#OFF MISR_CLK_SELECT::#OFF O1INV::O1 O1_DDRMUX::#OFF O2INV::#OFF O2_DDRMUX::#OFF OCEINV::#OFF ODDROUT1_MUX::#OFF ODDROUT2_MUX::#OFF OFF1::#OFF OFF1_INIT_ATTR::#OFF OFF1_SR_ATTR::#OFF OFF2::#OFF OFF2_INIT_ATTR::#OFF OFF2_SR_ATTR::#OFF OFFATTRBOX::#OFF OMUX::O1 OREV_USED::#OFF OSR_USED::#OFF OTCLK1INV::OTCLK1_B OTCLK2INV::#OFF PCICE_MUX::#OFF PCIRDY_MUX::#OFF PULL::#OFF REVINV::#OFF SEL_MUX::#OFF SLEW::SLOW SRINV::#OFF SUSPEND::3STATE T1INV::T1 T2INV::#OFF TCEINV::#OFF TFF1:u0/u2/Mtrien_AD_4:#LATCH TFF1_INIT_ATTR::INIT0 TFF1_SR_ATTR::#OFF TFF2::#OFF TFF2_INIT_ATTR::#OFF TFF2_SR_ATTR::#OFF TFFATTRBOX::#OFF TMUX::TFF1 TREV_USED::#OFF TSMUX::#OFF TSR_USED::#OFF T_USED::#OFF OUTBUF:AD_4_OBUFT: PAD:AD<4>: " ; inst "AD<5>" "IOB",placed RIOIS_PCI_X17Y6 P59 , cfg " DELAY_ADJ_ATTRBOX::#OFF DRIVEATTRBOX::12 DRIVE_0MA::#OFF GTSATTRBOX::#OFF IBUF_DELAY_VALUE::#OFF ICEINV::#OFF ICLK1INV::#OFF ICLK2INV::#OFF IDDRIN_MUX::#OFF IFD_DELAY_VALUE::#OFF IFF1::#OFF IFF1_INIT_ATTR::#OFF IFF1_SR_ATTR::#OFF IFF2::#OFF IFF2_INIT_ATTR::#OFF IFF2_SR_ATTR::#OFF IFFATTRBOX::#OFF IFFDMUX::#OFF IMUX::#OFF IOATTRBOX::LVCMOS33 IREV_USED::#OFF ISR_USED::#OFF MISRATTRBOX::#OFF MISR_CLK_SELECT::#OFF O1INV::O1 O1_DDRMUX::#OFF O2INV::#OFF O2_DDRMUX::#OFF OCEINV::#OFF ODDROUT1_MUX::#OFF ODDROUT2_MUX::#OFF OFF1::#OFF OFF1_INIT_ATTR::#OFF OFF1_SR_ATTR::#OFF OFF2::#OFF OFF2_INIT_ATTR::#OFF OFF2_SR_ATTR::#OFF OFFATTRBOX::#OFF OMUX::O1 OREV_USED::#OFF OSR_USED::#OFF OTCLK1INV::OTCLK1_B OTCLK2INV::#OFF PCICE_MUX::#OFF PCIRDY_MUX::#OFF PULL::#OFF REVINV::#OFF SEL_MUX::#OFF SLEW::SLOW SRINV::#OFF SUSPEND::3STATE T1INV::T1 T2INV::#OFF TCEINV::#OFF TFF1:u0/u2/Mtrien_AD_3:#LATCH TFF1_INIT_ATTR::INIT0 TFF1_SR_ATTR::#OFF TFF2::#OFF TFF2_INIT_ATTR::#OFF TFF2_SR_ATTR::#OFF TFFATTRBOX::#OFF TMUX::TFF1 TREV_USED::#OFF TSMUX::#OFF TSR_USED::#OFF T_USED::#OFF OUTBUF:AD_5_OBUFT: PAD:AD<5>: " ; inst "AD<6>" "IOB",placed RIOIS_PCI_X17Y6 P60 , cfg " DELAY_ADJ_ATTRBOX::#OFF DRIVEATTRBOX::12 DRIVE_0MA::#OFF GTSATTRBOX::#OFF IBUF_DELAY_VALUE::#OFF ICEINV::#OFF ICLK1INV::#OFF ICLK2INV::#OFF IDDRIN_MUX::#OFF IFD_DELAY_VALUE::#OFF IFF1::#OFF IFF1_INIT_ATTR::#OFF IFF1_SR_ATTR::#OFF IFF2::#OFF IFF2_INIT_ATTR::#OFF IFF2_SR_ATTR::#OFF IFFATTRBOX::#OFF IFFDMUX::#OFF IMUX::#OFF IOATTRBOX::LVCMOS33 IREV_USED::#OFF ISR_USED::#OFF MISRATTRBOX::#OFF MISR_CLK_SELECT::#OFF O1INV::O1 O1_DDRMUX::#OFF O2INV::#OFF O2_DDRMUX::#OFF OCEINV::#OFF ODDROUT1_MUX::#OFF ODDROUT2_MUX::#OFF OFF1::#OFF OFF1_INIT_ATTR::#OFF OFF1_SR_ATTR::#OFF OFF2::#OFF OFF2_INIT_ATTR::#OFF OFF2_SR_ATTR::#OFF OFFATTRBOX::#OFF OMUX::O1 OREV_USED::#OFF OSR_USED::#OFF OTCLK1INV::OTCLK1_B OTCLK2INV::#OFF PCICE_MUX::#OFF PCIRDY_MUX::#OFF PULL::#OFF REVINV::#OFF SEL_MUX::#OFF SLEW::SLOW SRINV::#OFF SUSPEND::3STATE T1INV::T1 T2INV::#OFF TCEINV::#OFF TFF1:u0/u2/Mtrien_AD_2:#LATCH TFF1_INIT_ATTR::INIT0 TFF1_SR_ATTR::#OFF TFF2::#OFF TFF2_INIT_ATTR::#OFF TFF2_SR_ATTR::#OFF TFFATTRBOX::#OFF TMUX::TFF1 TREV_USED::#OFF TSMUX::#OFF TSR_USED::#OFF T_USED::#OFF OUTBUF:AD_6_OBUFT: PAD:AD<6>: " ; inst "AD<7>" "IOB",placed RIOIS_PCI_X17Y7 P61 , cfg " DELAY_ADJ_ATTRBOX::#OFF DRIVEATTRBOX::12 DRIVE_0MA::#OFF GTSATTRBOX::#OFF IBUF_DELAY_VALUE::#OFF ICEINV::#OFF ICLK1INV::#OFF ICLK2INV::#OFF IDDRIN_MUX::#OFF IFD_DELAY_VALUE::#OFF IFF1::#OFF IFF1_INIT_ATTR::#OFF IFF1_SR_ATTR::#OFF IFF2::#OFF IFF2_INIT_ATTR::#OFF IFF2_SR_ATTR::#OFF IFFATTRBOX::#OFF IFFDMUX::#OFF IMUX::#OFF IOATTRBOX::LVCMOS33 IREV_USED::#OFF ISR_USED::#OFF MISRATTRBOX::#OFF MISR_CLK_SELECT::#OFF O1INV::O1 O1_DDRMUX::#OFF O2INV::#OFF O2_DDRMUX::#OFF OCEINV::#OFF ODDROUT1_MUX::#OFF ODDROUT2_MUX::#OFF OFF1::#OFF OFF1_INIT_ATTR::#OFF OFF1_SR_ATTR::#OFF OFF2::#OFF OFF2_INIT_ATTR::#OFF OFF2_SR_ATTR::#OFF OFFATTRBOX::#OFF OMUX::O1 OREV_USED::#OFF OSR_USED::#OFF OTCLK1INV::OTCLK1_B OTCLK2INV::#OFF PCICE_MUX::#OFF PCIRDY_MUX::#OFF PULL::#OFF REVINV::#OFF SEL_MUX::#OFF SLEW::SLOW SRINV::#OFF SUSPEND::3STATE T1INV::T1 T2INV::#OFF TCEINV::#OFF TFF1:u0/u2/Mtrien_AD_1:#LATCH TFF1_INIT_ATTR::INIT0 TFF1_SR_ATTR::#OFF TFF2::#OFF TFF2_INIT_ATTR::#OFF TFF2_SR_ATTR::#OFF TFFATTRBOX::#OFF TMUX::TFF1 TREV_USED::#OFF TSMUX::#OFF TSR_USED::#OFF T_USED::#OFF OUTBUF:AD_7_OBUFT: PAD:AD<7>: " ; inst "fClk_BUFGP/BUFG" "BUFGMUX",placed CLKB_X8Y0 BUFGMUX_X1Y1 , cfg " DISABLE_ATTR::LOW I0_USED::0 I1_USED::#OFF SINV::S_B GCLKMUX:fClk_BUFGP/BUFG.GCLKMUX: GCLK_BUFFER:fClk_BUFGP/BUFG: " ; inst "Rst_IBUF_BUFG" "BUFGMUX",placed CLKB_X8Y0 BUFGMUX_X2Y1 , cfg " DISABLE_ATTR::LOW I0_USED::0 I1_USED::#OFF SINV::S_B GCLKMUX:Rst_IBUF_BUFG.GCLKMUX: GCLK_BUFFER:Rst_IBUF_BUFG: " ; inst "u0/u2/TickCount_1_BUFG" "BUFGMUX",placed CLKT_X8Y17 BUFGMUX_X2Y10 , cfg " DISABLE_ATTR::LOW I0_USED::0 I1_USED::#OFF SINV::S_B GCLKMUX:u0/u2/TickCount_1_BUFG.GCLKMUX: GCLK_BUFFER:u0/u2/TickCount_1_BUFG: " ; inst "u8/u3/u1/En_BUFG" "BUFGMUX",placed CLKT_X8Y17 BUFGMUX_X2Y11 , cfg " DISABLE_ATTR::LOW I0_USED::0 I1_USED::#OFF SINV::S_B GCLKMUX:u8/u3/u1/En_BUFG.GCLKMUX: GCLK_BUFFER:u8/u3/u1/En_BUFG: " ; inst "u7/u8/Wr_int_and0000" "SLICEL",placed CLB_X4Y13 SLICE_X7Y24 , cfg " BXINV::BX BYINV::#OFF CEINV::#OFF CLKINV::#OFF COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DXMUX::#OFF DYMUX::#OFF F:u0/u2/Mtridata_AD<1>_113.SLICEL_F:#LUT:D=0 F5USED::#OFF FFX::#OFF FFX_INIT_ATTR::#OFF FFX_SR_ATTR::#OFF FFY::#OFF FFY_INIT_ATTR::#OFF FFY_SR_ATTR::#OFF FXMUX::F5 FXUSED::#OFF G:u7/u8/Wr_int_and000011:#LUT:D=((~A2*(A4*A3))+A1) GYMUX::#OFF REVUSED::#OFF SRINV::#OFF SYNC_ATTR::#OFF XBUSED::#OFF XUSED::0 YBUSED::#OFF YUSED::#OFF F5MUX:u7/u8/Wr_int_and00001_f5: " ; inst "u1/Go" "SLICEL",placed CLB_X13Y11 SLICE_X16Y20 , cfg " BXINV::BX BYINV::#OFF CEINV::#OFF CLKINV::#OFF COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DXMUX::#OFF DYMUX::#OFF F:ADCregs_A<0>_70.SLICEL_F:#LUT:D=1 F5USED::#OFF FFX::#OFF FFX_INIT_ATTR::#OFF FFX_SR_ATTR::#OFF FFY::#OFF FFY_INIT_ATTR::#OFF FFY_SR_ATTR::#OFF FXMUX::F5 FXUSED::#OFF G:u1/Go1:#LUT:D=(~A3*(~A2*(~A4*~A1))) GYMUX::#OFF REVUSED::#OFF SRINV::#OFF SYNC_ATTR::#OFF XBUSED::#OFF XUSED::0 YBUSED::#OFF YUSED::#OFF F5MUX:u1/Go_f5: " ; inst "u2/u3/u1/u1/Q_int" "SLICEL",placed CLB_X7Y10 SLICE_X12Y19 , cfg " BXINV::BX BYINV::#OFF CEINV::#OFF CLKINV::CLK_B COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DXMUX::1 DYMUX::#OFF F:u2/Go_Byte11:#LUT:D=(~A3+~A1) F5USED::#OFF FFX:u2/u3/u1/u1/Q_int:#FF FFX_INIT_ATTR::INIT0 FFX_SR_ATTR::SRLOW FFY::#OFF FFY_INIT_ATTR::#OFF FFY_SR_ATTR::#OFF FXMUX::F5 FXUSED::#OFF G:u2/Go_Byte12:#LUT:D=(~A4*(~A2*(~A3+~A1))) GYMUX::#OFF REVUSED::#OFF SRINV::#OFF SYNC_ATTR::ASYNC XBUSED::#OFF XUSED::#OFF YBUSED::#OFF YUSED::#OFF F5MUX:u2/Go_Byte1_f5: " ; inst "u0/u2/ALE_not0001" "SLICEL",placed CLB_X8Y1 SLICE_X14Y0 , cfg " BXINV::BX BYINV::#OFF CEINV::#OFF CLKINV::#OFF COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DXMUX::#OFF DYMUX::#OFF F:Rst_IBUF1_rt:#LUT:D=A2 _BEL_PROP::F:PK_PACKTHRU: F5USED::#OFF FFX::#OFF FFX_INIT_ATTR::#OFF FFX_SR_ATTR::#OFF FFY::#OFF FFY_INIT_ATTR::#OFF FFY_SR_ATTR::#OFF FXMUX::F5 FXUSED::#OFF G:u0/u2/ALE_not000111:#LUT:D=((~A4*(A3@~A2))+A1) GYMUX::#OFF REVUSED::#OFF SRINV::#OFF SYNC_ATTR::#OFF XBUSED::#OFF XUSED::0 YBUSED::#OFF YUSED::#OFF F5MUX:u0/u2/ALE_not00011_f5: " ; inst "u0/u2/RWflag" "SLICEL",placed CLB_X8Y1 SLICE_X15Y0 , cfg " BXINV::BX BYINV::#OFF CEINV::#OFF CLKINV::CLK COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DXMUX::1 DYMUX::#OFF F:u0/u2/RWflag_mux0001_G:#LUT:D=(A3+(~A1+(~A2+A4))) F5USED::#OFF FFX:u0/u2/RWflag:#LATCH FFX_INIT_ATTR::INIT0 FFX_SR_ATTR::SRLOW FFY::#OFF FFY_INIT_ATTR::#OFF FFY_SR_ATTR::#OFF FXMUX::F5 FXUSED::#OFF G:u0/u2/RWflag_mux0001_F:#LUT:D=(~A2*((~A4*(~A1*~A3))+(A4*(A1*A3)))) GYMUX::#OFF REVUSED::#OFF SRINV::#OFF SYNC_ATTR::ASYNC XBUSED::#OFF XUSED::#OFF YBUSED::#OFF YUSED::#OFF F5MUX:u0/u2/RWflag_mux0001: " ; inst "u8/Addr<4>" "SLICEL",placed CLB_X4Y10 SLICE_X6Y19 , cfg " BXINV::BX BYINV::#OFF CEINV::CE CLKINV::CLK COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DXMUX::1 DYMUX::#OFF F:u8/Result<4>1:#LUT:D=(~A1+(~A4+(~A2+~A3))) F5USED::#OFF FFX:u8/Addr_4:#FF FFX_INIT_ATTR::INIT1 FFX_SR_ATTR::SRHIGH FFY::#OFF FFY_INIT_ATTR::#OFF FFY_SR_ATTR::#OFF FXMUX::F5 FXUSED::#OFF G:u8/Result<4>2:#LUT:D=(A3*(A1*(A4*A2))) GYMUX::#OFF REVUSED::#OFF SRINV::SR SYNC_ATTR::ASYNC XBUSED::#OFF XUSED::#OFF YBUSED::#OFF YUSED::#OFF F5MUX:u8/Result<4>_f5: " ; inst "u0/u2/ALE_mux0001" "SLICEL",placed CLB_X13Y1 SLICE_X17Y0 , cfg " BXINV::BX BYINV::#OFF CEINV::#OFF CLKINV::#OFF COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DXMUX::#OFF DYMUX::#OFF F:u0/u2/Mtridata_AD<1>_112.SLICEL_F:#LUT:D=0 F5USED::#OFF FFX::#OFF FFX_INIT_ATTR::#OFF FFX_SR_ATTR::#OFF FFY::#OFF FFY_INIT_ATTR::#OFF FFY_SR_ATTR::#OFF FXMUX::F5 FXUSED::#OFF G:u0/u2/ALE_mux00011:#LUT:D=(~A1*(~A4*(~A3*~A2))) GYMUX::#OFF REVUSED::#OFF SRINV::#OFF SYNC_ATTR::#OFF XBUSED::#OFF XUSED::0 YBUSED::#OFF YUSED::#OFF F5MUX:u0/u2/ALE_mux0001_f5: " ; inst "u5/Go_Cyc14Step_inv" "SLICEL",placed CLB_X16Y14 SLICE_X23Y26 , cfg " BXINV::BX BYINV::#OFF CEINV::#OFF CLKINV::#OFF COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DXMUX::#OFF DYMUX::#OFF F:u5/Go_Cyc14Step_inv331:#LUT:D=(A3*(A4*(A1*A2))) F5USED::#OFF FFX::#OFF FFX_INIT_ATTR::#OFF FFX_SR_ATTR::#OFF FFY::#OFF FFY_INIT_ATTR::#OFF FFY_SR_ATTR::#OFF FXMUX::F5 FXUSED::#OFF G:ADCregs_A<0>_68.SLICEL_G:#LUT:D=1 GYMUX::#OFF REVUSED::#OFF SRINV::#OFF SYNC_ATTR::#OFF XBUSED::#OFF XUSED::0 YBUSED::#OFF YUSED::#OFF F5MUX:u5/Go_Cyc14Step_inv33_f5: " ; inst "u0/u2/Mtrien_AD_mux0000" "SLICEL",placed CLB_X15Y2 SLICE_X21Y2 , cfg " BXINV::BX BYINV::#OFF CEINV::#OFF CLKINV::#OFF COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DXMUX::#OFF DYMUX::#OFF F:u0/u2/Mtrien_AD_mux00001:#LUT:D=(A1+(A3*(A2*A4))) F5USED::#OFF FFX::#OFF FFX_INIT_ATTR::#OFF FFX_SR_ATTR::#OFF FFY::#OFF FFY_INIT_ATTR::#OFF FFY_SR_ATTR::#OFF FXMUX::F5 FXUSED::#OFF G:u0/u2/Mtrien_AD_mux00002:#LUT:D=((~A3*(A2*A4))+A1) GYMUX::#OFF REVUSED::#OFF SRINV::#OFF SYNC_ATTR::#OFF XBUSED::#OFF XUSED::0 YBUSED::#OFF YUSED::#OFF F5MUX:u0/u2/Mtrien_AD_mux0000_f5: " ; inst "u9/shift" "SLICEL",placed CLB_X1Y8 SLICE_X1Y15 , cfg " BXINV::BX BYINV::#OFF CEINV::#OFF CLKINV::#OFF COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DXMUX::#OFF DYMUX::#OFF F:ADCregs_A<0>_69.SLICEL_F:#LUT:D=1 F5USED::#OFF FFX::#OFF FFX_INIT_ATTR::#OFF FFX_SR_ATTR::#OFF FFY::#OFF FFY_INIT_ATTR::#OFF FFY_SR_ATTR::#OFF FXMUX::F5 FXUSED::#OFF G:u9/u1/Go1:#LUT:D=(A3+(A1+(A2+A4))) GYMUX::#OFF REVUSED::#OFF SRINV::#OFF SYNC_ATTR::#OFF XBUSED::#OFF XUSED::0 YBUSED::#OFF YUSED::#OFF F5MUX:u9/u1/Go_f5: " ; inst "u0/u2/Mtridata_AD_mux0000<0>" "SLICEL",placed CLB_X14Y1 SLICE_X19Y0 , cfg " BXINV::BX BYINV::#OFF CEINV::#OFF CLKINV::#OFF COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DXMUX::#OFF DYMUX::#OFF F:u0/u2/Mtridata_AD<1>_111.SLICEL_F:#LUT:D=0 F5USED::#OFF FFX::#OFF FFX_INIT_ATTR::#OFF FFX_SR_ATTR::#OFF FFY::#OFF FFY_INIT_ATTR::#OFF FFY_SR_ATTR::#OFF FXMUX::F5 FXUSED::#OFF G:u0/u2/Mtridata_AD_mux0000<0>1:#LUT:D=(~A1*(~A2*(~A4*A3))) GYMUX::#OFF REVUSED::#OFF SRINV::#OFF SYNC_ATTR::#OFF XBUSED::#OFF XUSED::0 YBUSED::#OFF YUSED::#OFF F5MUX:u0/u2/Mtridata_AD_mux0000<0>_f5: " ; inst "u7/u1/count<4>" "SLICEL",placed CLB_X2Y16 SLICE_X2Y30 , cfg " BXINV::BX BYINV::#OFF CEINV::CE CLKINV::CLK COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DXMUX::1 DYMUX::#OFF F:u7/u1/Mcount_count_xor<4>11:#LUT:D=(~A2+(~A1+(~A3+~A4))) F5USED::#OFF FFX:u7/u1/count_4:#FF FFX_INIT_ATTR::INIT0 FFX_SR_ATTR::SRLOW FFY::#OFF FFY_INIT_ATTR::#OFF FFY_SR_ATTR::#OFF FXMUX::F5 FXUSED::#OFF G:u7/u1/Mcount_count_xor<4>12:#LUT:D=(A2*((~A1*(~A4*~A3))+(A1*(A4*A3)))) GYMUX::#OFF REVUSED::#OFF SRINV::SR SYNC_ATTR::ASYNC XBUSED::#OFF XUSED::#OFF YBUSED::#OFF YUSED::#OFF F5MUX:u7/u1/Mcount_count_xor<4>1_f5: " ; inst "u0/u2/Mtrien_AD_not0001" "SLICEL",placed CLB_X15Y2 SLICE_X20Y2 , cfg " BXINV::BX BYINV::#OFF CEINV::#OFF CLKINV::#OFF COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DXMUX::#OFF DYMUX::#OFF F:u0/u2/Mtrien_AD_not00011:#LUT:D=(((~A2*(~A1*~A3))+(A2*(A1*A3)))+A4) F5USED::#OFF FFX::#OFF FFX_INIT_ATTR::#OFF FFX_SR_ATTR::#OFF FFY::#OFF FFY_INIT_ATTR::#OFF FFY_SR_ATTR::#OFF FXMUX::F5 FXUSED::#OFF G:u0/u2/Mtrien_AD_not00012:#LUT:D=((~A2*(~A3+(A4+A1)))+(A2*A4)) GYMUX::#OFF REVUSED::#OFF SRINV::#OFF SYNC_ATTR::#OFF XBUSED::#OFF XUSED::0 YBUSED::#OFF YUSED::#OFF F5MUX:u0/u2/Mtrien_AD_not0001_f5: " ; inst "u1/p6b/Q_int" "SLICEL",placed CLB_X16Y8 SLICE_X22Y15 , cfg " BXINV::#OFF BYINV::#OFF CEINV::#OFF CLKINV::CLK_B COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DXMUX::1 DYMUX::#OFF F:u1/Done_Wait2361:#LUT:D=(A3*(A1*A4)) F5USED::#OFF FFX:u1/p6b/Q_int:#FF FFX_INIT_ATTR::INIT1 FFX_SR_ATTR::SRHIGH FFY::#OFF FFY_INIT_ATTR::#OFF FFY_SR_ATTR::#OFF FXMUX::F FXUSED::#OFF G:u1/Done_Wait25:#LUT:D=(A3*(A1*(A4*A2))) GYMUX::G REVUSED::#OFF SRINV::SR SYNC_ATTR::SYNC XBUSED::#OFF XUSED::#OFF YBUSED::#OFF YUSED::0 " ; inst "DAC_iRst_OBUF" "SLICEL",placed CLB_X8Y10 SLICE_X14Y18 , cfg " BXINV::#OFF BYINV::#OFF CEINV::#OFF CLKINV::#OFF COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DXMUX::#OFF DYMUX::#OFF F:DAC_iRst1:#LUT:D=(A3+(~A2+(~A1+A4))) F5USED::#OFF FFX::#OFF FFX_INIT_ATTR::#OFF FFX_SR_ATTR::#OFF FFY::#OFF FFY_INIT_ATTR::#OFF FFY_SR_ATTR::#OFF FXMUX::F FXUSED::#OFF G:u2/En_or00001:#LUT:D=(~A1+(A2+A4)) GYMUX::G REVUSED::#OFF SRINV::#OFF SYNC_ATTR::#OFF XBUSED::#OFF XUSED::0 YBUSED::#OFF YUSED::0 " ; inst "state_D<0>LogicTrst82" "SLICEL",placed CLB_X8Y12 SLICE_X14Y22 , cfg " BXINV::#OFF BYINV::#OFF CEINV::#OFF CLKINV::#OFF COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DXMUX::#OFF DYMUX::#OFF F:state_D<0>LogicTrst82:#LUT:D=((~A1*(~A4+A2))+(A1*(A3+(~A4+A2)))) F5USED::#OFF FFX::#OFF FFX_INIT_ATTR::#OFF FFX_SR_ATTR::#OFF FFY::#OFF FFY_INIT_ATTR::#OFF FFY_SR_ATTR::#OFF FXMUX::F FXUSED::#OFF G:u6/stateEn_and0000_inv:#LUT:D=(A3+(~A4+(~A1+A2))) GYMUX::G REVUSED::#OFF SRINV::#OFF SYNC_ATTR::#OFF XBUSED::#OFF XUSED::0 YBUSED::#OFF YUSED::0 " ; inst "u5/count<3>" "SLICEL",placed CLB_X15Y14 SLICE_X20Y26 , cfg " BXINV::#OFF BYINV::#OFF CEINV::#OFF CLKINV::CLK COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DXMUX::1 DYMUX::1 F:u5/Mcount_count_xor<3>11:#LUT:D=((~A2*(A4*(A1*A3)))+(A2*(~A4+(~A1+~A3)))) F5USED::#OFF FFX:u5/count_3:#FF FFX_INIT_ATTR::INIT0 FFX_SR_ATTR::SRLOW FFY:u5/count_2:#FF FFY_INIT_ATTR::INIT0 FFY_SR_ATTR::SRLOW FXMUX::F FXUSED::#OFF G:u5/Mcount_count_xor<2>11:#LUT:D=((~A3*(A1*A4))+(A3*(~A1+~A4))) GYMUX::G REVUSED::#OFF SRINV::SR SYNC_ATTR::ASYNC XBUSED::#OFF XUSED::#OFF YBUSED::#OFF YUSED::#OFF " ; inst "u0/u2/TickCount_11" "SLICEL",placed CLB_X7Y4 SLICE_X13Y7 , cfg " BXINV::#OFF BYINV::#OFF CEINV::#OFF CLKINV::CLK COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DXMUX::#OFF DYMUX::1 F:u1/g3/u2/En_and00001:#LUT:D=(A4*A2) F5USED::#OFF FFX::#OFF FFX_INIT_ATTR::#OFF FFX_SR_ATTR::#OFF FFY:u0/u2/TickCount_1:#FF FFY_INIT_ATTR::INIT0 FFY_SR_ATTR::SRLOW FXMUX::F FXUSED::#OFF G:u0/u2/Mcount_TickCount_xor<1>11:#LUT:D=(A4@A2) GYMUX::G REVUSED::#OFF SRINV::SR SYNC_ATTR::ASYNC XBUSED::#OFF XUSED::0 YBUSED::#OFF YUSED::#OFF " ; inst "u0/u2/u2/count<3>" "SLICEL",placed CLB_X13Y1 SLICE_X16Y1 , cfg " BXINV::#OFF BYINV::#OFF CEINV::CE CLKINV::CLK COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DXMUX::1 DYMUX::1 F:u0/u2/u2/Mcount_count_xor<3>11:#LUT:D=((~A3*(A2*(A4*A1)))+(A3*(~A2+(~A4+~A1)))) F5USED::#OFF FFX:u0/u2/u2/count_3:#FF FFX_INIT_ATTR::INIT0 FFX_SR_ATTR::SRLOW FFY:u0/u2/u2/count_2:#FF FFY_INIT_ATTR::INIT0 FFY_SR_ATTR::SRLOW FXMUX::F FXUSED::#OFF G:u0/u2/u2/Mcount_count_xor<2>11:#LUT:D=((~A1*(A2*A4))+(A1*(~A2+~A4))) GYMUX::G REVUSED::#OFF SRINV::#OFF SYNC_ATTR::SYNC XBUSED::#OFF XUSED::#OFF YBUSED::#OFF YUSED::#OFF " ; inst "u4/u1/Qa" "SLICEL",placed CLB_X8Y12 SLICE_X15Y23 , cfg " BXINV::#OFF BYINV::#OFF CEINV::#OFF CLKINV::CLK_B COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DXMUX::1 DYMUX::1 F:u4/S_En1:#LUT:D=(~A3*(~A4*A1)) F5USED::#OFF FFX:u4/u1/Qa:#FF FFX_INIT_ATTR::INIT0 FFX_SR_ATTR::SRLOW FFY:u2/u1/Qa:#FF FFY_INIT_ATTR::INIT0 FFY_SR_ATTR::SRLOW FXMUX::F FXUSED::#OFF G:u2/En1:#LUT:D=(~A3*(~A4*A1)) GYMUX::G REVUSED::#OFF SRINV::#OFF SYNC_ATTR::ASYNC XBUSED::#OFF XUSED::#OFF YBUSED::#OFF YUSED::0 " ; inst "u8/lenregL/Data<0>" "SLICEL",placed CLB_X5Y9 SLICE_X8Y16 , cfg " BXINV::#OFF BYINV::#OFF CEINV::CE CLKINV::CLK_B COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DXMUX::#OFF DYMUX::1 F:u8/MaskStage_and00001:#LUT:D=(~A2*A4) F5USED::#OFF FFX::#OFF FFX_INIT_ATTR::#OFF FFX_SR_ATTR::#OFF FFY:u8/lenregL/Data_0:#FF FFY_INIT_ATTR::INIT0 FFY_SR_ATTR::SRLOW FXMUX::F FXUSED::#OFF G:u8/Data<0>1:#LUT:D=(~A4*(~A2*~A3)) GYMUX::G REVUSED::#OFF SRINV::SR SYNC_ATTR::ASYNC XBUSED::#OFF XUSED::0 YBUSED::#OFF YUSED::0 " ; inst "u1/p5/count<11>" "SLICEL",placed CLB_X16Y11 SLICE_X22Y20 , cfg " BXINV::#OFF BYINV::#OFF CEINV::#OFF CLKINV::CLK COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DXMUX::1 DYMUX::1 F:u1/p5/Mcount_count_eqn_111:#LUT:D=(((~A4*(A3+A1))+A4)*A2) F5USED::#OFF FFX:u1/p5/count_11:#FF FFX_INIT_ATTR::INIT0 FFX_SR_ATTR::SRLOW FFY:u1/p5/count_10:#FF FFY_INIT_ATTR::INIT0 FFY_SR_ATTR::SRLOW FXMUX::F FXUSED::#OFF G:u1/p5/Mcount_count_eqn_101:#LUT:D=(((~A4*(A2+A1))+A4)*A3) GYMUX::G REVUSED::#OFF SRINV::SR SYNC_ATTR::ASYNC XBUSED::#OFF XUSED::#OFF YBUSED::#OFF YUSED::#OFF " ; inst "u8/Mtridata_DAC_D<10>" "SLICEL",placed CLB_X3Y7 SLICE_X5Y12 , cfg " BXINV::#OFF BYINV::#OFF CEINV::#OFF CLKINV::CLK COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DXMUX::1 DYMUX::1 F:u8/Mtridata_DAC_D_mux0000<10>1:#LUT:D=(A1*A3) F5USED::#OFF FFX:u8/Mtridata_DAC_D_13:#LATCH FFX_INIT_ATTR::INIT0 FFX_SR_ATTR::SRLOW FFY:u8/Mtridata_DAC_D_7:#LATCH FFY_INIT_ATTR::INIT0 FFY_SR_ATTR::SRLOW FXMUX::F FXUSED::#OFF G:u8/Mtridata_DAC_D_mux0000<0>1:#LUT:D=(A3*A4) GYMUX::G REVUSED::#OFF SRINV::#OFF SYNC_ATTR::ASYNC XBUSED::#OFF XUSED::#OFF YBUSED::#OFF YUSED::#OFF " ; inst "u7/u6/reg<13>" "SLICEL",placed CLB_X1Y14 SLICE_X1Y26 , cfg " BXINV::BX BYINV::#OFF CEINV::CE CLKINV::CLK COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DXMUX::0 DYMUX::1 F::#OFF F5USED::#OFF FFX:u7/u6/reg_13:#FF FFX_INIT_ATTR::INIT0 FFX_SR_ATTR::SRLOW FFY:u7/u6/reg_12:#FF FFY_INIT_ATTR::INIT0 FFY_SR_ATTR::SRLOW FXMUX::#OFF FXUSED::#OFF G:u7/u6/reg_1211:#LUT:D=(A3*A2) GYMUX::G REVUSED::#OFF SRINV::SR SYNC_ATTR::ASYNC XBUSED::#OFF XUSED::#OFF YBUSED::#OFF YUSED::#OFF " ; inst "u2/ReadCount<3>" "SLICEL",placed CLB_X6Y11 SLICE_X10Y20 , cfg " BXINV::#OFF BYINV::#OFF CEINV::CE CLKINV::CLK COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DXMUX::1 DYMUX::1 F:u2/Mcount_ReadCount_xor<3>11:#LUT:D=((~A4*(A3*(A1*A2)))+(A4*(~A3+(~A1+~A2)))) F5USED::#OFF FFX:u2/ReadCount_3:#FF FFX_INIT_ATTR::INIT0 FFX_SR_ATTR::SRLOW FFY:u2/ReadCount_2:#FF FFY_INIT_ATTR::INIT0 FFY_SR_ATTR::SRLOW FXMUX::F FXUSED::#OFF G:u2/Mcount_ReadCount_xor<2>11:#LUT:D=((~A2*(A1*A3))+(A2*(~A1+~A3))) GYMUX::G REVUSED::#OFF SRINV::SR SYNC_ATTR::ASYNC XBUSED::#OFF XUSED::#OFF YBUSED::#OFF YUSED::#OFF " ; inst "u1/g2/count<3>" "SLICEL",placed CLB_X13Y10 SLICE_X16Y18 , cfg " BXINV::#OFF BYINV::#OFF CEINV::CE CLKINV::CLK COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DXMUX::1 DYMUX::1 F:u1/g2/Mcount_count_xor<3>11:#LUT:D=((~A4*(A2*(A3*A1)))+(A4*(~A2+(~A3+~A1)))) F5USED::#OFF FFX:u1/g2/count_3:#FF FFX_INIT_ATTR::INIT0 FFX_SR_ATTR::SRLOW FFY:u1/g2/count_2:#FF FFY_INIT_ATTR::INIT0 FFY_SR_ATTR::SRLOW FXMUX::F FXUSED::#OFF G:u1/g2/Mcount_count_xor<2>11:#LUT:D=((~A4*(A1*A3))+(A4*(~A1+~A3))) GYMUX::G REVUSED::#OFF SRINV::SR SYNC_ATTR::ASYNC XBUSED::#OFF XUSED::#OFF YBUSED::#OFF YUSED::#OFF " ; inst "u1/g2/count<6>" "SLICEL",placed CLB_X13Y10 SLICE_X17Y18 , cfg " BXINV::#OFF BYINV::#OFF CEINV::CE CLKINV::CLK COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DXMUX::1 DYMUX::1 F:u1/g2/Mcount_count61:#LUT:D=((~A1*A3)+(A1*((~A3*(~A2*A4))+(A3*(A2+~A4))))) F5USED::#OFF FFX:u1/g2/count_6:#FF FFX_INIT_ATTR::INIT0 FFX_SR_ATTR::SRLOW FFY:u1/g2/count_5:#FF FFY_INIT_ATTR::INIT0 FFY_SR_ATTR::SRLOW FXMUX::F FXUSED::#OFF G:u1/g2/Mcount_count51:#LUT:D=((~A4*(~A2*A1))+(A4*(A2+~A1))) GYMUX::G REVUSED::#OFF SRINV::SR SYNC_ATTR::ASYNC XBUSED::#OFF XUSED::#OFF YBUSED::#OFF YUSED::#OFF " ; inst "u7/u8/Go_next_clk" "SLICEL",placed CLB_X4Y13 SLICE_X6Y25 , cfg " BXINV::#OFF BYINV::#OFF CEINV::CE_B CLKINV::CLK COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DXMUX::#OFF DYMUX::1 F:u7/u9/CycNum_not00011:#LUT:D=(A1*(A2*~A3)) F5USED::#OFF FFX::#OFF FFX_INIT_ATTR::#OFF FFX_SR_ATTR::#OFF FFY:u7/u8/Go_next_clk:#FF FFY_INIT_ATTR::INIT0 FFY_SR_ATTR::SRLOW FXMUX::F FXUSED::#OFF G:u7/u8/Go_next_clk_mux00031:#LUT:D=((~A3*(A1*A2))+A4) GYMUX::G REVUSED::#OFF SRINV::SR SYNC_ATTR::ASYNC XBUSED::#OFF XUSED::0 YBUSED::#OFF YUSED::#OFF " ; inst "u7/u1/count<1>" "SLICEL",placed CLB_X3Y16 SLICE_X5Y31 , cfg " BXINV::#OFF BYINV::#OFF CEINV::CE CLKINV::CLK COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DXMUX::#OFF DYMUX::1 F:u7/u5/A_addr_not00011:#LUT:D=(~A2*(~A1*A4)) F5USED::#OFF FFX::#OFF FFX_INIT_ATTR::#OFF FFX_SR_ATTR::#OFF FFY:u7/u1/count_1:#FF FFY_INIT_ATTR::INIT1 FFY_SR_ATTR::SRHIGH FXMUX::F FXUSED::#OFF G:u7/u1/Mcount_count_xor<1>11:#LUT:D=((~A4*(A3*A1))+(A4*~A3)) GYMUX::G REVUSED::#OFF SRINV::SR SYNC_ATTR::ASYNC XBUSED::#OFF XUSED::0 YBUSED::#OFF YUSED::#OFF " ; inst "u7/u1/count<3>" "SLICEL",placed CLB_X2Y16 SLICE_X3Y30 , cfg " BXINV::#OFF BYINV::#OFF CEINV::CE CLKINV::CLK COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DXMUX::1 DYMUX::1 F:u7/u1/Mcount_count_xor<3>11:#LUT:D=((~A1*(A4*(A3*A2)))+(A1*(~A4+(~A3+~A2)))) F5USED::#OFF FFX:u7/u1/count_3:#FF FFX_INIT_ATTR::INIT0 FFX_SR_ATTR::SRLOW FFY:u7/u1/count_2:#FF FFY_INIT_ATTR::INIT0 FFY_SR_ATTR::SRLOW FXMUX::F FXUSED::#OFF G:u7/u1/Mcount_count_xor<2>11:#LUT:D=((~A3*(A1*A4))+(A3*(~A1+~A4))) GYMUX::G REVUSED::#OFF SRINV::SR SYNC_ATTR::ASYNC XBUSED::#OFF XUSED::#OFF YBUSED::#OFF YUSED::#OFF " ; inst "u1/m2/m2/u1/Q_int" "SLICEL",placed CLB_X7Y1 SLICE_X13Y0 , cfg " BXINV::#OFF BYINV::#OFF CEINV::#OFF CLKINV::CLK_B COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DXMUX::#OFF DYMUX::1 F::#OFF F5USED::#OFF FFX::#OFF FFX_INIT_ATTR::#OFF FFX_SR_ATTR::#OFF FFY:u1/m2/m2/u1/Q_int:#FF FFY_INIT_ATTR::INIT0 FFY_SR_ATTR::SRLOW FXMUX::#OFF FXUSED::#OFF G:u1/m2/m1/En1:#LUT:D=(~A3*(~A2*A1)) GYMUX::G REVUSED::#OFF SRINV::#OFF SYNC_ATTR::ASYNC XBUSED::#OFF XUSED::#OFF YBUSED::#OFF YUSED::0 " ; inst "u6/u1/Q_int" "SLICEL",placed CLB_X13Y12 SLICE_X16Y22 , cfg " BXINV::#OFF BYINV::#OFF CEINV::#OFF CLKINV::CLK_B COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DXMUX::#OFF DYMUX::1 F:u4/u1/Q1:#LUT:D=(~A1*(~A2*(~A3*A4))) F5USED::#OFF FFX::#OFF FFX_INIT_ATTR::#OFF FFX_SR_ATTR::#OFF FFY:u6/u1/Q_int:#FF FFY_INIT_ATTR::INIT0 FFY_SR_ATTR::SRLOW FXMUX::F FXUSED::#OFF G:u6/En_tmp11:#LUT:D=(~A2*A3) GYMUX::G REVUSED::#OFF SRINV::SR SYNC_ATTR::SYNC XBUSED::#OFF XUSED::0 YBUSED::#OFF YUSED::#OFF " ; inst "r1/state<2>" "SLICEL",placed CLB_X8Y11 SLICE_X14Y20 , cfg " BXINV::#OFF BYINV::#OFF CEINV::#OFF CLKINV::CLK_B COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DXMUX::#OFF DYMUX::1 F::#OFF F5USED::#OFF FFX::#OFF FFX_INIT_ATTR::#OFF FFX_SR_ATTR::#OFF FFY:r1/state_2:#FF FFY_INIT_ATTR::INIT0 FFY_SR_ATTR::SRLOW FXMUX::#OFF FXUSED::#OFF G:state_D<2>LogicTrst1:#LUT:D=(~A2+(A3+(A4+A1))) GYMUX::G REVUSED::#OFF SRINV::SR SYNC_ATTR::ASYNC XBUSED::#OFF XUSED::#OFF YBUSED::#OFF YUSED::#OFF _GND_SOURCE::X " ; inst "u8/Mtrien_DAC_Addr" "SLICEL",placed CLB_X7Y9 SLICE_X12Y16 , cfg " BXINV::#OFF BYINV::#OFF CEINV::#OFF CLKINV::CLK COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DXMUX::#OFF DYMUX::1 F:u8/Go_PacketSkip_and00001:#LUT:D=(~A2*A3) F5USED::#OFF FFX::#OFF FFX_INIT_ATTR::#OFF FFX_SR_ATTR::#OFF FFY:u8/Mtrien_DAC_Addr:#LATCH FFY_INIT_ATTR::INIT0 FFY_SR_ATTR::SRLOW FXMUX::F FXUSED::#OFF G:u8/Mtrien_DAC_Addr_mux00001:#LUT:D=(~A3*~A2) GYMUX::G REVUSED::#OFF SRINV::#OFF SYNC_ATTR::ASYNC XBUSED::#OFF XUSED::0 YBUSED::#OFF YUSED::0 " ; inst "u1/p4/count<1>" "SLICEL",placed CLB_X16Y3 SLICE_X22Y5 , cfg " BXINV::#OFF BYINV::#OFF CEINV::#OFF CLKINV::CLK COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DXMUX::#OFF DYMUX::1 F::#OFF F5USED::#OFF FFX::#OFF FFX_INIT_ATTR::#OFF FFX_SR_ATTR::#OFF FFY:u1/p4/count_1:#FF FFY_INIT_ATTR::INIT0 FFY_SR_ATTR::SRLOW FXMUX::#OFF FXUSED::#OFF G:u1/p4/Mcount_count_eqn_12:#LUT:D=(((~A3*(A4+A1))+A3)*A2) GYMUX::G REVUSED::#OFF SRINV::SR SYNC_ATTR::ASYNC XBUSED::#OFF XUSED::#OFF YBUSED::#OFF YUSED::#OFF " ; inst "u1/p4/count<3>" "SLICEL",placed CLB_X16Y4 SLICE_X22Y7 , cfg " BXINV::#OFF BYINV::#OFF CEINV::#OFF CLKINV::CLK COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DXMUX::1 DYMUX::1 F:u1/p4/Mcount_count_eqn_31:#LUT:D=(((~A1*(A3+A4))+A1)*A2) F5USED::#OFF FFX:u1/p4/count_3:#FF FFX_INIT_ATTR::INIT0 FFX_SR_ATTR::SRLOW FFY:u1/p4/count_2:#FF FFY_INIT_ATTR::INIT0 FFY_SR_ATTR::SRLOW FXMUX::F FXUSED::#OFF G:u1/p4/Mcount_count_eqn_21:#LUT:D=(((~A2*(A4+A1))+A2)*A3) GYMUX::G REVUSED::#OFF SRINV::SR SYNC_ATTR::ASYNC XBUSED::#OFF XUSED::#OFF YBUSED::#OFF YUSED::#OFF " ; inst "u1/p4/count<5>" "SLICEL",placed CLB_X16Y4 SLICE_X22Y6 , cfg " BXINV::#OFF BYINV::#OFF CEINV::#OFF CLKINV::CLK COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DXMUX::1 DYMUX::1 F:u1/p4/Mcount_count_eqn_51:#LUT:D=(((~A2*(A3+A4))+A2)*A1) F5USED::#OFF FFX:u1/p4/count_5:#FF FFX_INIT_ATTR::INIT0 FFX_SR_ATTR::SRLOW FFY:u1/p4/count_4:#FF FFY_INIT_ATTR::INIT0 FFY_SR_ATTR::SRLOW FXMUX::F FXUSED::#OFF G:u1/p4/Mcount_count_eqn_41:#LUT:D=(((~A2*(A3+A1))+A2)*A4) GYMUX::G REVUSED::#OFF SRINV::SR SYNC_ATTR::ASYNC XBUSED::#OFF XUSED::#OFF YBUSED::#OFF YUSED::#OFF " ; inst "u1/p4/count<7>" "SLICEL",placed CLB_X16Y5 SLICE_X22Y8 , cfg " BXINV::#OFF BYINV::#OFF CEINV::#OFF CLKINV::CLK COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DXMUX::1 DYMUX::1 F:u1/p4/Mcount_count_eqn_71:#LUT:D=(((~A1*(A3+A4))+A1)*A2) F5USED::#OFF FFX:u1/p4/count_7:#FF FFX_INIT_ATTR::INIT0 FFX_SR_ATTR::SRLOW FFY:u1/p4/count_6:#FF FFY_INIT_ATTR::INIT0 FFY_SR_ATTR::SRLOW FXMUX::F FXUSED::#OFF G:u1/p4/Mcount_count_eqn_61:#LUT:D=(((~A1*(A2+A4))+A1)*A3) GYMUX::G REVUSED::#OFF SRINV::SR SYNC_ATTR::ASYNC XBUSED::#OFF XUSED::#OFF YBUSED::#OFF YUSED::#OFF " ; inst "u1/p4/count<9>" "SLICEL",placed CLB_X16Y6 SLICE_X22Y11 , cfg " BXINV::#OFF BYINV::#OFF CEINV::#OFF CLKINV::CLK COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DXMUX::1 DYMUX::1 F:u1/p4/Mcount_count_eqn_91:#LUT:D=(((~A4*(A3+A2))+A4)*A1) F5USED::#OFF FFX:u1/p4/count_9:#FF FFX_INIT_ATTR::INIT0 FFX_SR_ATTR::SRLOW FFY:u1/p4/count_8:#FF FFY_INIT_ATTR::INIT0 FFY_SR_ATTR::SRLOW FXMUX::F FXUSED::#OFF G:u1/p4/Mcount_count_eqn_81:#LUT:D=(((~A1*(A4+A2))+A1)*A3) GYMUX::G REVUSED::#OFF SRINV::SR SYNC_ATTR::ASYNC XBUSED::#OFF XUSED::#OFF YBUSED::#OFF YUSED::#OFF " ; inst "u9/u1/count<4>" "SLICEL",placed CLB_X1Y8 SLICE_X1Y14 , cfg " BXINV::#OFF BYINV::#OFF CEINV::#OFF CLKINV::CLK_B COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DXMUX::1 DYMUX::1 F:u9/u1/count_mux0003<0>1:#LUT:D=((~A4*(A3*(A2*~A1)))+(A4*((A3@A2)+A1))) F5USED::#OFF FFX:u9/u1/count_4:#FF FFX_INIT_ATTR::INIT0 FFX_SR_ATTR::SRLOW FFY:u9/u1/count_3:#FF FFY_INIT_ATTR::INIT0 FFY_SR_ATTR::SRLOW FXMUX::F FXUSED::#OFF G:u9/u1/count_mux0003<1>1:#LUT:D=((~A1*(A3*(A4*A2)))+(A1*(~A3+(~A4+~A2)))) GYMUX::G REVUSED::#OFF SRINV::SR SYNC_ATTR::ASYNC XBUSED::#OFF XUSED::#OFF YBUSED::#OFF YUSED::#OFF " ; inst "u7/u7/reg<11>" "SLICEL",placed CLB_X4Y15 SLICE_X7Y29 , cfg " BXINV::#OFF BYINV::#OFF CEINV::#OFF CLKINV::CLK COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DXMUX::1 DYMUX::1 F:u7/u7/reg_11_mux00011:#LUT:D=((~A1*A3)+(A1*A4)) F5USED::#OFF FFX:u7/u7/reg_11:#FF FFX_INIT_ATTR::INIT0 FFX_SR_ATTR::SRLOW FFY:u7/u7/reg_10:#FF FFY_INIT_ATTR::INIT0 FFY_SR_ATTR::SRLOW FXMUX::F FXUSED::#OFF G:u7/u7/reg_10_mux00011:#LUT:D=(A1*A2) GYMUX::G REVUSED::#OFF SRINV::SR SYNC_ATTR::ASYNC XBUSED::#OFF XUSED::#OFF YBUSED::#OFF YUSED::#OFF " ; inst "u1/m3/m2/u1/Q_int" "SLICEL",placed CLB_X4Y1 SLICE_X7Y0 , cfg " BXINV::#OFF BYINV::#OFF CEINV::#OFF CLKINV::CLK_B COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DXMUX::#OFF DYMUX::1 F::#OFF F5USED::#OFF FFX::#OFF FFX_INIT_ATTR::#OFF FFX_SR_ATTR::#OFF FFY:u1/m3/m2/u1/Q_int:#FF FFY_INIT_ATTR::INIT0 FFY_SR_ATTR::SRLOW FXMUX::#OFF FXUSED::#OFF G:u1/m3/m1/En1:#LUT:D=(~A2*((~A3+(A3*A4))*A1)) GYMUX::G REVUSED::#OFF SRINV::#OFF SYNC_ATTR::ASYNC XBUSED::#OFF XUSED::#OFF YBUSED::#OFF YUSED::0 " ; inst "u8/u2/Q_int" "SLICEL",placed CLB_X7Y9 SLICE_X13Y16 , cfg " BXINV::#OFF BYINV::#OFF CEINV::#OFF CLKINV::CLK_B COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DXMUX::#OFF DYMUX::1 F:u8/u5/En1:#LUT:D=(~A1*((~A2+(A2*A3))*A4)) F5USED::#OFF FFX::#OFF FFX_INIT_ATTR::#OFF FFX_SR_ATTR::#OFF FFY:u8/u2/Q_int:#FF FFY_INIT_ATTR::INIT0 FFY_SR_ATTR::SRLOW FXMUX::F FXUSED::#OFF G:u8/En_and00001:#LUT:D=(A2*(A4*(A3*~A1))) GYMUX::G REVUSED::#OFF SRINV::SR SYNC_ATTR::SYNC XBUSED::#OFF XUSED::0 YBUSED::#OFF YUSED::0 " ; inst "u1/m4/m2/u1/Q_int" "SLICEL",placed CLB_X2Y2 SLICE_X2Y2 , cfg " BXINV::#OFF BYINV::#OFF CEINV::#OFF CLKINV::CLK_B COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DXMUX::#OFF DYMUX::1 F::#OFF F5USED::#OFF FFX::#OFF FFX_INIT_ATTR::#OFF FFX_SR_ATTR::#OFF FFY:u1/m4/m2/u1/Q_int:#FF FFY_INIT_ATTR::INIT0 FFY_SR_ATTR::SRLOW FXMUX::#OFF FXUSED::#OFF G:u1/m4/m1/En1:#LUT:D=(~A3*((~A2+(A2*A1))*A4)) GYMUX::G REVUSED::#OFF SRINV::#OFF SYNC_ATTR::ASYNC XBUSED::#OFF XUSED::#OFF YBUSED::#OFF YUSED::0 " ; inst "u1/m5/m2/u1/Q_int" "SLICEL",placed CLB_X1Y4 SLICE_X1Y6 , cfg " BXINV::#OFF BYINV::#OFF CEINV::#OFF CLKINV::CLK_B COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DXMUX::#OFF DYMUX::1 F::#OFF F5USED::#OFF FFX::#OFF FFX_INIT_ATTR::#OFF FFX_SR_ATTR::#OFF FFY:u1/m5/m2/u1/Q_int:#FF FFY_INIT_ATTR::INIT0 FFY_SR_ATTR::SRLOW FXMUX::#OFF FXUSED::#OFF G:u1/m5/m1/En1:#LUT:D=(~A1*((~A4+(A4*A2))*A3)) GYMUX::G REVUSED::#OFF SRINV::#OFF SYNC_ATTR::ASYNC XBUSED::#OFF XUSED::#OFF YBUSED::#OFF YUSED::0 " ; inst "u7/u6/reg_121" "SLICEM",placed CLB_X1Y14 SLICE_X0Y27 , cfg " BXINV::#OFF BYINV::BY BYINVOUTUSED::#OFF BYOUTUSED::#OFF CEINV::CE CLKINV::CLK COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DIF_MUX::#OFF DIGUSED::#OFF DIG_MUX::BY DXMUX::#OFF DYMUX::1 F::#OFF F5USED::#OFF FFX::#OFF FFX_INIT_ATTR::#OFF FFX_SR_ATTR::#OFF FFY:u7/u6/reg_121:#FF FFY_INIT_ATTR::INIT0 FFY_SR_ATTR::SRLOW FXMUX::#OFF FXUSED::#OFF F_ATTR::#OFF G:u7/u6/Mshreg_reg_12:#RAM:D=0x0000 GYMUX::G G_ATTR::SHIFT_REG REVUSED::#OFF SHIFTOUTUSED::#OFF SLICEWE0USED::#OFF SLICEWE1USED::#OFF SRFFMUX::#OFF SRINV::SR SYNC_ATTR::ASYNC WF1USED::#OFF WF2USED::#OFF WF3USED::#OFF WF4USED::#OFF WG1USED::#OFF WG2USED::#OFF WG3USED::#OFF WG4USED::#OFF XBMUX::#OFF XUSED::#OFF YBMUX::#OFF YBUSED::#OFF YUSED::#OFF WSGEN:u7/u6/Mshreg_reg_12.CE: " ; inst "u1/m6/m/m2/u1/Q_int" "SLICEL",placed CLB_X4Y4 SLICE_X7Y7 , cfg " BXINV::#OFF BYINV::#OFF CEINV::#OFF CLKINV::CLK_B COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DXMUX::#OFF DYMUX::1 F::#OFF F5USED::#OFF FFX::#OFF FFX_INIT_ATTR::#OFF FFX_SR_ATTR::#OFF FFY:u1/m6/m/m2/u1/Q_int:#FF FFY_INIT_ATTR::INIT0 FFY_SR_ATTR::SRLOW FXMUX::#OFF FXUSED::#OFF G:u1/m6/m/m1/En1:#LUT:D=(~A2*(~A1*A4)) GYMUX::G REVUSED::#OFF SRINV::#OFF SYNC_ATTR::ASYNC XBUSED::#OFF XUSED::#OFF YBUSED::#OFF YUSED::0 " ; inst "u1/p5/count<1>" "SLICEL",placed CLB_X16Y8 SLICE_X22Y14 , cfg " BXINV::#OFF BYINV::#OFF CEINV::#OFF CLKINV::CLK COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DXMUX::#OFF DYMUX::1 F::#OFF F5USED::#OFF FFX::#OFF FFX_INIT_ATTR::#OFF FFX_SR_ATTR::#OFF FFY:u1/p5/count_1:#FF FFY_INIT_ATTR::INIT0 FFY_SR_ATTR::SRLOW FXMUX::#OFF FXUSED::#OFF G:u1/p5/Mcount_count_eqn_12:#LUT:D=(((~A3*(A4+A2))+A3)*A1) GYMUX::G REVUSED::#OFF SRINV::SR SYNC_ATTR::ASYNC XBUSED::#OFF XUSED::#OFF YBUSED::#OFF YUSED::#OFF _GND_SOURCE::X " ; inst "u1/p5/count<3>" "SLICEL",placed CLB_X16Y9 SLICE_X22Y17 , cfg " BXINV::#OFF BYINV::#OFF CEINV::#OFF CLKINV::CLK COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DXMUX::1 DYMUX::1 F:u1/p5/Mcount_count_eqn_31:#LUT:D=(((~A1*(A4+A3))+A1)*A2) F5USED::#OFF FFX:u1/p5/count_3:#FF FFX_INIT_ATTR::INIT0 FFX_SR_ATTR::SRLOW FFY:u1/p5/count_2:#FF FFY_INIT_ATTR::INIT0 FFY_SR_ATTR::SRLOW FXMUX::F FXUSED::#OFF G:u1/p5/Mcount_count_eqn_21:#LUT:D=(((~A2*(A4+A1))+A2)*A3) GYMUX::G REVUSED::#OFF SRINV::SR SYNC_ATTR::ASYNC XBUSED::#OFF XUSED::#OFF YBUSED::#OFF YUSED::#OFF " ; inst "u1/p5/count<5>" "SLICEL",placed CLB_X16Y9 SLICE_X22Y16 , cfg " BXINV::#OFF BYINV::#OFF CEINV::#OFF CLKINV::CLK COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DXMUX::1 DYMUX::1 F:u1/p5/Mcount_count_eqn_51:#LUT:D=(((~A2*(A4+A3))+A2)*A1) F5USED::#OFF FFX:u1/p5/count_5:#FF FFX_INIT_ATTR::INIT0 FFX_SR_ATTR::SRLOW FFY:u1/p5/count_4:#FF FFY_INIT_ATTR::INIT0 FFY_SR_ATTR::SRLOW FXMUX::F FXUSED::#OFF G:u1/p5/Mcount_count_eqn_41:#LUT:D=(((~A1*(A2+A3))+A1)*A4) GYMUX::G REVUSED::#OFF SRINV::SR SYNC_ATTR::ASYNC XBUSED::#OFF XUSED::#OFF YBUSED::#OFF YUSED::#OFF " ; inst "u1/p5/count<7>" "SLICEL",placed CLB_X15Y10 SLICE_X21Y18 , cfg " BXINV::#OFF BYINV::#OFF CEINV::#OFF CLKINV::CLK COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DXMUX::1 DYMUX::1 F:u1/p5/Mcount_count_eqn_71:#LUT:D=(((~A1*(A3+A4))+A1)*A2) F5USED::#OFF FFX:u1/p5/count_7:#FF FFX_INIT_ATTR::INIT0 FFX_SR_ATTR::SRLOW FFY:u1/p5/count_6:#FF FFY_INIT_ATTR::INIT0 FFY_SR_ATTR::SRLOW FXMUX::F FXUSED::#OFF G:u1/p5/Mcount_count_eqn_61:#LUT:D=(((~A1*(A2+A4))+A1)*A3) GYMUX::G REVUSED::#OFF SRINV::SR SYNC_ATTR::ASYNC XBUSED::#OFF XUSED::#OFF YBUSED::#OFF YUSED::#OFF " ; inst "u1/p5/count<9>" "SLICEL",placed CLB_X16Y10 SLICE_X22Y19 , cfg " BXINV::#OFF BYINV::#OFF CEINV::#OFF CLKINV::CLK COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DXMUX::1 DYMUX::1 F:u1/p5/Mcount_count_eqn_91:#LUT:D=(((~A3*(A4+A2))+A3)*A1) F5USED::#OFF FFX:u1/p5/count_9:#FF FFX_INIT_ATTR::INIT0 FFX_SR_ATTR::SRLOW FFY:u1/p5/count_8:#FF FFY_INIT_ATTR::INIT0 FFY_SR_ATTR::SRLOW FXMUX::F FXUSED::#OFF G:u1/p5/Mcount_count_eqn_81:#LUT:D=(((~A1*(A3+A2))+A1)*A4) GYMUX::G REVUSED::#OFF SRINV::SR SYNC_ATTR::ASYNC XBUSED::#OFF XUSED::#OFF YBUSED::#OFF YUSED::#OFF " ; inst "u6/Addr<3>" "SLICEL",placed CLB_X7Y12 SLICE_X13Y23 , cfg " BXINV::#OFF BYINV::#OFF CEINV::CE CLKINV::CLK_B COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DXMUX::1 DYMUX::1 F:u6/Mcount_Addr_xor<3>11:#LUT:D=((~A1*(A3*(A4*A2)))+(A1*(~A3+(~A4+~A2)))) F5USED::#OFF FFX:u6/Addr_3:#FF FFX_INIT_ATTR::INIT1 FFX_SR_ATTR::SRHIGH FFY:u6/Addr_2:#FF FFY_INIT_ATTR::INIT1 FFY_SR_ATTR::SRHIGH FXMUX::F FXUSED::#OFF G:u6/Mcount_Addr_xor<2>11:#LUT:D=((~A2*(A4*A3))+(A2*(~A4+~A3))) GYMUX::G REVUSED::#OFF SRINV::SR SYNC_ATTR::ASYNC XBUSED::#OFF XUSED::#OFF YBUSED::#OFF YUSED::#OFF " ; inst "u7/u7/reg<7>" "SLICEL",placed CLB_X3Y15 SLICE_X5Y28 , cfg " BXINV::#OFF BYINV::#OFF CEINV::#OFF CLKINV::CLK COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DXMUX::1 DYMUX::1 F:u7/u7/reg_7_mux00011:#LUT:D=((~A1*A3)+(A1*A4)) F5USED::#OFF FFX:u7/u7/reg_7:#FF FFX_INIT_ATTR::INIT0 FFX_SR_ATTR::SRLOW FFY:u7/u7/reg_6:#FF FFY_INIT_ATTR::INIT0 FFY_SR_ATTR::SRLOW FXMUX::F FXUSED::#OFF G:u7/u7/reg_6_mux00011:#LUT:D=((~A3*A2)+(A3*A1)) GYMUX::G REVUSED::#OFF SRINV::SR SYNC_ATTR::ASYNC XBUSED::#OFF XUSED::#OFF YBUSED::#OFF YUSED::#OFF " ; inst "u7/u7/reg<9>" "SLICEL",placed CLB_X4Y15 SLICE_X6Y28 , cfg " BXINV::#OFF BYINV::#OFF CEINV::#OFF CLKINV::CLK COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DXMUX::1 DYMUX::1 F:u7/u7/reg_9_mux00011:#LUT:D=(A4*A2) F5USED::#OFF FFX:u7/u7/reg_9:#FF FFX_INIT_ATTR::INIT0 FFX_SR_ATTR::SRLOW FFY:u7/u7/reg_8:#FF FFY_INIT_ATTR::INIT0 FFY_SR_ATTR::SRLOW FXMUX::F FXUSED::#OFF G:u7/u7/reg_8_mux00011:#LUT:D=((~A4*A1)+(A4*A2)) GYMUX::G REVUSED::#OFF SRINV::SR SYNC_ATTR::ASYNC XBUSED::#OFF XUSED::#OFF YBUSED::#OFF YUSED::#OFF " ; inst "u1/p4/count<11>" "SLICEL",placed CLB_X16Y6 SLICE_X22Y10 , cfg " BXINV::#OFF BYINV::#OFF CEINV::#OFF CLKINV::CLK COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DXMUX::1 DYMUX::1 F:u1/p4/Mcount_count_eqn_111:#LUT:D=(((~A1*(A4+A3))+A1)*A2) F5USED::#OFF FFX:u1/p4/count_11:#FF FFX_INIT_ATTR::INIT0 FFX_SR_ATTR::SRLOW FFY:u1/p4/count_10:#FF FFY_INIT_ATTR::INIT0 FFY_SR_ATTR::SRLOW FXMUX::F FXUSED::#OFF G:u1/p4/Mcount_count_eqn_101:#LUT:D=(((~A1*(A4+A2))+A1)*A3) GYMUX::G REVUSED::#OFF SRINV::SR SYNC_ATTR::ASYNC XBUSED::#OFF XUSED::#OFF YBUSED::#OFF YUSED::#OFF " ; inst "u7/u9/T_iA_int" "SLICEL",placed CLB_X4Y14 SLICE_X7Y27 , cfg " BXINV::#OFF BYINV::#OFF CEINV::#OFF CLKINV::CLK_B COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DXMUX::#OFF DYMUX::1 F:u7/u8/Addr_mem_and00001:#LUT:D=(~A4*A3) F5USED::#OFF FFX::#OFF FFX_INIT_ATTR::#OFF FFX_SR_ATTR::#OFF FFY:u7/u9/T_iA_int:#LATCH FFY_INIT_ATTR::INIT0 FFY_SR_ATTR::SRLOW FXMUX::F FXUSED::#OFF G:u7/u9/T_iA_int_mux00011:#LUT:D=(~A4*A1) GYMUX::G REVUSED::#OFF SRINV::#OFF SYNC_ATTR::ASYNC XBUSED::#OFF XUSED::0 YBUSED::#OFF YUSED::#OFF " ; inst "u8/Mtridata_DAC_Addr<1>" "SLICEL",placed CLB_X3Y7 SLICE_X5Y13 , cfg " BXINV::#OFF BYINV::#OFF CEINV::#OFF CLKINV::CLK COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DXMUX::1 DYMUX::1 F:u8/Mtridata_DAC_Addr_mux0000<1>1:#LUT:D=(A3*A4) F5USED::#OFF FFX:u8/Mtridata_DAC_Addr_1:#LATCH FFX_INIT_ATTR::INIT0 FFX_SR_ATTR::SRLOW FFY:u8/Mtridata_DAC_Addr_0:#LATCH FFY_INIT_ATTR::INIT0 FFY_SR_ATTR::SRLOW FXMUX::F FXUSED::#OFF G:u8/Mtridata_DAC_Addr_mux0000<0>1:#LUT:D=(A3*A1) GYMUX::G REVUSED::#OFF SRINV::#OFF SYNC_ATTR::ASYNC XBUSED::#OFF XUSED::#OFF YBUSED::#OFF YUSED::#OFF " ; inst "u8/Mtridata_DAC_Addr<3>" "SLICEL",placed CLB_X4Y9 SLICE_X6Y16 , cfg " BXINV::#OFF BYINV::#OFF CEINV::#OFF CLKINV::CLK COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DXMUX::1 DYMUX::1 F:u8/Mtridata_DAC_Addr_mux0000<3>1:#LUT:D=(A3*A2) F5USED::#OFF FFX:u8/Mtridata_DAC_Addr_3:#LATCH FFX_INIT_ATTR::INIT0 FFX_SR_ATTR::SRLOW FFY:u8/Mtridata_DAC_Addr_2:#LATCH FFY_INIT_ATTR::INIT0 FFY_SR_ATTR::SRLOW FXMUX::F FXUSED::#OFF G:u8/Mtridata_DAC_Addr_mux0000<2>1:#LUT:D=(A3*A1) GYMUX::G REVUSED::#OFF SRINV::#OFF SYNC_ATTR::ASYNC XBUSED::#OFF XUSED::#OFF YBUSED::#OFF YUSED::#OFF " ; inst "u8/Mtridata_DAC_Addr<4>" "SLICEL",placed CLB_X5Y10 SLICE_X8Y18 , cfg " BXINV::#OFF BYINV::#OFF CEINV::#OFF CLKINV::CLK COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DXMUX::#OFF DYMUX::1 F::#OFF F5USED::#OFF FFX::#OFF FFX_INIT_ATTR::#OFF FFX_SR_ATTR::#OFF FFY:u8/Mtridata_DAC_Addr_4:#LATCH FFY_INIT_ATTR::INIT0 FFY_SR_ATTR::SRLOW FXMUX::#OFF FXUSED::#OFF G:u8/Mtridata_DAC_Addr_mux0000<4>1:#LUT:D=(A2*A3) GYMUX::G REVUSED::#OFF SRINV::#OFF SYNC_ATTR::ASYNC XBUSED::#OFF XUSED::#OFF YBUSED::#OFF YUSED::#OFF " ; inst "u1/g1/Qa" "SLICEL",placed CLB_X14Y13 SLICE_X19Y24 , cfg " BXINV::#OFF BYINV::#OFF CEINV::#OFF CLKINV::CLK_B COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DXMUX::1 DYMUX::1 F:u1/En11:#LUT:D=(~A3*~A2) F5USED::#OFF FFX:u1/g1/Qa:#FF FFX_INIT_ATTR::INIT0 FFX_SR_ATTR::SRLOW FFY:u5/u1/Q_int:#FF FFY_INIT_ATTR::INIT0 FFY_SR_ATTR::SRLOW FXMUX::F FXUSED::#OFF G:u5/En11:#LUT:D=(A3*A2) GYMUX::G REVUSED::#OFF SRINV::SR SYNC_ATTR::SYNC XBUSED::#OFF XUSED::#OFF YBUSED::#OFF YUSED::#OFF " ; inst "u7/u7/line" "SLICEL",placed CLB_X4Y16 SLICE_X7Y30 , cfg " BXINV::#OFF BYINV::#OFF CEINV::#OFF CLKINV::CLK COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DXMUX::#OFF DYMUX::1 F:u7/u3/T_CE1:#LUT:D=(A3*A1) F5USED::#OFF FFX::#OFF FFX_INIT_ATTR::#OFF FFX_SR_ATTR::#OFF FFY:u7/u7/line:#FF FFY_INIT_ATTR::INIT0 FFY_SR_ATTR::SRLOW FXMUX::F FXUSED::#OFF G:u7/u7/line_mux00011:#LUT:D=(A3*A4) GYMUX::G REVUSED::#OFF SRINV::SR SYNC_ATTR::ASYNC XBUSED::#OFF XUSED::0 YBUSED::#OFF YUSED::#OFF " ; inst "u8/Addr<3>" "SLICEL",placed CLB_X4Y10 SLICE_X6Y18 , cfg " BXINV::#OFF BYINV::#OFF CEINV::CE CLKINV::CLK COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DXMUX::1 DYMUX::1 F:u8/Result<3>1:#LUT:D=((~A2*(A4*(A3*A1)))+(A2*(~A4+(~A3+~A1)))) F5USED::#OFF FFX:u8/Addr_3:#FF FFX_INIT_ATTR::INIT1 FFX_SR_ATTR::SRHIGH FFY:u8/Addr_2:#FF FFY_INIT_ATTR::INIT1 FFY_SR_ATTR::SRHIGH FXMUX::F FXUSED::#OFF G:u8/Mcount_Addr_xor<2>11:#LUT:D=((~A2*(A3*A4))+(A2*(~A3+~A4))) GYMUX::G REVUSED::#OFF SRINV::SR SYNC_ATTR::ASYNC XBUSED::#OFF XUSED::#OFF YBUSED::#OFF YUSED::#OFF " ; inst "u7/u8/Done_int" "SLICEL",placed CLB_X8Y11 SLICE_X15Y21 , cfg " BXINV::#OFF BYINV::#OFF CEINV::CE CLKINV::CLK COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DXMUX::#OFF DYMUX::1 F:u7/u9/RstCyc_not00011:#LUT:D=(A4*(A3*(A1*~A2))) F5USED::#OFF FFX::#OFF FFX_INIT_ATTR::#OFF FFX_SR_ATTR::#OFF FFY:u7/u8/Done_int:#FF FFY_INIT_ATTR::INIT0 FFY_SR_ATTR::SRLOW FXMUX::F FXUSED::#OFF G:u7/u8/Done_int_mux00021:#LUT:D=(~A1*(~A2*A4)) GYMUX::G REVUSED::#OFF SRINV::#OFF SYNC_ATTR::ASYNC XBUSED::#OFF XUSED::0 YBUSED::#OFF YUSED::#OFF " ; inst "u5/count<0>" "SLICEL",placed CLB_X15Y14 SLICE_X21Y26 , cfg " BXINV::BX_B BYINV::#OFF CEINV::#OFF CLKINV::CLK COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DXMUX::0 DYMUX::1 F:state_D<0>LogicTrst49:#LUT:D=(~A1*(~A2*~A4)) F5USED::#OFF FFX:u5/count_0:#FF FFX_INIT_ATTR::INIT0 FFX_SR_ATTR::SRLOW FFY:u5/count_1:#FF FFY_INIT_ATTR::INIT0 FFY_SR_ATTR::SRLOW FXMUX::F FXUSED::#OFF G:u5/Mcount_count_xor<1>11:#LUT:D=(A4@A1) GYMUX::G REVUSED::#OFF SRINV::SR SYNC_ATTR::ASYNC XBUSED::#OFF XUSED::0 YBUSED::#OFF YUSED::#OFF " ; inst "u1/g3/u2/En" "SLICEL",placed CLB_X7Y4 SLICE_X12Y7 , cfg " BXINV::BX BYINV::BY CEINV::#OFF CLKINV::CLK_B COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DXMUX::0 DYMUX::#OFF F::#OFF F5USED::#OFF FFX:u1/g3/u2/En:#FF FFX_INIT_ATTR::INIT0 FFX_SR_ATTR::SRLOW FFY::#OFF FFY_INIT_ATTR::#OFF FFY_SR_ATTR::#OFF FXMUX::#OFF FXUSED::#OFF G::#OFF GYMUX::#OFF REVUSED::0 SRINV::SR SYNC_ATTR::ASYNC XBUSED::#OFF XUSED::#OFF YBUSED::#OFF YUSED::#OFF " ; inst "u1/g3/u1/Qa" "SLICEL",placed CLB_X7Y2 SLICE_X13Y2 , cfg " BXINV::#OFF BYINV::BY CEINV::#OFF CLKINV::CLK_B COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DXMUX::#OFF DYMUX::0 F::#OFF F5USED::#OFF FFX::#OFF FFX_INIT_ATTR::#OFF FFX_SR_ATTR::#OFF FFY:u1/g3/u1/Qa:#FF FFY_INIT_ATTR::INIT0 FFY_SR_ATTR::SRLOW FXMUX::#OFF FXUSED::#OFF G::#OFF GYMUX::#OFF REVUSED::#OFF SRINV::#OFF SYNC_ATTR::ASYNC XBUSED::#OFF XUSED::#OFF YBUSED::#OFF YUSED::#OFF " ; inst "u1/g3/u1/Qb" "SLICEL",placed CLB_X7Y2 SLICE_X12Y2 , cfg " BXINV::#OFF BYINV::BY CEINV::#OFF CLKINV::CLK COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DXMUX::#OFF DYMUX::0 F::#OFF F5USED::#OFF FFX::#OFF FFX_INIT_ATTR::#OFF FFX_SR_ATTR::#OFF FFY:u1/g3/u1/Qb:#FF FFY_INIT_ATTR::INIT0 FFY_SR_ATTR::SRLOW FXMUX::#OFF FXUSED::#OFF G::#OFF GYMUX::#OFF REVUSED::#OFF SRINV::#OFF SYNC_ATTR::ASYNC XBUSED::#OFF XUSED::#OFF YBUSED::#OFF YUSED::#OFF " ; inst "u1/g3/u3/En" "SLICEL",placed CLB_X13Y2 SLICE_X17Y3 , cfg " BXINV::BX BYINV::BY CEINV::#OFF CLKINV::CLK_B COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DXMUX::0 DYMUX::#OFF F::#OFF F5USED::#OFF FFX:u1/g3/u3/En:#FF FFX_INIT_ATTR::INIT0 FFX_SR_ATTR::SRLOW FFY::#OFF FFY_INIT_ATTR::#OFF FFY_SR_ATTR::#OFF FXMUX::#OFF FXUSED::#OFF G::#OFF GYMUX::#OFF REVUSED::0 SRINV::SR SYNC_ATTR::ASYNC XBUSED::#OFF XUSED::#OFF YBUSED::#OFF YUSED::#OFF " ; inst "u8/l2/u1/Q" "SLICEL",placed CLB_X6Y6 SLICE_X11Y10 , cfg " BXINV::#OFF BYINV::BY CEINV::#OFF CLKINV::CLK COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DXMUX::#OFF DYMUX::0 F::#OFF F5USED::#OFF FFX::#OFF FFX_INIT_ATTR::#OFF FFX_SR_ATTR::#OFF FFY:u8/l2/u1/Q:#FF FFY_INIT_ATTR::INIT0 FFY_SR_ATTR::SRLOW FXMUX::#OFF FXUSED::#OFF G::#OFF GYMUX::#OFF REVUSED::#OFF SRINV::#OFF SYNC_ATTR::ASYNC XBUSED::#OFF XUSED::#OFF YBUSED::#OFF YUSED::#OFF " ; inst "u1/m6/Done_Word_inv" "SLICEL",placed CLB_X5Y4 SLICE_X9Y6 , cfg " BXINV::#OFF BYINV::#OFF CEINV::#OFF CLKINV::#OFF COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DXMUX::#OFF DYMUX::#OFF F:u1/m6/Done_Word_inv1:#LUT:D=(~A1+(A3+A2)) F5USED::#OFF FFX::#OFF FFX_INIT_ATTR::#OFF FFX_SR_ATTR::#OFF FFY::#OFF FFY_INIT_ATTR::#OFF FFY_SR_ATTR::#OFF FXMUX::F FXUSED::#OFF G:u1/m6/m/m2/aL/En1:#LUT:D=(~A3*((~A2+(A2*A1))*A4)) GYMUX::G REVUSED::#OFF SRINV::#OFF SYNC_ATTR::#OFF XBUSED::#OFF XUSED::0 YBUSED::#OFF YUSED::0 " ; inst "u1/Done_Wait210" "SLICEL",placed CLB_X15Y9 SLICE_X21Y16 , cfg " BXINV::#OFF BYINV::#OFF CEINV::#OFF CLKINV::#OFF COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DXMUX::#OFF DYMUX::#OFF F:u1/Done_Wait210:#LUT:D=(A4*(A2*(A1*A3))) F5USED::#OFF FFX::#OFF FFX_INIT_ATTR::#OFF FFX_SR_ATTR::#OFF FFY::#OFF FFY_INIT_ATTR::#OFF FFY_SR_ATTR::#OFF FXMUX::F FXUSED::#OFF G:u1/p5/count_not00014:#LUT:D=(A3+(A2+(A1+A4))) GYMUX::G REVUSED::#OFF SRINV::#OFF SYNC_ATTR::#OFF XBUSED::#OFF XUSED::0 YBUSED::#OFF YUSED::0 " ; inst "u1/p2/Working" "SLICEL",placed CLB_X15Y5 SLICE_X21Y8 , cfg " BXINV::BX BYINV::BY CEINV::CE CLKINV::CLK_B COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DXMUX::0 DYMUX::#OFF F::#OFF F5USED::#OFF FFX:u1/p2/Working:#FF FFX_INIT_ATTR::INIT0 FFX_SR_ATTR::SRLOW FFY::#OFF FFY_INIT_ATTR::#OFF FFY_SR_ATTR::#OFF FXMUX::#OFF FXUSED::#OFF G::#OFF GYMUX::#OFF REVUSED::0 SRINV::SR SYNC_ATTR::ASYNC XBUSED::#OFF XUSED::#OFF YBUSED::#OFF YUSED::#OFF " ; inst "u1/Done_Wait215" "SLICEL",placed CLB_X16Y11 SLICE_X22Y21 , cfg " BXINV::#OFF BYINV::#OFF CEINV::#OFF CLKINV::#OFF COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DXMUX::#OFF DYMUX::#OFF F:u1/Done_Wait215:#LUT:D=(A1*(A3*(A4*A2))) F5USED::#OFF FFX::#OFF FFX_INIT_ATTR::#OFF FFX_SR_ATTR::#OFF FFY::#OFF FFY_INIT_ATTR::#OFF FFY_SR_ATTR::#OFF FXMUX::F FXUSED::#OFF G:u1/p5/count_not00019:#LUT:D=(A1+(A3+(A4+A2))) GYMUX::G REVUSED::#OFF SRINV::#OFF SYNC_ATTR::#OFF XBUSED::#OFF XUSED::0 YBUSED::#OFF YUSED::0 " ; inst "u7/Go_int" "SLICEL",placed CLB_X13Y16 SLICE_X16Y31 , cfg " BXINV::#OFF BYINV::#OFF CEINV::#OFF CLKINV::#OFF COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DXMUX::#OFF DYMUX::#OFF F:u7/Go_int1:#LUT:D=(A1+A2) F5USED::#OFF FFX::#OFF FFX_INIT_ATTR::#OFF FFX_SR_ATTR::#OFF FFY::#OFF FFY_INIT_ATTR::#OFF FFY_SR_ATTR::#OFF FXMUX::F FXUSED::#OFF G:u7/SDI1:#LUT:D=(A2+A1) GYMUX::G REVUSED::#OFF SRINV::#OFF SYNC_ATTR::#OFF XBUSED::#OFF XUSED::0 YBUSED::#OFF YUSED::0 " ; inst "u0/u2/TickCount<0>" "SLICEL",placed CLB_X8Y4 SLICE_X14Y6 , cfg " BXINV::#OFF BYINV::BY_B CEINV::#OFF CLKINV::CLK COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DXMUX::#OFF DYMUX::0 F::#OFF F5USED::#OFF FFX::#OFF FFX_INIT_ATTR::#OFF FFX_SR_ATTR::#OFF FFY:u0/u2/TickCount_0:#FF FFY_INIT_ATTR::INIT0 FFY_SR_ATTR::SRLOW FXMUX::#OFF FXUSED::#OFF G::#OFF GYMUX::#OFF REVUSED::#OFF SRINV::SR SYNC_ATTR::ASYNC XBUSED::#OFF XUSED::#OFF YBUSED::#OFF YUSED::#OFF " ; inst "u1/Done_Wait20" "SLICEL",placed CLB_X13Y10 SLICE_X16Y19 , cfg " BXINV::#OFF BYINV::#OFF CEINV::#OFF CLKINV::#OFF COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DXMUX::#OFF DYMUX::#OFF F:u1/Done_Wait20:#LUT:D=(A3*A1) F5USED::#OFF FFX::#OFF FFX_INIT_ATTR::#OFF FFX_SR_ATTR::#OFF FFY::#OFF FFY_INIT_ATTR::#OFF FFY_SR_ATTR::#OFF FXMUX::F FXUSED::#OFF G:u1/g2/count_not00031:#LUT:D=((~A1*A3)+~A2) GYMUX::G REVUSED::#OFF SRINV::#OFF SYNC_ATTR::#OFF XBUSED::#OFF XUSED::0 YBUSED::#OFF YUSED::0 " ; inst "u7/iRst_out_inv_shift2" "SLICEL",placed CLB_X1Y12 SLICE_X1Y22 , cfg " BXINV::BX BYINV::BY CEINV::CE CLKINV::CLK COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DXMUX::0 DYMUX::0 F::#OFF F5USED::#OFF FFX:u7/iRst_out_inv_shift2:#FF FFX_INIT_ATTR::INIT0 FFX_SR_ATTR::SRLOW FFY:u7/iRst_out_inv_shift1:#FF FFY_INIT_ATTR::INIT0 FFY_SR_ATTR::SRLOW FXMUX::#OFF FXUSED::#OFF G::#OFF GYMUX::#OFF REVUSED::#OFF SRINV::SR SYNC_ATTR::ASYNC XBUSED::#OFF XUSED::#OFF YBUSED::#OFF YUSED::#OFF " ; inst "u7/iRst_out_inv_shift4" "SLICEL",placed CLB_X1Y12 SLICE_X0Y22 , cfg " BXINV::BX BYINV::BY CEINV::CE CLKINV::CLK COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DXMUX::0 DYMUX::0 F::#OFF F5USED::#OFF FFX:u7/iRst_out_inv_shift4:#FF FFX_INIT_ATTR::INIT0 FFX_SR_ATTR::SRLOW FFY:u7/iRst_out_inv_shift3:#FF FFY_INIT_ATTR::INIT0 FFY_SR_ATTR::SRLOW FXMUX::#OFF FXUSED::#OFF G::#OFF GYMUX::#OFF REVUSED::#OFF SRINV::SR SYNC_ATTR::ASYNC XBUSED::#OFF XUSED::#OFF YBUSED::#OFF YUSED::#OFF " ; inst "u7/iRst_out_inv_shift6" "SLICEL",placed CLB_X1Y12 SLICE_X0Y23 , cfg " BXINV::BX BYINV::BY CEINV::CE CLKINV::CLK COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DXMUX::0 DYMUX::0 F::#OFF F5USED::#OFF FFX:u7/iRst_out_inv_shift6:#FF FFX_INIT_ATTR::INIT0 FFX_SR_ATTR::SRLOW FFY:u7/iRst_out_inv_shift5:#FF FFY_INIT_ATTR::INIT0 FFY_SR_ATTR::SRLOW FXMUX::#OFF FXUSED::#OFF G::#OFF GYMUX::#OFF REVUSED::#OFF SRINV::SR SYNC_ATTR::ASYNC XBUSED::#OFF XUSED::#OFF YBUSED::#OFF YUSED::#OFF " ; inst "u7/iRst_out_inv_shift8" "SLICEL",placed CLB_X1Y13 SLICE_X1Y25 , cfg " BXINV::BX BYINV::BY CEINV::CE CLKINV::CLK COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DXMUX::0 DYMUX::0 F::#OFF F5USED::#OFF FFX:u7/iRst_out_inv_shift8:#FF FFX_INIT_ATTR::INIT0 FFX_SR_ATTR::SRLOW FFY:u7/iRst_out_inv_shift7:#FF FFY_INIT_ATTR::INIT0 FFY_SR_ATTR::SRLOW FXMUX::#OFF FXUSED::#OFF G::#OFF GYMUX::#OFF REVUSED::#OFF SRINV::SR SYNC_ATTR::ASYNC XBUSED::#OFF XUSED::#OFF YBUSED::#OFF YUSED::#OFF " ; inst "u7/iRst_out_inv_shift10" "SLICEL",placed CLB_X1Y13 SLICE_X1Y24 , cfg " BXINV::BX BYINV::BY CEINV::CE CLKINV::CLK COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DXMUX::0 DYMUX::0 F::#OFF F5USED::#OFF FFX:u7/iRst_out_inv_shift10:#FF FFX_INIT_ATTR::INIT0 FFX_SR_ATTR::SRLOW FFY:u7/iRst_out_inv_shift9:#FF FFY_INIT_ATTR::INIT0 FFY_SR_ATTR::SRLOW FXMUX::#OFF FXUSED::#OFF G::#OFF GYMUX::#OFF REVUSED::#OFF SRINV::SR SYNC_ATTR::ASYNC XBUSED::#OFF XUSED::#OFF YBUSED::#OFF YUSED::#OFF " ; inst "u0/u2/u2/count<0>" "SLICEL",placed CLB_X13Y1 SLICE_X16Y0 , cfg " BXINV::BX_B BYINV::#OFF CEINV::CE CLKINV::CLK COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DXMUX::0 DYMUX::1 F:u0/u2/u2/En_int1:#LUT:D=(~A3+(~A1+(~A2+~A4))) F5USED::#OFF FFX:u0/u2/u2/count_0:#FF FFX_INIT_ATTR::INIT0 FFX_SR_ATTR::SRLOW FFY:u0/u2/u2/count_1:#FF FFY_INIT_ATTR::INIT0 FFY_SR_ATTR::SRLOW FXMUX::F FXUSED::#OFF G:u0/u2/Result<1>11:#LUT:D=(A2@A4) GYMUX::G REVUSED::#OFF SRINV::#OFF SYNC_ATTR::SYNC XBUSED::#OFF XUSED::0 YBUSED::#OFF YUSED::#OFF " ; inst "u1/p7/u2/u1/Q_int" "SLICEL",placed CLB_X6Y3 SLICE_X11Y4 , cfg " BXINV::#OFF BYINV::BY CEINV::#OFF CLKINV::CLK_B COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DXMUX::#OFF DYMUX::0 F::#OFF F5USED::#OFF FFX::#OFF FFX_INIT_ATTR::#OFF FFX_SR_ATTR::#OFF FFY:u1/p7/u2/u1/Q_int:#FF FFY_INIT_ATTR::INIT0 FFY_SR_ATTR::SRLOW FXMUX::#OFF FXUSED::#OFF G::#OFF GYMUX::#OFF REVUSED::#OFF SRINV::SR SYNC_ATTR::SYNC XBUSED::#OFF XUSED::#OFF YBUSED::#OFF YUSED::#OFF " ; inst "u9/u5/Q_int" "SLICEL",placed CLB_X4Y11 SLICE_X6Y21 , cfg " BXINV::#OFF BYINV::BY_B CEINV::#OFF CLKINV::CLK_B COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DXMUX::#OFF DYMUX::0 F::#OFF F5USED::#OFF FFX::#OFF FFX_INIT_ATTR::#OFF FFX_SR_ATTR::#OFF FFY:u9/u5/Q_int:#FF FFY_INIT_ATTR::INIT0 FFY_SR_ATTR::SRLOW FXMUX::#OFF FXUSED::#OFF G::#OFF GYMUX::#OFF REVUSED::#OFF SRINV::SR SYNC_ATTR::SYNC XBUSED::#OFF XUSED::#OFF YBUSED::#OFF YUSED::#OFF " ; inst "u1/p7/En" "SLICEL",placed CLB_X14Y4 SLICE_X18Y7 , cfg " BXINV::BX BYINV::BY CEINV::#OFF CLKINV::CLK COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DXMUX::0 DYMUX::#OFF F::#OFF F5USED::#OFF FFX:u1/p7/En:#FF FFX_INIT_ATTR::INIT0 FFX_SR_ATTR::SRLOW FFY::#OFF FFY_INIT_ATTR::#OFF FFY_SR_ATTR::#OFF FXMUX::#OFF FXUSED::#OFF G::#OFF GYMUX::#OFF REVUSED::0 SRINV::SR SYNC_ATTR::ASYNC XBUSED::#OFF XUSED::#OFF YBUSED::#OFF YUSED::#OFF " ; inst "u1/p5/count_not0001" "SLICEL",placed CLB_X16Y8 SLICE_X23Y14 , cfg " BXINV::#OFF BYINV::#OFF CEINV::#OFF CLKINV::#OFF COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DXMUX::#OFF DYMUX::#OFF F:u1/p5/count_not000123:#LUT:D=(A2+(A1+A3)) F5USED::#OFF FFX::#OFF FFX_INIT_ATTR::#OFF FFX_SR_ATTR::#OFF FFY::#OFF FFY_INIT_ATTR::#OFF FFY_SR_ATTR::#OFF FXMUX::F FXUSED::#OFF G:u1/p5/count_not000114:#LUT:D=(A2+(A4+(A1+A3))) GYMUX::G REVUSED::#OFF SRINV::#OFF SYNC_ATTR::#OFF XBUSED::#OFF XUSED::0 YBUSED::#OFF YUSED::0 " ; inst "u2/u4/Working" "SLICEL",placed CLB_X8Y11 SLICE_X15Y20 , cfg " BXINV::BX BYINV::BY CEINV::CE CLKINV::CLK_B COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DXMUX::0 DYMUX::#OFF F::#OFF F5USED::#OFF FFX:u2/u4/Working:#FF FFX_INIT_ATTR::INIT0 FFX_SR_ATTR::SRLOW FFY::#OFF FFY_INIT_ATTR::#OFF FFY_SR_ATTR::#OFF FXMUX::#OFF FXUSED::#OFF G::#OFF GYMUX::#OFF REVUSED::0 SRINV::SR SYNC_ATTR::ASYNC XBUSED::#OFF XUSED::#OFF YBUSED::#OFF YUSED::#OFF " ; inst "u9/u2/SReg_16_and0000" "SLICEL",placed CLB_X3Y8 SLICE_X4Y15 , cfg " BXINV::#OFF BYINV::#OFF CEINV::#OFF CLKINV::#OFF COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DXMUX::#OFF DYMUX::#OFF F:u9/u2/SReg_16_and00001:#LUT:D=(~A2*(~A1*A3)) F5USED::#OFF FFX::#OFF FFX_INIT_ATTR::#OFF FFX_SR_ATTR::#OFF FFY::#OFF FFY_INIT_ATTR::#OFF FFY_SR_ATTR::#OFF FXMUX::F FXUSED::#OFF G:u9/u2/SReg_16_or00001:#LUT:D=((~A2*(~A3+(A4+A1)))+(A2*A4)) GYMUX::G REVUSED::#OFF SRINV::#OFF SYNC_ATTR::#OFF XBUSED::#OFF XUSED::0 YBUSED::#OFF YUSED::0 " ; inst "u1/Done_p0" "SLICEL",placed CLB_X16Y2 SLICE_X22Y3 , cfg " BXINV::#OFF BYINV::#OFF CEINV::#OFF CLKINV::#OFF COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DXMUX::#OFF DYMUX::#OFF F::#OFF F5USED::#OFF FFX::#OFF FFX_INIT_ATTR::#OFF FFX_SR_ATTR::#OFF FFY::#OFF FFY_INIT_ATTR::#OFF FFY_SR_ATTR::#OFF FXMUX::#OFF FXUSED::#OFF G:u1/p0/En1:#LUT:D=(~A2*(~A3*A4)) GYMUX::G REVUSED::#OFF SRINV::#OFF SYNC_ATTR::#OFF XBUSED::#OFF XUSED::#OFF YBUSED::#OFF YUSED::0 " ; inst "u1/m2/m2/aH/Working" "SLICEL",placed CLB_X6Y1 SLICE_X10Y1 , cfg " BXINV::BX BYINV::BY CEINV::CE CLKINV::CLK_B COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DXMUX::0 DYMUX::#OFF F::#OFF F5USED::#OFF FFX:u1/m2/m2/aH/Working:#FF FFX_INIT_ATTR::INIT0 FFX_SR_ATTR::SRLOW FFY::#OFF FFY_INIT_ATTR::#OFF FFY_SR_ATTR::#OFF FXMUX::#OFF FXUSED::#OFF G::#OFF GYMUX::#OFF REVUSED::0 SRINV::SR SYNC_ATTR::ASYNC XBUSED::#OFF XUSED::#OFF YBUSED::#OFF YUSED::#OFF " ; inst "u1/m4/m2/u1/Q" "SLICEL",placed CLB_X1Y2 SLICE_X1Y3 , cfg " BXINV::#OFF BYINV::BY CEINV::#OFF CLKINV::CLK COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DXMUX::#OFF DYMUX::0 F::#OFF F5USED::#OFF FFX::#OFF FFX_INIT_ATTR::#OFF FFX_SR_ATTR::#OFF FFY:u1/m4/m2/u1/Q:#FF FFY_INIT_ATTR::INIT0 FFY_SR_ATTR::SRLOW FXMUX::#OFF FXUSED::#OFF G::#OFF GYMUX::#OFF REVUSED::#OFF SRINV::#OFF SYNC_ATTR::ASYNC XBUSED::#OFF XUSED::#OFF YBUSED::#OFF YUSED::#OFF " ; inst "u7/iRst_out_inv_shift12" "SLICEL",placed CLB_X1Y14 SLICE_X0Y26 , cfg " BXINV::BX BYINV::BY CEINV::CE CLKINV::CLK COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DXMUX::0 DYMUX::0 F::#OFF F5USED::#OFF FFX:u7/iRst_out_inv_shift12:#FF FFX_INIT_ATTR::INIT0 FFX_SR_ATTR::SRLOW FFY:u7/iRst_out_inv_shift11:#FF FFY_INIT_ATTR::INIT0 FFY_SR_ATTR::SRLOW FXMUX::#OFF FXUSED::#OFF G::#OFF GYMUX::#OFF REVUSED::#OFF SRINV::SR SYNC_ATTR::ASYNC XBUSED::#OFF XUSED::#OFF YBUSED::#OFF YUSED::#OFF " ; inst "u2/ReadCount<1>" "SLICEL",placed CLB_X6Y11 SLICE_X11Y20 , cfg " BXINV::#OFF BYINV::BY_B CEINV::CE CLKINV::CLK COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DXMUX::1 DYMUX::0 F:u2/Mcount_ReadCount_xor<1>11:#LUT:D=(A4@A2) F5USED::#OFF FFX:u2/ReadCount_1:#FF FFX_INIT_ATTR::INIT0 FFX_SR_ATTR::SRLOW FFY:u2/ReadCount_0:#FF FFY_INIT_ATTR::INIT1 FFY_SR_ATTR::SRHIGH FXMUX::F FXUSED::#OFF G:u2/Go1_SW0:#LUT:D=(A2*A4) GYMUX::G REVUSED::#OFF SRINV::SR SYNC_ATTR::ASYNC XBUSED::#OFF XUSED::#OFF YBUSED::#OFF YUSED::0 " ; inst "u1/m1/En_and0000" "SLICEL",placed CLB_X13Y2 SLICE_X16Y2 , cfg " BXINV::#OFF BYINV::#OFF CEINV::#OFF CLKINV::#OFF COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DXMUX::#OFF DYMUX::#OFF F:u1/m1/En_and00001:#LUT:D=(A4*A2) F5USED::#OFF FFX::#OFF FFX_INIT_ATTR::#OFF FFX_SR_ATTR::#OFF FFY::#OFF FFY_INIT_ATTR::#OFF FFY_SR_ATTR::#OFF FXMUX::F FXUSED::#OFF G:u1/g3/u3/En_and00001:#LUT:D=(A2*A4) GYMUX::G REVUSED::#OFF SRINV::#OFF SYNC_ATTR::#OFF XBUSED::#OFF XUSED::0 YBUSED::#OFF YUSED::0 " ; inst "u1/m6/b1/En_and0000" "SLICEL",placed CLB_X6Y7 SLICE_X11Y13 , cfg " BXINV::#OFF BYINV::#OFF CEINV::#OFF CLKINV::#OFF COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DXMUX::#OFF DYMUX::#OFF F:u1/m6/b1/En_and00001:#LUT:D=(A4*A2) F5USED::#OFF FFX::#OFF FFX_INIT_ATTR::#OFF FFX_SR_ATTR::#OFF FFY::#OFF FFY_INIT_ATTR::#OFF FFY_SR_ATTR::#OFF FXMUX::F FXUSED::#OFF G:u2/u3/u1/En_and00001:#LUT:D=(A4*A2) GYMUX::G REVUSED::#OFF SRINV::#OFF SYNC_ATTR::#OFF XBUSED::#OFF XUSED::0 YBUSED::#OFF YUSED::0 " ; inst "u1/m2/m2/aL/Working" "SLICEL",placed CLB_X5Y1 SLICE_X8Y1 , cfg " BXINV::BX BYINV::BY CEINV::CE CLKINV::CLK_B COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DXMUX::0 DYMUX::#OFF F::#OFF F5USED::#OFF FFX:u1/m2/m2/aL/Working:#FF FFX_INIT_ATTR::INIT0 FFX_SR_ATTR::SRLOW FFY::#OFF FFY_INIT_ATTR::#OFF FFY_SR_ATTR::#OFF FXMUX::#OFF FXUSED::#OFF G::#OFF GYMUX::#OFF REVUSED::0 SRINV::SR SYNC_ATTR::ASYNC XBUSED::#OFF XUSED::#OFF YBUSED::#OFF YUSED::#OFF " ; inst "u7/u8/Addr_mem<1>" "SLICEL",placed CLB_X4Y14 SLICE_X6Y26 , cfg " BXINV::BX BYINV::BY CEINV::CE CLKINV::CLK COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DXMUX::0 DYMUX::0 F::#OFF F5USED::#OFF FFX:u7/u8/Addr_mem_1:#FF FFX_INIT_ATTR::INIT0 FFX_SR_ATTR::SRLOW FFY:u7/u8/Addr_mem_0:#FF FFY_INIT_ATTR::INIT0 FFY_SR_ATTR::SRLOW FXMUX::#OFF FXUSED::#OFF G::#OFF GYMUX::#OFF REVUSED::#OFF SRINV::SR SYNC_ATTR::ASYNC XBUSED::#OFF XUSED::#OFF YBUSED::#OFF YUSED::#OFF " ; inst "u7/u8/Addr_mem<2>" "SLICEL",placed CLB_X4Y14 SLICE_X6Y27 , cfg " BXINV::#OFF BYINV::BY CEINV::CE CLKINV::CLK COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DXMUX::#OFF DYMUX::0 F::#OFF F5USED::#OFF FFX::#OFF FFX_INIT_ATTR::#OFF FFX_SR_ATTR::#OFF FFY:u7/u8/Addr_mem_2:#FF FFY_INIT_ATTR::INIT0 FFY_SR_ATTR::SRLOW FXMUX::#OFF FXUSED::#OFF G::#OFF GYMUX::#OFF REVUSED::#OFF SRINV::SR SYNC_ATTR::ASYNC XBUSED::#OFF XUSED::#OFF YBUSED::#OFF YUSED::#OFF " ; inst "u1/m6/m/m2/aH/Working" "SLICEL",placed CLB_X5Y3 SLICE_X9Y4 , cfg " BXINV::BX BYINV::BY CEINV::CE CLKINV::CLK_B COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DXMUX::0 DYMUX::#OFF F::#OFF F5USED::#OFF FFX:u1/m6/m/m2/aH/Working:#FF FFX_INIT_ATTR::INIT0 FFX_SR_ATTR::SRLOW FFY::#OFF FFY_INIT_ATTR::#OFF FFY_SR_ATTR::#OFF FXMUX::#OFF FXUSED::#OFF G::#OFF GYMUX::#OFF REVUSED::0 SRINV::SR SYNC_ATTR::ASYNC XBUSED::#OFF XUSED::#OFF YBUSED::#OFF YUSED::#OFF " ; inst "u1/p4/count<0>" "SLICEL",placed CLB_X15Y5 SLICE_X20Y9 , cfg " BXINV::#OFF BYINV::#OFF CEINV::#OFF CLKINV::CLK COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DXMUX::1 DYMUX::#OFF F:u1/p4/Mcount_count_eqn_01:#LUT:D=((~A1*(A2+A4))+(A1*A3)) F5USED::#OFF FFX:u1/p4/count_0:#FF FFX_INIT_ATTR::INIT0 FFX_SR_ATTR::SRLOW FFY::#OFF FFY_INIT_ATTR::#OFF FFY_SR_ATTR::#OFF FXMUX::F FXUSED::#OFF G:u1/p2/En1:#LUT:D=(~A2*((~A1+(A1*A3))*A4)) GYMUX::G REVUSED::#OFF SRINV::SR SYNC_ATTR::ASYNC XBUSED::#OFF XUSED::#OFF YBUSED::#OFF YUSED::0 " ; inst "u1/p4/count_not0001" "SLICEL",placed CLB_X15Y5 SLICE_X20Y8 , cfg " BXINV::#OFF BYINV::#OFF CEINV::#OFF CLKINV::#OFF COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DXMUX::#OFF DYMUX::#OFF F:u1/p4/count_not000123:#LUT:D=(A1+(A3+A4)) F5USED::#OFF FFX::#OFF FFX_INIT_ATTR::#OFF FFX_SR_ATTR::#OFF FFY::#OFF FFY_INIT_ATTR::#OFF FFY_SR_ATTR::#OFF FXMUX::F FXUSED::#OFF G:u1/p4/count_not000114:#LUT:D=(A1+(A2+(A4+A3))) GYMUX::G REVUSED::#OFF SRINV::#OFF SYNC_ATTR::#OFF XBUSED::#OFF XUSED::0 YBUSED::#OFF YUSED::0 " ; inst "u5/u1/Q" "SLICEL",placed CLB_X16Y13 SLICE_X23Y25 , cfg " BXINV::#OFF BYINV::BY CEINV::#OFF CLKINV::CLK COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DXMUX::#OFF DYMUX::0 F::#OFF F5USED::#OFF FFX::#OFF FFX_INIT_ATTR::#OFF FFX_SR_ATTR::#OFF FFY:u5/u1/Q:#FF FFY_INIT_ATTR::INIT0 FFY_SR_ATTR::SRLOW FXMUX::#OFF FXUSED::#OFF G::#OFF GYMUX::#OFF REVUSED::#OFF SRINV::#OFF SYNC_ATTR::ASYNC XBUSED::#OFF XUSED::#OFF YBUSED::#OFF YUSED::#OFF " ; inst "u1/m6/m/m2/aL/Working" "SLICEL",placed CLB_X5Y3 SLICE_X8Y4 , cfg " BXINV::BX BYINV::BY CEINV::CE CLKINV::CLK_B COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DXMUX::0 DYMUX::#OFF F::#OFF F5USED::#OFF FFX:u1/m6/m/m2/aL/Working:#FF FFX_INIT_ATTR::INIT0 FFX_SR_ATTR::SRLOW FFY::#OFF FFY_INIT_ATTR::#OFF FFY_SR_ATTR::#OFF FXMUX::#OFF FXUSED::#OFF G::#OFF GYMUX::#OFF REVUSED::0 SRINV::SR SYNC_ATTR::ASYNC XBUSED::#OFF XUSED::#OFF YBUSED::#OFF YUSED::#OFF " ; inst "u1/Done_p2" "SLICEL",placed CLB_X15Y4 SLICE_X21Y7 , cfg " BXINV::#OFF BYINV::#OFF CEINV::#OFF CLKINV::#OFF COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DXMUX::#OFF DYMUX::#OFF F::#OFF F5USED::#OFF FFX::#OFF FFX_INIT_ATTR::#OFF FFX_SR_ATTR::#OFF FFY::#OFF FFY_INIT_ATTR::#OFF FFY_SR_ATTR::#OFF FXMUX::#OFF FXUSED::#OFF G:u1/p3/En1:#LUT:D=(~A1*(~A2*A4)) GYMUX::G REVUSED::#OFF SRINV::#OFF SYNC_ATTR::#OFF XBUSED::#OFF XUSED::#OFF YBUSED::#OFF YUSED::0 " ; inst "u1/m6/b1/u1/Q_int" "SLICEL",placed CLB_X5Y4 SLICE_X9Y7 , cfg " BXINV::#OFF BYINV::#OFF CEINV::#OFF CLKINV::CLK_B COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DXMUX::1 DYMUX::#OFF F:u1/m6/Go_Byte111:#LUT:D=(((~A2*A1)+A2)*A4) F5USED::#OFF FFX:u1/m6/b1/u1/Q_int:#FF FFX_INIT_ATTR::INIT1 FFX_SR_ATTR::SRHIGH FFY::#OFF FFY_INIT_ATTR::#OFF FFY_SR_ATTR::#OFF FXMUX::F FXUSED::#OFF G:u1/m6/m/m3/En1:#LUT:D=(~A2*(A1*~A3)) GYMUX::G REVUSED::#OFF SRINV::SR SYNC_ATTR::SYNC XBUSED::#OFF XUSED::#OFF YBUSED::#OFF YUSED::0 " ; inst "u1/m6/b2/En_and0000" "SLICEL",placed CLB_X4Y7 SLICE_X6Y13 , cfg " BXINV::#OFF BYINV::#OFF CEINV::#OFF CLKINV::#OFF COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DXMUX::#OFF DYMUX::#OFF F:u1/m6/b2/En_and00001:#LUT:D=(A4*A3) F5USED::#OFF FFX::#OFF FFX_INIT_ATTR::#OFF FFX_SR_ATTR::#OFF FFY::#OFF FFY_INIT_ATTR::#OFF FFY_SR_ATTR::#OFF FXMUX::F FXUSED::#OFF G:u8/l1/En_and00001:#LUT:D=(A2*A3) GYMUX::G REVUSED::#OFF SRINV::#OFF SYNC_ATTR::#OFF XBUSED::#OFF XUSED::0 YBUSED::#OFF YUSED::0 " ; inst "u9/u2/SReg<11>" "SLICEL",placed CLB_X2Y5 SLICE_X2Y8 , cfg " BXINV::BX BYINV::BY CEINV::#OFF CLKINV::CLK COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DXMUX::0 DYMUX::1 F::#OFF F5USED::#OFF FFX:u9/u2/SReg_11:#FF FFX_INIT_ATTR::INIT0 FFX_SR_ATTR::SRLOW FFY:u9/u2/SReg_10:#FF FFY_INIT_ATTR::INIT0 FFY_SR_ATTR::SRLOW FXMUX::#OFF FXUSED::#OFF G:u9/u2/SReg<9>_rt:#LUT:D=A2 _BEL_PROP::G:PK_PACKTHRU: GYMUX::G REVUSED::0 SRINV::SR SYNC_ATTR::ASYNC XBUSED::#OFF XUSED::#OFF YBUSED::#OFF YUSED::#OFF " ; inst "u6/u1/Q" "SLICEL",placed CLB_X13Y12 SLICE_X16Y23 , cfg " BXINV::#OFF BYINV::BY CEINV::#OFF CLKINV::CLK COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DXMUX::#OFF DYMUX::0 F::#OFF F5USED::#OFF FFX::#OFF FFX_INIT_ATTR::#OFF FFX_SR_ATTR::#OFF FFY:u6/u1/Q:#FF FFY_INIT_ATTR::INIT0 FFY_SR_ATTR::SRLOW FXMUX::#OFF FXUSED::#OFF G::#OFF GYMUX::#OFF REVUSED::#OFF SRINV::#OFF SYNC_ATTR::ASYNC XBUSED::#OFF XUSED::#OFF YBUSED::#OFF YUSED::#OFF " ; inst "u9/u2/SReg<13>" "SLICEL",placed CLB_X2Y5 SLICE_X2Y9 , cfg " BXINV::BX BYINV::BY CEINV::#OFF CLKINV::CLK COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DXMUX::0 DYMUX::1 F::#OFF F5USED::#OFF FFX:u9/u2/SReg_13:#FF FFX_INIT_ATTR::INIT0 FFX_SR_ATTR::SRLOW FFY:u9/u2/SReg_12:#FF FFY_INIT_ATTR::INIT0 FFY_SR_ATTR::SRLOW FXMUX::#OFF FXUSED::#OFF G:u9/u2/SReg<11>_rt:#LUT:D=A1 _BEL_PROP::G:PK_PACKTHRU: GYMUX::G REVUSED::0 SRINV::SR SYNC_ATTR::ASYNC XBUSED::#OFF XUSED::#OFF YBUSED::#OFF YUSED::#OFF " ; inst "u9/u2/SReg<14>" "SLICEL",placed CLB_X2Y6 SLICE_X2Y11 , cfg " BXINV::BX BYINV::BY CEINV::#OFF CLKINV::CLK COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DXMUX::0 DYMUX::#OFF F::#OFF F5USED::#OFF FFX:u9/u2/SReg_14:#FF FFX_INIT_ATTR::INIT0 FFX_SR_ATTR::SRLOW FFY::#OFF FFY_INIT_ATTR::#OFF FFY_SR_ATTR::#OFF FXMUX::#OFF FXUSED::#OFF G::#OFF GYMUX::#OFF REVUSED::0 SRINV::SR SYNC_ATTR::ASYNC XBUSED::#OFF XUSED::#OFF YBUSED::#OFF YUSED::#OFF " ; inst "u9/u2/SReg<15>" "SLICEL",placed CLB_X1Y6 SLICE_X1Y11 , cfg " BXINV::BX BYINV::BY CEINV::#OFF CLKINV::CLK COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DXMUX::0 DYMUX::#OFF F::#OFF F5USED::#OFF FFX:u9/u2/SReg_15:#FF FFX_INIT_ATTR::INIT0 FFX_SR_ATTR::SRLOW FFY::#OFF FFY_INIT_ATTR::#OFF FFY_SR_ATTR::#OFF FXMUX::#OFF FXUSED::#OFF G::#OFF GYMUX::#OFF REVUSED::0 SRINV::SR SYNC_ATTR::ASYNC XBUSED::#OFF XUSED::#OFF YBUSED::#OFF YUSED::#OFF " ; inst "u9/u2/SReg<16>" "SLICEL",placed CLB_X3Y8 SLICE_X5Y14 , cfg " BXINV::BX BYINV::BY CEINV::#OFF CLKINV::CLK COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DXMUX::0 DYMUX::#OFF F::#OFF F5USED::#OFF FFX:u9/u2/SReg_16:#FF FFX_INIT_ATTR::INIT0 FFX_SR_ATTR::SRLOW FFY::#OFF FFY_INIT_ATTR::#OFF FFY_SR_ATTR::#OFF FXMUX::#OFF FXUSED::#OFF G::#OFF GYMUX::#OFF REVUSED::0 SRINV::SR SYNC_ATTR::ASYNC XBUSED::#OFF XUSED::#OFF YBUSED::#OFF YUSED::#OFF " ; inst "u9/u2/SReg<17>" "SLICEL",placed CLB_X4Y8 SLICE_X7Y14 , cfg " BXINV::BX BYINV::BY CEINV::#OFF CLKINV::CLK COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DXMUX::0 DYMUX::#OFF F::#OFF F5USED::#OFF FFX:u9/u2/SReg_17:#FF FFX_INIT_ATTR::INIT0 FFX_SR_ATTR::SRLOW FFY::#OFF FFY_INIT_ATTR::#OFF FFY_SR_ATTR::#OFF FXMUX::#OFF FXUSED::#OFF G::#OFF GYMUX::#OFF REVUSED::0 SRINV::SR SYNC_ATTR::ASYNC XBUSED::#OFF XUSED::#OFF YBUSED::#OFF YUSED::#OFF " ; inst "u9/u2/SReg<18>" "SLICEL",placed CLB_X7Y11 SLICE_X12Y20 , cfg " BXINV::BX BYINV::BY CEINV::#OFF CLKINV::CLK COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DXMUX::0 DYMUX::#OFF F::#OFF F5USED::#OFF FFX:u9/u2/SReg_18:#FF FFX_INIT_ATTR::INIT0 FFX_SR_ATTR::SRLOW FFY::#OFF FFY_INIT_ATTR::#OFF FFY_SR_ATTR::#OFF FXMUX::#OFF FXUSED::#OFF G::#OFF GYMUX::#OFF REVUSED::0 SRINV::SR SYNC_ATTR::ASYNC XBUSED::#OFF XUSED::#OFF YBUSED::#OFF YUSED::#OFF " ; inst "u6/u4/Q" "SLICEL",placed CLB_X8Y12 SLICE_X14Y23 , cfg " BXINV::#OFF BYINV::BY CEINV::#OFF CLKINV::CLK COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DXMUX::#OFF DYMUX::0 F::#OFF F5USED::#OFF FFX::#OFF FFX_INIT_ATTR::#OFF FFX_SR_ATTR::#OFF FFY:u6/u4/Q:#FF FFY_INIT_ATTR::INIT0 FFY_SR_ATTR::SRLOW FXMUX::#OFF FXUSED::#OFF G::#OFF GYMUX::#OFF REVUSED::#OFF SRINV::#OFF SYNC_ATTR::ASYNC XBUSED::#OFF XUSED::#OFF YBUSED::#OFF YUSED::#OFF _GND_SOURCE::X " ; inst "u2/u1/Qb" "SLICEL",placed CLB_X8Y10 SLICE_X15Y18 , cfg " BXINV::#OFF BYINV::BY CEINV::#OFF CLKINV::CLK COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DXMUX::#OFF DYMUX::0 F::#OFF F5USED::#OFF FFX::#OFF FFX_INIT_ATTR::#OFF FFX_SR_ATTR::#OFF FFY:u2/u1/Qb:#FF FFY_INIT_ATTR::INIT0 FFY_SR_ATTR::SRLOW FXMUX::#OFF FXUSED::#OFF G::#OFF GYMUX::#OFF REVUSED::#OFF SRINV::#OFF SYNC_ATTR::ASYNC XBUSED::#OFF XUSED::#OFF YBUSED::#OFF YUSED::#OFF " ; inst "u1/InitDelay<0>" "SLICEL",placed CLB_X15Y11 SLICE_X21Y21 , cfg " BXINV::BX_B BYINV::#OFF CEINV::CE_B CLKINV::CLK COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DXMUX::0 DYMUX::1 F::#OFF F5USED::#OFF FFX:u1/InitDelay_0:#FF FFX_INIT_ATTR::INIT0 FFX_SR_ATTR::SRLOW FFY:u1/InitDelay_1:#FF FFY_INIT_ATTR::INIT0 FFY_SR_ATTR::SRLOW FXMUX::#OFF FXUSED::#OFF G:u1/Mcount_InitDelay_xor<1>11:#LUT:D=(A4@A1) GYMUX::G REVUSED::#OFF SRINV::SR SYNC_ATTR::ASYNC XBUSED::#OFF XUSED::#OFF YBUSED::#OFF YUSED::#OFF " ; inst "u1/f3/Working" "SLICEL",placed CLB_X8Y5 SLICE_X14Y8 , cfg " BXINV::BX BYINV::BY CEINV::CE CLKINV::CLK_B COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DXMUX::0 DYMUX::#OFF F::#OFF F5USED::#OFF FFX:u1/f3/Working:#FF FFX_INIT_ATTR::INIT0 FFX_SR_ATTR::SRLOW FFY::#OFF FFY_INIT_ATTR::#OFF FFY_SR_ATTR::#OFF FXMUX::#OFF FXUSED::#OFF G::#OFF GYMUX::#OFF REVUSED::0 SRINV::SR SYNC_ATTR::ASYNC XBUSED::#OFF XUSED::#OFF YBUSED::#OFF YUSED::#OFF " ; inst "u1/p6b/Q" "SLICEL",placed CLB_X14Y7 SLICE_X19Y12 , cfg " BXINV::#OFF BYINV::BY CEINV::#OFF CLKINV::CLK COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DXMUX::#OFF DYMUX::0 F::#OFF F5USED::#OFF FFX::#OFF FFX_INIT_ATTR::#OFF FFX_SR_ATTR::#OFF FFY:u1/p6b/Q:#FF FFY_INIT_ATTR::INIT0 FFY_SR_ATTR::SRLOW FXMUX::#OFF FXUSED::#OFF G::#OFF GYMUX::#OFF REVUSED::#OFF SRINV::#OFF SYNC_ATTR::ASYNC XBUSED::#OFF XUSED::#OFF YBUSED::#OFF YUSED::#OFF " ; inst "N48" "SLICEL",placed CLB_X8Y6 SLICE_X15Y11 , cfg " BXINV::#OFF BYINV::#OFF CEINV::#OFF CLKINV::#OFF COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DXMUX::#OFF DYMUX::#OFF F:u1/f1/En1_SW1:#LUT:D=(~A2+(A4+A1)) F5USED::#OFF FFX::#OFF FFX_INIT_ATTR::#OFF FFX_SR_ATTR::#OFF FFY::#OFF FFY_INIT_ATTR::#OFF FFY_SR_ATTR::#OFF FXMUX::F FXUSED::#OFF G:u1/f1/En1_SW0:#LUT:D=(A1+((~A4*A2)+~A3)) GYMUX::G REVUSED::#OFF SRINV::#OFF SYNC_ATTR::#OFF XBUSED::#OFF XUSED::0 YBUSED::#OFF YUSED::0 " ; inst "u7/u2/Q" "SLICEL",placed CLB_X1Y13 SLICE_X0Y25 , cfg " BXINV::#OFF BYINV::BY CEINV::#OFF CLKINV::CLK COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DXMUX::#OFF DYMUX::0 F::#OFF F5USED::#OFF FFX::#OFF FFX_INIT_ATTR::#OFF FFX_SR_ATTR::#OFF FFY:u7/u2/Q:#FF FFY_INIT_ATTR::INIT0 FFY_SR_ATTR::SRLOW FXMUX::#OFF FXUSED::#OFF G::#OFF GYMUX::#OFF REVUSED::#OFF SRINV::#OFF SYNC_ATTR::ASYNC XBUSED::#OFF XUSED::#OFF YBUSED::#OFF YUSED::#OFF " ; inst "u1/m2/m3/Working" "SLICEL",placed CLB_X5Y1 SLICE_X9Y1 , cfg " BXINV::BX BYINV::BY CEINV::CE CLKINV::CLK_B COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DXMUX::0 DYMUX::#OFF F::#OFF F5USED::#OFF FFX:u1/m2/m3/Working:#FF FFX_INIT_ATTR::INIT0 FFX_SR_ATTR::SRLOW FFY::#OFF FFY_INIT_ATTR::#OFF FFY_SR_ATTR::#OFF FXMUX::#OFF FXUSED::#OFF G::#OFF GYMUX::#OFF REVUSED::0 SRINV::SR SYNC_ATTR::ASYNC XBUSED::#OFF XUSED::#OFF YBUSED::#OFF YUSED::#OFF " ; inst "u1/i1/Working" "SLICEL",placed CLB_X15Y3 SLICE_X21Y5 , cfg " BXINV::BX BYINV::BY CEINV::CE CLKINV::CLK_B COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DXMUX::0 DYMUX::#OFF F::#OFF F5USED::#OFF FFX:u1/i1/Working:#FF FFX_INIT_ATTR::INIT0 FFX_SR_ATTR::SRLOW FFY::#OFF FFY_INIT_ATTR::#OFF FFY_SR_ATTR::#OFF FXMUX::#OFF FXUSED::#OFF G::#OFF GYMUX::#OFF REVUSED::0 SRINV::SR SYNC_ATTR::ASYNC XBUSED::#OFF XUSED::#OFF YBUSED::#OFF YUSED::#OFF " ; inst "u7/u6/reg<14>" "SLICEL",placed CLB_X2Y14 SLICE_X2Y27 , cfg " BXINV::#OFF BYINV::BY CEINV::CE CLKINV::CLK COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DXMUX::#OFF DYMUX::0 F::#OFF F5USED::#OFF FFX::#OFF FFX_INIT_ATTR::#OFF FFX_SR_ATTR::#OFF FFY:u7/u6/reg_14:#FF FFY_INIT_ATTR::INIT0 FFY_SR_ATTR::SRLOW FXMUX::#OFF FXUSED::#OFF G::#OFF GYMUX::#OFF REVUSED::#OFF SRINV::SR SYNC_ATTR::ASYNC XBUSED::#OFF XUSED::#OFF YBUSED::#OFF YUSED::#OFF " ; inst "u1/p7/u2/En_and0000" "SLICEL",placed CLB_X6Y5 SLICE_X11Y9 , cfg " BXINV::#OFF BYINV::#OFF CEINV::#OFF CLKINV::#OFF COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DXMUX::#OFF DYMUX::#OFF F:u1/p7/u2/En_and00001:#LUT:D=(A4*A1) F5USED::#OFF FFX::#OFF FFX_INIT_ATTR::#OFF FFX_SR_ATTR::#OFF FFY::#OFF FFY_INIT_ATTR::#OFF FFY_SR_ATTR::#OFF FXMUX::F FXUSED::#OFF G:u8/l2/En_and00001:#LUT:D=(A1*A2) GYMUX::G REVUSED::#OFF SRINV::#OFF SYNC_ATTR::#OFF XBUSED::#OFF XUSED::0 YBUSED::#OFF YUSED::0 " ; inst "u4/u2/u2/En" "SLICEL",placed CLB_X15Y8 SLICE_X21Y15 , cfg " BXINV::BX BYINV::BY CEINV::#OFF CLKINV::CLK_B COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DXMUX::0 DYMUX::#OFF F::#OFF F5USED::#OFF FFX:u4/u2/u2/En:#FF FFX_INIT_ATTR::INIT0 FFX_SR_ATTR::SRLOW FFY::#OFF FFY_INIT_ATTR::#OFF FFY_SR_ATTR::#OFF FXMUX::#OFF FXUSED::#OFF G::#OFF GYMUX::#OFF REVUSED::0 SRINV::SR SYNC_ATTR::ASYNC XBUSED::#OFF XUSED::#OFF YBUSED::#OFF YUSED::#OFF " ; inst "u8/u2/Q" "SLICEL",placed CLB_X3Y9 SLICE_X5Y17 , cfg " BXINV::#OFF BYINV::BY CEINV::#OFF CLKINV::CLK COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DXMUX::#OFF DYMUX::0 F::#OFF F5USED::#OFF FFX::#OFF FFX_INIT_ATTR::#OFF FFX_SR_ATTR::#OFF FFY:u8/u2/Q:#FF FFY_INIT_ATTR::INIT0 FFY_SR_ATTR::SRLOW FXMUX::#OFF FXUSED::#OFF G::#OFF GYMUX::#OFF REVUSED::#OFF SRINV::#OFF SYNC_ATTR::ASYNC XBUSED::#OFF XUSED::#OFF YBUSED::#OFF YUSED::#OFF " ; inst "u4/u2/u1/Qa" "SLICEL",placed CLB_X14Y5 SLICE_X18Y8 , cfg " BXINV::#OFF BYINV::BY CEINV::#OFF CLKINV::CLK_B COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DXMUX::#OFF DYMUX::0 F::#OFF F5USED::#OFF FFX::#OFF FFX_INIT_ATTR::#OFF FFX_SR_ATTR::#OFF FFY:u4/u2/u1/Qa:#FF FFY_INIT_ATTR::INIT0 FFY_SR_ATTR::SRLOW FXMUX::#OFF FXUSED::#OFF G::#OFF GYMUX::#OFF REVUSED::#OFF SRINV::#OFF SYNC_ATTR::ASYNC XBUSED::#OFF XUSED::#OFF YBUSED::#OFF YUSED::#OFF " ; inst "u4/u2/u1/Qb" "SLICEL",placed CLB_X14Y5 SLICE_X19Y9 , cfg " BXINV::#OFF BYINV::BY CEINV::#OFF CLKINV::CLK COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DXMUX::#OFF DYMUX::0 F::#OFF F5USED::#OFF FFX::#OFF FFX_INIT_ATTR::#OFF FFX_SR_ATTR::#OFF FFY:u4/u2/u1/Qb:#FF FFY_INIT_ATTR::INIT0 FFY_SR_ATTR::SRLOW FXMUX::#OFF FXUSED::#OFF G::#OFF GYMUX::#OFF REVUSED::#OFF SRINV::#OFF SYNC_ATTR::ASYNC XBUSED::#OFF XUSED::#OFF YBUSED::#OFF YUSED::#OFF " ; inst "u1/m3/m3/Working" "SLICEL",placed CLB_X2Y2 SLICE_X2Y3 , cfg " BXINV::BX BYINV::BY CEINV::CE CLKINV::CLK_B COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DXMUX::0 DYMUX::#OFF F::#OFF F5USED::#OFF FFX:u1/m3/m3/Working:#FF FFX_INIT_ATTR::INIT0 FFX_SR_ATTR::SRLOW FFY::#OFF FFY_INIT_ATTR::#OFF FFY_SR_ATTR::#OFF FXMUX::#OFF FXUSED::#OFF G::#OFF GYMUX::#OFF REVUSED::0 SRINV::SR SYNC_ATTR::ASYNC XBUSED::#OFF XUSED::#OFF YBUSED::#OFF YUSED::#OFF " ; inst "u4/u2/u3/En" "SLICEL",placed CLB_X15Y12 SLICE_X21Y22 , cfg " BXINV::BX BYINV::BY CEINV::#OFF CLKINV::CLK_B COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DXMUX::0 DYMUX::#OFF F::#OFF F5USED::#OFF FFX:u4/u2/u3/En:#FF FFX_INIT_ATTR::INIT0 FFX_SR_ATTR::SRLOW FFY::#OFF FFY_INIT_ATTR::#OFF FFY_SR_ATTR::#OFF FXMUX::#OFF FXUSED::#OFF G::#OFF GYMUX::#OFF REVUSED::0 SRINV::SR SYNC_ATTR::ASYNC XBUSED::#OFF XUSED::#OFF YBUSED::#OFF YUSED::#OFF " ; inst "u1/g2/count<0>" "SLICEL",placed CLB_X13Y10 SLICE_X17Y19 , cfg " BXINV::BX_B BYINV::#OFF CEINV::CE CLKINV::CLK COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DXMUX::0 DYMUX::1 F:u1/Eth_iRst_or0000_inv2_SW0:#LUT:D=(A3+(A1+(A2+A4))) F5USED::#OFF FFX:u1/g2/count_0:#FF FFX_INIT_ATTR::INIT0 FFX_SR_ATTR::SRLOW FFY:u1/g2/count_1:#FF FFY_INIT_ATTR::INIT0 FFY_SR_ATTR::SRLOW FXMUX::F FXUSED::#OFF G:u1/g2/Mcount_count_xor<1>11:#LUT:D=(A1@A4) GYMUX::G REVUSED::#OFF SRINV::SR SYNC_ATTR::ASYNC XBUSED::#OFF XUSED::0 YBUSED::#OFF YUSED::#OFF " ; inst "u1/Done_ResCfg" "SLICEL",placed CLB_X14Y3 SLICE_X18Y4 , cfg " BXINV::#OFF BYINV::#OFF CEINV::#OFF CLKINV::#OFF COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DXMUX::#OFF DYMUX::#OFF F::#OFF F5USED::#OFF FFX::#OFF FFX_INIT_ATTR::#OFF FFX_SR_ATTR::#OFF FFY::#OFF FFY_INIT_ATTR::#OFF FFY_SR_ATTR::#OFF FXMUX::#OFF FXUSED::#OFF G:u1/p9/En1:#LUT:D=(~A3*((~A2+(A2*A4))*A1)) GYMUX::G REVUSED::#OFF SRINV::#OFF SYNC_ATTR::#OFF XBUSED::#OFF XUSED::#OFF YBUSED::#OFF YUSED::0 " ; inst "u9/u1/count<2>" "SLICEL",placed CLB_X1Y8 SLICE_X0Y14 , cfg " BXINV::#OFF BYINV::#OFF CEINV::#OFF CLKINV::CLK_B COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DXMUX::1 DYMUX::#OFF F:u9/u1/count_mux0003<2>1:#LUT:D=((~A3*(~A4*(A2+~A1)))+(A3*A4)) F5USED::#OFF FFX:u9/u1/count_2:#FF FFX_INIT_ATTR::INIT0 FFX_SR_ATTR::SRLOW FFY::#OFF FFY_INIT_ATTR::#OFF FFY_SR_ATTR::#OFF FXMUX::F FXUSED::#OFF G:u9/u1/count_mux0003<2>21:#LUT:D=(~A2+~A1) GYMUX::G REVUSED::#OFF SRINV::SR SYNC_ATTR::ASYNC XBUSED::#OFF XUSED::#OFF YBUSED::#OFF YUSED::0 " ; inst "u1/g3/u3/u1/Q_int" "SLICEL",placed CLB_X8Y4 SLICE_X14Y7 , cfg " BXINV::#OFF BYINV::BY CEINV::#OFF CLKINV::CLK_B COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DXMUX::#OFF DYMUX::0 F::#OFF F5USED::#OFF FFX::#OFF FFX_INIT_ATTR::#OFF FFX_SR_ATTR::#OFF FFY:u1/g3/u3/u1/Q_int:#FF FFY_INIT_ATTR::INIT0 FFY_SR_ATTR::SRLOW FXMUX::#OFF FXUSED::#OFF G::#OFF GYMUX::#OFF REVUSED::#OFF SRINV::#OFF SYNC_ATTR::ASYNC XBUSED::#OFF XUSED::#OFF YBUSED::#OFF YUSED::#OFF " ; inst "u8/l1/u1/Q_int" "SLICEL",placed CLB_X4Y8 SLICE_X7Y15 , cfg " BXINV::#OFF BYINV::BY CEINV::#OFF CLKINV::CLK_B COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DXMUX::#OFF DYMUX::0 F::#OFF F5USED::#OFF FFX::#OFF FFX_INIT_ATTR::#OFF FFX_SR_ATTR::#OFF FFY:u8/l1/u1/Q_int:#FF FFY_INIT_ATTR::INIT0 FFY_SR_ATTR::SRLOW FXMUX::#OFF FXUSED::#OFF G::#OFF GYMUX::#OFF REVUSED::#OFF SRINV::#OFF SYNC_ATTR::ASYNC XBUSED::#OFF XUSED::#OFF YBUSED::#OFF YUSED::#OFF " ; inst "u4/u2/u2/u1/Q" "SLICEL",placed CLB_X14Y6 SLICE_X18Y10 , cfg " BXINV::#OFF BYINV::BY CEINV::#OFF CLKINV::CLK COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DXMUX::#OFF DYMUX::0 F::#OFF F5USED::#OFF FFX::#OFF FFX_INIT_ATTR::#OFF FFX_SR_ATTR::#OFF FFY:u4/u2/u2/u1/Q:#FF FFY_INIT_ATTR::INIT0 FFY_SR_ATTR::SRLOW FXMUX::#OFF FXUSED::#OFF G::#OFF GYMUX::#OFF REVUSED::#OFF SRINV::#OFF SYNC_ATTR::ASYNC XBUSED::#OFF XUSED::#OFF YBUSED::#OFF YUSED::#OFF " ; inst "u1/m1/u1/Q" "SLICEL",placed CLB_X13Y2 SLICE_X16Y3 , cfg " BXINV::#OFF BYINV::BY CEINV::#OFF CLKINV::CLK COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DXMUX::#OFF DYMUX::0 F::#OFF F5USED::#OFF FFX::#OFF FFX_INIT_ATTR::#OFF FFX_SR_ATTR::#OFF FFY:u1/m1/u1/Q:#FF FFY_INIT_ATTR::INIT0 FFY_SR_ATTR::SRLOW FXMUX::#OFF FXUSED::#OFF G::#OFF GYMUX::#OFF REVUSED::#OFF SRINV::#OFF SYNC_ATTR::ASYNC XBUSED::#OFF XUSED::#OFF YBUSED::#OFF YUSED::#OFF " ; inst "u1/m4/m3/Working" "SLICEL",placed CLB_X1Y4 SLICE_X0Y6 , cfg " BXINV::BX BYINV::BY CEINV::CE CLKINV::CLK_B COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DXMUX::0 DYMUX::#OFF F::#OFF F5USED::#OFF FFX:u1/m4/m3/Working:#FF FFX_INIT_ATTR::INIT0 FFX_SR_ATTR::SRLOW FFY::#OFF FFY_INIT_ATTR::#OFF FFY_SR_ATTR::#OFF FXMUX::#OFF FXUSED::#OFF G::#OFF GYMUX::#OFF REVUSED::0 SRINV::SR SYNC_ATTR::ASYNC XBUSED::#OFF XUSED::#OFF YBUSED::#OFF YUSED::#OFF " ; inst "u1/p3/Working" "SLICEL",placed CLB_X15Y4 SLICE_X20Y6 , cfg " BXINV::BX BYINV::BY CEINV::CE CLKINV::CLK_B COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DXMUX::0 DYMUX::#OFF F::#OFF F5USED::#OFF FFX:u1/p3/Working:#FF FFX_INIT_ATTR::INIT0 FFX_SR_ATTR::SRLOW FFY::#OFF FFY_INIT_ATTR::#OFF FFY_SR_ATTR::#OFF FXMUX::#OFF FXUSED::#OFF G::#OFF GYMUX::#OFF REVUSED::0 SRINV::SR SYNC_ATTR::ASYNC XBUSED::#OFF XUSED::#OFF YBUSED::#OFF YUSED::#OFF " ; inst "u2/u3/u1/En" "SLICEL",placed CLB_X6Y10 SLICE_X10Y18 , cfg " BXINV::BX BYINV::BY CEINV::#OFF CLKINV::CLK_B COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DXMUX::0 DYMUX::#OFF F::#OFF F5USED::#OFF FFX:u2/u3/u1/En:#FF FFX_INIT_ATTR::INIT0 FFX_SR_ATTR::SRLOW FFY::#OFF FFY_INIT_ATTR::#OFF FFY_SR_ATTR::#OFF FXMUX::#OFF FXUSED::#OFF G::#OFF GYMUX::#OFF REVUSED::0 SRINV::SR SYNC_ATTR::ASYNC XBUSED::#OFF XUSED::#OFF YBUSED::#OFF YUSED::#OFF " ; inst "u1/m6/Done_FlashAddr" "SLICEL",placed CLB_X4Y3 SLICE_X6Y4 , cfg " BXINV::#OFF BYINV::#OFF CEINV::#OFF CLKINV::#OFF COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DXMUX::#OFF DYMUX::#OFF F:u1/m6/a1/aL/En1:#LUT:D=(~A4*((~A1+(A1*A3))*A2)) F5USED::#OFF FFX::#OFF FFX_INIT_ATTR::#OFF FFX_SR_ATTR::#OFF FFY::#OFF FFY_INIT_ATTR::#OFF FFY_SR_ATTR::#OFF FXMUX::F FXUSED::#OFF G:u1/m6/a1/aH/En1:#LUT:D=(~A3*(~A4*A1)) GYMUX::G REVUSED::#OFF SRINV::#OFF SYNC_ATTR::#OFF XBUSED::#OFF XUSED::0 YBUSED::#OFF YUSED::0 " ; inst "u9/u5/Q" "SLICEL",placed CLB_X6Y10 SLICE_X11Y18 , cfg " BXINV::#OFF BYINV::BY CEINV::#OFF CLKINV::CLK COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DXMUX::#OFF DYMUX::0 F::#OFF F5USED::#OFF FFX::#OFF FFX_INIT_ATTR::#OFF FFX_SR_ATTR::#OFF FFY:u9/u5/Q:#FF FFY_INIT_ATTR::INIT0 FFY_SR_ATTR::SRLOW FXMUX::#OFF FXUSED::#OFF G::#OFF GYMUX::#OFF REVUSED::#OFF SRINV::#OFF SYNC_ATTR::ASYNC XBUSED::#OFF XUSED::#OFF YBUSED::#OFF YUSED::#OFF " ; inst "u4/u2/u3/u1/Q_int" "SLICEL",placed CLB_X15Y9 SLICE_X20Y16 , cfg " BXINV::#OFF BYINV::BY CEINV::#OFF CLKINV::CLK_B COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DXMUX::#OFF DYMUX::0 F::#OFF F5USED::#OFF FFX::#OFF FFX_INIT_ATTR::#OFF FFX_SR_ATTR::#OFF FFY:u4/u2/u3/u1/Q_int:#FF FFY_INIT_ATTR::INIT0 FFY_SR_ATTR::SRLOW FXMUX::#OFF FXUSED::#OFF G::#OFF GYMUX::#OFF REVUSED::#OFF SRINV::#OFF SYNC_ATTR::ASYNC XBUSED::#OFF XUSED::#OFF YBUSED::#OFF YUSED::#OFF " ; inst "u9/u2/SReg_0_or0000" "SLICEL",placed CLB_X2Y7 SLICE_X3Y13 , cfg " BXINV::#OFF BYINV::#OFF CEINV::#OFF CLKINV::#OFF COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DXMUX::#OFF DYMUX::#OFF F:u9/u2/SReg_7_or00001:#LUT:D=((~A2*(~A3*~A4))+A1) F5USED::#OFF FFX::#OFF FFX_INIT_ATTR::#OFF FFX_SR_ATTR::#OFF FFY::#OFF FFY_INIT_ATTR::#OFF FFY_SR_ATTR::#OFF FXMUX::F FXUSED::#OFF G:u9/u2/SReg_7_and00001:#LUT:D=(~A2*(A3+A4)) GYMUX::G REVUSED::#OFF SRINV::#OFF SYNC_ATTR::#OFF XBUSED::#OFF XUSED::0 YBUSED::#OFF YUSED::0 " ; inst "u4/u2/u3/u1/Q" "SLICEL",placed CLB_X15Y9 SLICE_X21Y17 , cfg " BXINV::#OFF BYINV::BY CEINV::#OFF CLKINV::CLK COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DXMUX::#OFF DYMUX::0 F::#OFF F5USED::#OFF FFX::#OFF FFX_INIT_ATTR::#OFF FFX_SR_ATTR::#OFF FFY:u4/u2/u3/u1/Q:#FF FFY_INIT_ATTR::INIT0 FFY_SR_ATTR::SRLOW FXMUX::#OFF FXUSED::#OFF G::#OFF GYMUX::#OFF REVUSED::#OFF SRINV::#OFF SYNC_ATTR::ASYNC XBUSED::#OFF XUSED::#OFF YBUSED::#OFF YUSED::#OFF " ; inst "u1/m5/m3/Working" "SLICEL",placed CLB_X3Y3 SLICE_X4Y5 , cfg " BXINV::BX BYINV::BY CEINV::CE CLKINV::CLK_B COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DXMUX::0 DYMUX::#OFF F::#OFF F5USED::#OFF FFX:u1/m5/m3/Working:#FF FFX_INIT_ATTR::INIT0 FFX_SR_ATTR::SRLOW FFY::#OFF FFY_INIT_ATTR::#OFF FFY_SR_ATTR::#OFF FXMUX::#OFF FXUSED::#OFF G::#OFF GYMUX::#OFF REVUSED::0 SRINV::SR SYNC_ATTR::ASYNC XBUSED::#OFF XUSED::#OFF YBUSED::#OFF YUSED::#OFF " ; inst "u1/m7/m2/aH/Working" "SLICEL",placed CLB_X8Y8 SLICE_X14Y15 , cfg " BXINV::BX BYINV::BY CEINV::CE CLKINV::CLK_B COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DXMUX::0 DYMUX::#OFF F::#OFF F5USED::#OFF FFX:u1/m7/m2/aH/Working:#FF FFX_INIT_ATTR::INIT0 FFX_SR_ATTR::SRLOW FFY::#OFF FFY_INIT_ATTR::#OFF FFY_SR_ATTR::#OFF FXMUX::#OFF FXUSED::#OFF G::#OFF GYMUX::#OFF REVUSED::0 SRINV::SR SYNC_ATTR::ASYNC XBUSED::#OFF XUSED::#OFF YBUSED::#OFF YUSED::#OFF " ; inst "u9/u2/SReg_10_or0000" "SLICEL",placed CLB_X2Y6 SLICE_X3Y10 , cfg " BXINV::#OFF BYINV::#OFF CEINV::#OFF CLKINV::#OFF COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DXMUX::#OFF DYMUX::#OFF F:u9/u2/SReg_9_or00001:#LUT:D=((~A2*(~A3*~A4))+A1) F5USED::#OFF FFX::#OFF FFX_INIT_ATTR::#OFF FFX_SR_ATTR::#OFF FFY::#OFF FFY_INIT_ATTR::#OFF FFY_SR_ATTR::#OFF FXMUX::F FXUSED::#OFF G:u9/u2/SReg_9_and00001:#LUT:D=(~A2*(A3+A4)) GYMUX::G REVUSED::#OFF SRINV::#OFF SYNC_ATTR::#OFF XBUSED::#OFF XUSED::0 YBUSED::#OFF YUSED::0 " ; inst "u4/u2/En" "SLICEL",placed CLB_X15Y11 SLICE_X20Y20 , cfg " BXINV::BX BYINV::BY CEINV::#OFF CLKINV::CLK COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DXMUX::0 DYMUX::#OFF F::#OFF F5USED::#OFF FFX:u4/u2/En:#FF FFX_INIT_ATTR::INIT0 FFX_SR_ATTR::SRLOW FFY::#OFF FFY_INIT_ATTR::#OFF FFY_SR_ATTR::#OFF FXMUX::#OFF FXUSED::#OFF G::#OFF GYMUX::#OFF REVUSED::0 SRINV::SR SYNC_ATTR::ASYNC XBUSED::#OFF XUSED::#OFF YBUSED::#OFF YUSED::#OFF " ; inst "u6/Addr_or0000" "SLICEL",placed CLB_X6Y12 SLICE_X11Y23 , cfg " BXINV::#OFF BYINV::#OFF CEINV::#OFF CLKINV::#OFF COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DXMUX::#OFF DYMUX::#OFF F::#OFF F5USED::#OFF FFX::#OFF FFX_INIT_ATTR::#OFF FFX_SR_ATTR::#OFF FFY::#OFF FFY_INIT_ATTR::#OFF FFY_SR_ATTR::#OFF FXMUX::#OFF FXUSED::#OFF G:u6/Addr_or00001:#LUT:D=((A2*~A4)+A3) GYMUX::G REVUSED::#OFF SRINV::#OFF SYNC_ATTR::#OFF XBUSED::#OFF XUSED::#OFF YBUSED::#OFF YUSED::0 " ; inst "u1/Done_EthiRST" "SLICEL",placed CLB_X14Y10 SLICE_X18Y19 , cfg " BXINV::#OFF BYINV::#OFF CEINV::#OFF CLKINV::#OFF COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DXMUX::#OFF DYMUX::#OFF F:u1/Done_EthiRST15:#LUT:D=((A4*A2)+(A1*A3)) F5USED::#OFF FFX::#OFF FFX_INIT_ATTR::#OFF FFX_SR_ATTR::#OFF FFY::#OFF FFY_INIT_ATTR::#OFF FFY_SR_ATTR::#OFF FXMUX::F FXUSED::#OFF G:u1/Done_EthiRST15_SW0:#LUT:D=(A1*(A4*A2)) GYMUX::G REVUSED::#OFF SRINV::#OFF SYNC_ATTR::#OFF XBUSED::#OFF XUSED::0 YBUSED::#OFF YUSED::0 " ; inst "u4/u1/Qb" "SLICEL",placed CLB_X13Y13 SLICE_X16Y25 , cfg " BXINV::#OFF BYINV::BY CEINV::#OFF CLKINV::CLK COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DXMUX::#OFF DYMUX::0 F::#OFF F5USED::#OFF FFX::#OFF FFX_INIT_ATTR::#OFF FFX_SR_ATTR::#OFF FFY:u4/u1/Qb:#FF FFY_INIT_ATTR::INIT0 FFY_SR_ATTR::SRLOW FXMUX::#OFF FXUSED::#OFF G::#OFF GYMUX::#OFF REVUSED::#OFF SRINV::#OFF SYNC_ATTR::ASYNC XBUSED::#OFF XUSED::#OFF YBUSED::#OFF YUSED::#OFF " ; inst "u1/m7/m2/aL/Working" "SLICEL",placed CLB_X8Y8 SLICE_X15Y15 , cfg " BXINV::BX BYINV::BY CEINV::CE CLKINV::CLK_B COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DXMUX::0 DYMUX::#OFF F::#OFF F5USED::#OFF FFX:u1/m7/m2/aL/Working:#FF FFX_INIT_ATTR::INIT0 FFX_SR_ATTR::SRLOW FFY::#OFF FFY_INIT_ATTR::#OFF FFY_SR_ATTR::#OFF FXMUX::#OFF FXUSED::#OFF G::#OFF GYMUX::#OFF REVUSED::0 SRINV::SR SYNC_ATTR::ASYNC XBUSED::#OFF XUSED::#OFF YBUSED::#OFF YUSED::#OFF " ; inst "u1/p7/u3/En_and0000" "SLICEL",placed CLB_X14Y5 SLICE_X18Y9 , cfg " BXINV::#OFF BYINV::#OFF CEINV::#OFF CLKINV::#OFF COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DXMUX::#OFF DYMUX::#OFF F:u1/p7/u3/En_and00001:#LUT:D=(A2*A1) F5USED::#OFF FFX::#OFF FFX_INIT_ATTR::#OFF FFX_SR_ATTR::#OFF FFY::#OFF FFY_INIT_ATTR::#OFF FFY_SR_ATTR::#OFF FXMUX::F FXUSED::#OFF G:u4/u2/u2/En_and00001:#LUT:D=(A2*A1) GYMUX::G REVUSED::#OFF SRINV::#OFF SYNC_ATTR::#OFF XBUSED::#OFF XUSED::0 YBUSED::#OFF YUSED::0 " ; inst "u1/m6/a1/aH/Working" "SLICEL",placed CLB_X4Y3 SLICE_X6Y5 , cfg " BXINV::BX BYINV::BY CEINV::CE CLKINV::CLK_B COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DXMUX::0 DYMUX::#OFF F::#OFF F5USED::#OFF FFX:u1/m6/a1/aH/Working:#FF FFX_INIT_ATTR::INIT0 FFX_SR_ATTR::SRLOW FFY::#OFF FFY_INIT_ATTR::#OFF FFY_SR_ATTR::#OFF FXMUX::#OFF FXUSED::#OFF G::#OFF GYMUX::#OFF REVUSED::0 SRINV::SR SYNC_ATTR::ASYNC XBUSED::#OFF XUSED::#OFF YBUSED::#OFF YUSED::#OFF _VCC_SOURCE::X " ; inst "u8/u3/u1/En1" "SLICEL",placed CLB_X8Y9 SLICE_X14Y17 , cfg " BXINV::BX BYINV::BY CEINV::#OFF CLKINV::CLK_B COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DXMUX::0 DYMUX::#OFF F::#OFF F5USED::#OFF FFX:u8/u3/u1/En:#FF FFX_INIT_ATTR::INIT0 FFX_SR_ATTR::SRLOW FFY::#OFF FFY_INIT_ATTR::#OFF FFY_SR_ATTR::#OFF FXMUX::#OFF FXUSED::#OFF G::#OFF GYMUX::#OFF REVUSED::0 SRINV::SR SYNC_ATTR::ASYNC XBUSED::#OFF XUSED::#OFF YBUSED::#OFF YUSED::#OFF " ; inst "u1/p10/Working" "SLICEL",placed CLB_X14Y2 SLICE_X18Y3 , cfg " BXINV::BX BYINV::BY CEINV::CE CLKINV::CLK_B COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DXMUX::0 DYMUX::#OFF F::#OFF F5USED::#OFF FFX:u1/p10/Working:#FF FFX_INIT_ATTR::INIT0 FFX_SR_ATTR::SRLOW FFY::#OFF FFY_INIT_ATTR::#OFF FFY_SR_ATTR::#OFF FXMUX::#OFF FXUSED::#OFF G::#OFF GYMUX::#OFF REVUSED::0 SRINV::SR SYNC_ATTR::ASYNC XBUSED::#OFF XUSED::#OFF YBUSED::#OFF YUSED::#OFF " ; inst "u1/g3/u2/u1/Q" "SLICEL",placed CLB_X7Y4 SLICE_X13Y6 , cfg " BXINV::#OFF BYINV::BY CEINV::#OFF CLKINV::CLK COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DXMUX::#OFF DYMUX::0 F::#OFF F5USED::#OFF FFX::#OFF FFX_INIT_ATTR::#OFF FFX_SR_ATTR::#OFF FFY:u1/g3/u2/u1/Q:#FF FFY_INIT_ATTR::INIT0 FFY_SR_ATTR::SRLOW FXMUX::#OFF FXUSED::#OFF G::#OFF GYMUX::#OFF REVUSED::#OFF SRINV::#OFF SYNC_ATTR::ASYNC XBUSED::#OFF XUSED::#OFF YBUSED::#OFF YUSED::#OFF " ; inst "u9/u1/count<0>" "SLICEL",placed CLB_X2Y8 SLICE_X2Y15 , cfg " BXINV::BX_B BYINV::#OFF CEINV::#OFF CLKINV::CLK_B COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DXMUX::0 DYMUX::1 F::#OFF F5USED::#OFF FFX:u9/u1/count_0:#FF FFX_INIT_ATTR::INIT0 FFX_SR_ATTR::SRLOW FFY:u9/u1/count_1:#FF FFY_INIT_ATTR::INIT0 FFY_SR_ATTR::SRLOW FXMUX::#OFF FXUSED::#OFF G:u9/u1/count_mux0003<3>1:#LUT:D=(A2@A4) GYMUX::G REVUSED::#OFF SRINV::SR SYNC_ATTR::ASYNC XBUSED::#OFF XUSED::#OFF YBUSED::#OFF YUSED::#OFF " ; inst "u1/m6/a1/aL/Working" "SLICEL",placed CLB_X4Y3 SLICE_X7Y5 , cfg " BXINV::BX BYINV::BY CEINV::CE CLKINV::CLK_B COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DXMUX::0 DYMUX::#OFF F::#OFF F5USED::#OFF FFX:u1/m6/a1/aL/Working:#FF FFX_INIT_ATTR::INIT0 FFX_SR_ATTR::SRLOW FFY::#OFF FFY_INIT_ATTR::#OFF FFY_SR_ATTR::#OFF FXMUX::#OFF FXUSED::#OFF G::#OFF GYMUX::#OFF REVUSED::0 SRINV::SR SYNC_ATTR::ASYNC XBUSED::#OFF XUSED::#OFF YBUSED::#OFF YUSED::#OFF " ; inst "u5/InitGo" "SLICEL",placed CLB_X16Y13 SLICE_X23Y24 , cfg " BXINV::#OFF BYINV::#OFF CEINV::#OFF CLKINV::#OFF COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DXMUX::#OFF DYMUX::#OFF F::#OFF F5USED::#OFF FFX::#OFF FFX_INIT_ATTR::#OFF FFX_SR_ATTR::#OFF FFY::#OFF FFY_INIT_ATTR::#OFF FFY_SR_ATTR::#OFF FXMUX::#OFF FXUSED::#OFF G:u5/u2/Q1:#LUT:D=(~A1*A4) GYMUX::G REVUSED::#OFF SRINV::#OFF SYNC_ATTR::#OFF XBUSED::#OFF XUSED::#OFF YBUSED::#OFF YUSED::0 " ; inst "u1/m6/m/m3/Working" "SLICEL",placed CLB_X5Y5 SLICE_X8Y8 , cfg " BXINV::BX BYINV::BY CEINV::CE CLKINV::CLK_B COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DXMUX::0 DYMUX::#OFF F::#OFF F5USED::#OFF FFX:u1/m6/m/m3/Working:#FF FFX_INIT_ATTR::INIT0 FFX_SR_ATTR::SRLOW FFY::#OFF FFY_INIT_ATTR::#OFF FFY_SR_ATTR::#OFF FXMUX::#OFF FXUSED::#OFF G::#OFF GYMUX::#OFF REVUSED::0 SRINV::SR SYNC_ATTR::ASYNC XBUSED::#OFF XUSED::#OFF YBUSED::#OFF YUSED::#OFF " ; inst "u7/u3/u1/Q_int" "SLICEL",placed CLB_X2Y15 SLICE_X3Y28 , cfg " BXINV::#OFF BYINV::BY_B CEINV::#OFF CLKINV::CLK_B COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DXMUX::#OFF DYMUX::0 F::#OFF F5USED::#OFF FFX::#OFF FFX_INIT_ATTR::#OFF FFX_SR_ATTR::#OFF FFY:u7/u3/u1/Q_int:#FF FFY_INIT_ATTR::INIT1 FFY_SR_ATTR::SRHIGH FXMUX::#OFF FXUSED::#OFF G::#OFF GYMUX::#OFF REVUSED::#OFF SRINV::SR SYNC_ATTR::SYNC XBUSED::#OFF XUSED::#OFF YBUSED::#OFF YUSED::#OFF " ; inst "u1/m3/m2/aH/Working" "SLICEL",placed CLB_X2Y1 SLICE_X3Y0 , cfg " BXINV::BX BYINV::BY CEINV::CE CLKINV::CLK_B COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DXMUX::0 DYMUX::#OFF F::#OFF F5USED::#OFF FFX:u1/m3/m2/aH/Working:#FF FFX_INIT_ATTR::INIT0 FFX_SR_ATTR::SRLOW FFY::#OFF FFY_INIT_ATTR::#OFF FFY_SR_ATTR::#OFF FXMUX::#OFF FXUSED::#OFF G::#OFF GYMUX::#OFF REVUSED::0 SRINV::SR SYNC_ATTR::ASYNC XBUSED::#OFF XUSED::#OFF YBUSED::#OFF YUSED::#OFF " ; inst "u1/m1/u1/Q_int" "SLICEL",placed CLB_X14Y2 SLICE_X19Y2 , cfg " BXINV::#OFF BYINV::#OFF CEINV::#OFF CLKINV::CLK_B COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DXMUX::1 DYMUX::#OFF F:u1/p10/En1:#LUT:D=(~A2*((~A4+(A4*A3))*A1)) F5USED::#OFF FFX:u1/m1/u1/Q_int:#FF FFX_INIT_ATTR::INIT0 FFX_SR_ATTR::SRLOW FFY::#OFF FFY_INIT_ATTR::#OFF FFY_SR_ATTR::#OFF FXMUX::F FXUSED::#OFF G:u1/p7/Done1:#LUT:D=(~A1*A3) GYMUX::G REVUSED::#OFF SRINV::#OFF SYNC_ATTR::ASYNC XBUSED::#OFF XUSED::0 YBUSED::#OFF YUSED::0 " ; inst "u9/u2/SReg_17_and0000" "SLICEL",placed CLB_X4Y8 SLICE_X6Y15 , cfg " BXINV::#OFF BYINV::#OFF CEINV::#OFF CLKINV::#OFF COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DXMUX::#OFF DYMUX::#OFF F:u9/u2/SReg_17_and00001:#LUT:D=(~A2*(~A1*A3)) F5USED::#OFF FFX::#OFF FFX_INIT_ATTR::#OFF FFX_SR_ATTR::#OFF FFY::#OFF FFY_INIT_ATTR::#OFF FFY_SR_ATTR::#OFF FXMUX::F FXUSED::#OFF G:u9/u2/SReg_17_or00001:#LUT:D=((~A2*(~A3+(A4+A1)))+(A2*A4)) GYMUX::G REVUSED::#OFF SRINV::#OFF SYNC_ATTR::#OFF XBUSED::#OFF XUSED::0 YBUSED::#OFF YUSED::0 " ; inst "u1/g3/u3/u1/Q" "SLICEL",placed CLB_X8Y3 SLICE_X14Y5 , cfg " BXINV::#OFF BYINV::BY CEINV::#OFF CLKINV::CLK COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DXMUX::#OFF DYMUX::0 F::#OFF F5USED::#OFF FFX::#OFF FFX_INIT_ATTR::#OFF FFX_SR_ATTR::#OFF FFY:u1/g3/u3/u1/Q:#FF FFY_INIT_ATTR::INIT0 FFY_SR_ATTR::SRLOW FXMUX::#OFF FXUSED::#OFF G::#OFF GYMUX::#OFF REVUSED::#OFF SRINV::#OFF SYNC_ATTR::ASYNC XBUSED::#OFF XUSED::#OFF YBUSED::#OFF YUSED::#OFF " ; inst "u1/m6/b2/u1/Q_int" "SLICEL",placed CLB_X5Y7 SLICE_X9Y13 , cfg " BXINV::#OFF BYINV::BY CEINV::#OFF CLKINV::CLK_B COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DXMUX::#OFF DYMUX::0 F::#OFF F5USED::#OFF FFX::#OFF FFX_INIT_ATTR::#OFF FFX_SR_ATTR::#OFF FFY:u1/m6/b2/u1/Q_int:#FF FFY_INIT_ATTR::INIT0 FFY_SR_ATTR::SRLOW FXMUX::#OFF FXUSED::#OFF G::#OFF GYMUX::#OFF REVUSED::#OFF SRINV::#OFF SYNC_ATTR::ASYNC XBUSED::#OFF XUSED::#OFF YBUSED::#OFF YUSED::#OFF " ; inst "u7/u1/count<0>" "SLICEL",placed CLB_X3Y16 SLICE_X4Y30 , cfg " BXINV::#OFF BYINV::#OFF CEINV::CE CLKINV::CLK COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DXMUX::1 DYMUX::#OFF F:u7/u1/Mcount_count_xor<0>11:#LUT:D=(~A1*(A4+~A2)) F5USED::#OFF FFX:u7/u1/count_0:#FF FFX_INIT_ATTR::INIT0 FFX_SR_ATTR::SRLOW FFY::#OFF FFY_INIT_ATTR::#OFF FFY_SR_ATTR::#OFF FXMUX::F FXUSED::#OFF G:u7/u1/Mcount_count_xor<1>111:#LUT:D=(A3+(A2+A4)) GYMUX::G REVUSED::#OFF SRINV::SR SYNC_ATTR::ASYNC XBUSED::#OFF XUSED::#OFF YBUSED::#OFF YUSED::0 " ; inst "u1/m7/m3/Working" "SLICEL",placed CLB_X8Y7 SLICE_X14Y12 , cfg " BXINV::BX BYINV::BY CEINV::CE CLKINV::CLK_B COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DXMUX::0 DYMUX::#OFF F::#OFF F5USED::#OFF FFX:u1/m7/m3/Working:#FF FFX_INIT_ATTR::INIT0 FFX_SR_ATTR::SRLOW FFY::#OFF FFY_INIT_ATTR::#OFF FFY_SR_ATTR::#OFF FXMUX::#OFF FXUSED::#OFF G::#OFF GYMUX::#OFF REVUSED::0 SRINV::SR SYNC_ATTR::ASYNC XBUSED::#OFF XUSED::#OFF YBUSED::#OFF YUSED::#OFF " ; inst "u7/u3/u1/Q" "SLICEL",placed CLB_X1Y15 SLICE_X1Y29 , cfg " BXINV::#OFF BYINV::BY CEINV::#OFF CLKINV::CLK COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DXMUX::#OFF DYMUX::0 F::#OFF F5USED::#OFF FFX::#OFF FFX_INIT_ATTR::#OFF FFX_SR_ATTR::#OFF FFY:u7/u3/u1/Q:#FF FFY_INIT_ATTR::INIT0 FFY_SR_ATTR::SRLOW FXMUX::#OFF FXUSED::#OFF G::#OFF GYMUX::#OFF REVUSED::#OFF SRINV::#OFF SYNC_ATTR::ASYNC XBUSED::#OFF XUSED::#OFF YBUSED::#OFF YUSED::#OFF " ; inst "u1/m3/m2/aL/Working" "SLICEL",placed CLB_X2Y1 SLICE_X2Y0 , cfg " BXINV::BX BYINV::BY CEINV::CE CLKINV::CLK_B COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DXMUX::0 DYMUX::#OFF F::#OFF F5USED::#OFF FFX:u1/m3/m2/aL/Working:#FF FFX_INIT_ATTR::INIT0 FFX_SR_ATTR::SRLOW FFY::#OFF FFY_INIT_ATTR::#OFF FFY_SR_ATTR::#OFF FXMUX::#OFF FXUSED::#OFF G::#OFF GYMUX::#OFF REVUSED::0 SRINV::SR SYNC_ATTR::ASYNC XBUSED::#OFF XUSED::#OFF YBUSED::#OFF YUSED::#OFF _GND_SOURCE::X " ; inst "u9/u2/SReg_15_or0000" "SLICEL",placed CLB_X1Y6 SLICE_X1Y10 , cfg " BXINV::#OFF BYINV::#OFF CEINV::#OFF CLKINV::#OFF COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DXMUX::#OFF DYMUX::#OFF F:u9/u2/SReg_15_or00001:#LUT:D=((~A1*(~A4+(A3+A2)))+(A1*A3)) F5USED::#OFF FFX::#OFF FFX_INIT_ATTR::#OFF FFX_SR_ATTR::#OFF FFY::#OFF FFY_INIT_ATTR::#OFF FFY_SR_ATTR::#OFF FXMUX::F FXUSED::#OFF G:u9/u2/SReg_15_and00001:#LUT:D=(~A1*(~A2*A4)) GYMUX::G REVUSED::#OFF SRINV::#OFF SYNC_ATTR::#OFF XBUSED::#OFF XUSED::0 YBUSED::#OFF YUSED::0 " ; inst "u1/m5/m2/u1/Q" "SLICEL",placed CLB_X2Y4 SLICE_X3Y6 , cfg " BXINV::#OFF BYINV::BY CEINV::#OFF CLKINV::CLK COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DXMUX::#OFF DYMUX::0 F::#OFF F5USED::#OFF FFX::#OFF FFX_INIT_ATTR::#OFF FFX_SR_ATTR::#OFF FFY:u1/m5/m2/u1/Q:#FF FFY_INIT_ATTR::INIT0 FFY_SR_ATTR::SRLOW FXMUX::#OFF FXUSED::#OFF G::#OFF GYMUX::#OFF REVUSED::#OFF SRINV::#OFF SYNC_ATTR::ASYNC XBUSED::#OFF XUSED::#OFF YBUSED::#OFF YUSED::#OFF " ; inst "u8/u3/u1/En_and0000" "SLICEL",placed CLB_X15Y9 SLICE_X20Y17 , cfg " BXINV::#OFF BYINV::#OFF CEINV::#OFF CLKINV::#OFF COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DXMUX::#OFF DYMUX::#OFF F:u8/u3/u1/En_and00001:#LUT:D=(A2*A3) F5USED::#OFF FFX::#OFF FFX_INIT_ATTR::#OFF FFX_SR_ATTR::#OFF FFY::#OFF FFY_INIT_ATTR::#OFF FFY_SR_ATTR::#OFF FXMUX::F FXUSED::#OFF G:u4/u2/u3/En_and00001:#LUT:D=(A4*A3) GYMUX::G REVUSED::#OFF SRINV::#OFF SYNC_ATTR::#OFF XBUSED::#OFF XUSED::0 YBUSED::#OFF YUSED::0 " ; inst "u5/u2/Qa" "SLICEL",placed CLB_X16Y13 SLICE_X22Y25 , cfg " BXINV::#OFF BYINV::BY CEINV::#OFF CLKINV::CLK_B COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DXMUX::#OFF DYMUX::0 F::#OFF F5USED::#OFF FFX::#OFF FFX_INIT_ATTR::#OFF FFX_SR_ATTR::#OFF FFY:u5/u2/Qa:#FF FFY_INIT_ATTR::INIT0 FFY_SR_ATTR::SRLOW FXMUX::#OFF FXUSED::#OFF G::#OFF GYMUX::#OFF REVUSED::#OFF SRINV::#OFF SYNC_ATTR::ASYNC XBUSED::#OFF XUSED::#OFF YBUSED::#OFF YUSED::#OFF " ; inst "u5/u2/Qb" "SLICEL",placed CLB_X16Y13 SLICE_X22Y24 , cfg " BXINV::#OFF BYINV::BY CEINV::#OFF CLKINV::CLK COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DXMUX::#OFF DYMUX::0 F::#OFF F5USED::#OFF FFX::#OFF FFX_INIT_ATTR::#OFF FFX_SR_ATTR::#OFF FFY:u5/u2/Qb:#FF FFY_INIT_ATTR::INIT0 FFY_SR_ATTR::SRLOW FXMUX::#OFF FXUSED::#OFF G::#OFF GYMUX::#OFF REVUSED::#OFF SRINV::#OFF SYNC_ATTR::ASYNC XBUSED::#OFF XUSED::#OFF YBUSED::#OFF YUSED::#OFF " ; inst "u1/m2/m2/Done_AddrH" "SLICEL",placed CLB_X6Y1 SLICE_X10Y0 , cfg " BXINV::#OFF BYINV::#OFF CEINV::#OFF CLKINV::#OFF COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DXMUX::#OFF DYMUX::#OFF F::#OFF F5USED::#OFF FFX::#OFF FFX_INIT_ATTR::#OFF FFX_SR_ATTR::#OFF FFY::#OFF FFY_INIT_ATTR::#OFF FFY_SR_ATTR::#OFF FXMUX::#OFF FXUSED::#OFF G:u1/m2/m2/aH/En1:#LUT:D=(~A3*(~A1*A4)) GYMUX::G REVUSED::#OFF SRINV::#OFF SYNC_ATTR::#OFF XBUSED::#OFF XUSED::#OFF YBUSED::#OFF YUSED::0 " ; inst "u1/p7/u2/En" "SLICEL",placed CLB_X7Y5 SLICE_X13Y8 , cfg " BXINV::BX BYINV::BY CEINV::#OFF CLKINV::CLK_B COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DXMUX::0 DYMUX::#OFF F::#OFF F5USED::#OFF FFX:u1/p7/u2/En:#FF FFX_INIT_ATTR::INIT0 FFX_SR_ATTR::SRLOW FFY::#OFF FFY_INIT_ATTR::#OFF FFY_SR_ATTR::#OFF FXMUX::#OFF FXUSED::#OFF G::#OFF GYMUX::#OFF REVUSED::0 SRINV::SR SYNC_ATTR::ASYNC XBUSED::#OFF XUSED::#OFF YBUSED::#OFF YUSED::#OFF " ; inst "u1/p7/u1/Qa" "SLICEL",placed CLB_X7Y3 SLICE_X12Y5 , cfg " BXINV::#OFF BYINV::BY CEINV::#OFF CLKINV::CLK_B COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DXMUX::#OFF DYMUX::0 F::#OFF F5USED::#OFF FFX::#OFF FFX_INIT_ATTR::#OFF FFX_SR_ATTR::#OFF FFY:u1/p7/u1/Qa:#FF FFY_INIT_ATTR::INIT0 FFY_SR_ATTR::SRLOW FXMUX::#OFF FXUSED::#OFF G::#OFF GYMUX::#OFF REVUSED::#OFF SRINV::#OFF SYNC_ATTR::ASYNC XBUSED::#OFF XUSED::#OFF YBUSED::#OFF YUSED::#OFF " ; inst "u1/p7/u1/Qb" "SLICEL",placed CLB_X6Y3 SLICE_X11Y5 , cfg " BXINV::#OFF BYINV::BY CEINV::#OFF CLKINV::CLK COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DXMUX::#OFF DYMUX::0 F::#OFF F5USED::#OFF FFX::#OFF FFX_INIT_ATTR::#OFF FFX_SR_ATTR::#OFF FFY:u1/p7/u1/Qb:#FF FFY_INIT_ATTR::INIT0 FFY_SR_ATTR::SRLOW FXMUX::#OFF FXUSED::#OFF G::#OFF GYMUX::#OFF REVUSED::#OFF SRINV::#OFF SYNC_ATTR::ASYNC XBUSED::#OFF XUSED::#OFF YBUSED::#OFF YUSED::#OFF " ; inst "u1/p7/u3/En" "SLICEL",placed CLB_X14Y4 SLICE_X19Y6 , cfg " BXINV::BX BYINV::BY CEINV::#OFF CLKINV::CLK_B COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DXMUX::0 DYMUX::#OFF F::#OFF F5USED::#OFF FFX:u1/p7/u3/En:#FF FFX_INIT_ATTR::INIT0 FFX_SR_ATTR::SRLOW FFY::#OFF FFY_INIT_ATTR::#OFF FFY_SR_ATTR::#OFF FXMUX::#OFF FXUSED::#OFF G::#OFF GYMUX::#OFF REVUSED::0 SRINV::SR SYNC_ATTR::ASYNC XBUSED::#OFF XUSED::#OFF YBUSED::#OFF YUSED::#OFF " ; inst "u1/m3/m2/Done_AddrH" "SLICEL",placed CLB_X2Y1 SLICE_X3Y1 , cfg " BXINV::#OFF BYINV::#OFF CEINV::#OFF CLKINV::#OFF COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DXMUX::#OFF DYMUX::#OFF F::#OFF F5USED::#OFF FFX::#OFF FFX_INIT_ATTR::#OFF FFX_SR_ATTR::#OFF FFY::#OFF FFY_INIT_ATTR::#OFF FFY_SR_ATTR::#OFF FXMUX::#OFF FXUSED::#OFF G:u1/m3/m2/aH/En1:#LUT:D=(~A1*(~A2*A4)) GYMUX::G REVUSED::#OFF SRINV::#OFF SYNC_ATTR::#OFF XBUSED::#OFF XUSED::#OFF YBUSED::#OFF YUSED::0 " ; inst "SPI_iRst" "SLICEL",placed CLB_X4Y16 SLICE_X6Y31 , cfg " BXINV::#OFF BYINV::#OFF CEINV::#OFF CLKINV::#OFF COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DXMUX::#OFF DYMUX::#OFF F:SPI_iRst1:#LUT:D=(~A2*A1) F5USED::#OFF FFX::#OFF FFX_INIT_ATTR::#OFF FFX_SR_ATTR::#OFF FFY::#OFF FFY_INIT_ATTR::#OFF FFY_SR_ATTR::#OFF FXMUX::F FXUSED::#OFF G:u7/u9/iRst_inv1:#LUT:D=(A2+~A1) GYMUX::G REVUSED::#OFF SRINV::#OFF SYNC_ATTR::#OFF XBUSED::#OFF XUSED::0 YBUSED::#OFF YUSED::0 " ; inst "u8/intMaskByteNum<0>" "SLICEL",placed CLB_X3Y8 SLICE_X5Y15 , cfg " BXINV::BX_B BYINV::#OFF CEINV::CE CLKINV::CLK_B COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DXMUX::0 DYMUX::1 F:u8/MaskStage_and00011:#LUT:D=(A4*(A3*(A2+A1))) F5USED::#OFF FFX:u8/intMaskByteNum_0:#FF FFX_INIT_ATTR::INIT1 FFX_SR_ATTR::SRLOW FFY:u8/intMaskByteNum_1:#FF FFY_INIT_ATTR::INIT1 FFY_SR_ATTR::SRLOW FXMUX::F FXUSED::#OFF G:u8/Mcount_intMaskByteNum_xor<1>11:#LUT:D=(A4@A3) GYMUX::G REVUSED::#OFF SRINV::SR SYNC_ATTR::ASYNC XBUSED::#OFF XUSED::0 YBUSED::#OFF YUSED::#OFF " ; inst "u8/l1/En" "SLICEL",placed CLB_X5Y7 SLICE_X8Y13 , cfg " BXINV::BX BYINV::BY CEINV::#OFF CLKINV::CLK_B COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DXMUX::0 DYMUX::#OFF F::#OFF F5USED::#OFF FFX:u8/l1/En:#FF FFX_INIT_ATTR::INIT0 FFX_SR_ATTR::SRLOW FFY::#OFF FFY_INIT_ATTR::#OFF FFY_SR_ATTR::#OFF FXMUX::#OFF FXUSED::#OFF G::#OFF GYMUX::#OFF REVUSED::0 SRINV::SR SYNC_ATTR::ASYNC XBUSED::#OFF XUSED::#OFF YBUSED::#OFF YUSED::#OFF " ; inst "u8/VoltData<7>" "SLICEL",placed CLB_X4Y9 SLICE_X6Y17 , cfg " BXINV::#OFF BYINV::BY CEINV::CE CLKINV::CLK COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DXMUX::#OFF DYMUX::0 F::#OFF F5USED::#OFF FFX::#OFF FFX_INIT_ATTR::#OFF FFX_SR_ATTR::#OFF FFY:u8/VoltData_7:#FF FFY_INIT_ATTR::INIT0 FFY_SR_ATTR::SRLOW FXMUX::#OFF FXUSED::#OFF G::#OFF GYMUX::#OFF REVUSED::#OFF SRINV::SR SYNC_ATTR::ASYNC XBUSED::#OFF XUSED::#OFF YBUSED::#OFF YUSED::#OFF _GND_SOURCE::X " ; inst "u1/m4/m2/Done_AddrH" "SLICEL",placed CLB_X1Y3 SLICE_X1Y4 , cfg " BXINV::#OFF BYINV::#OFF CEINV::#OFF CLKINV::#OFF COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DXMUX::#OFF DYMUX::#OFF F::#OFF F5USED::#OFF FFX::#OFF FFX_INIT_ATTR::#OFF FFX_SR_ATTR::#OFF FFY::#OFF FFY_INIT_ATTR::#OFF FFY_SR_ATTR::#OFF FXMUX::#OFF FXUSED::#OFF G:u1/m4/m2/aH/En1:#LUT:D=(~A3*(~A4*A1)) GYMUX::G REVUSED::#OFF SRINV::#OFF SYNC_ATTR::#OFF XBUSED::#OFF XUSED::#OFF YBUSED::#OFF YUSED::0 " ; inst "u8/VoltData<9>" "SLICEL",placed CLB_X3Y9 SLICE_X4Y17 , cfg " BXINV::#OFF BYINV::BY CEINV::CE CLKINV::CLK COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DXMUX::#OFF DYMUX::0 F::#OFF F5USED::#OFF FFX::#OFF FFX_INIT_ATTR::#OFF FFX_SR_ATTR::#OFF FFY:u8/VoltData_9:#FF FFY_INIT_ATTR::INIT0 FFY_SR_ATTR::SRLOW FXMUX::#OFF FXUSED::#OFF G::#OFF GYMUX::#OFF REVUSED::#OFF SRINV::SR SYNC_ATTR::ASYNC XBUSED::#OFF XUSED::#OFF YBUSED::#OFF YUSED::#OFF " ; inst "u8/l2/En" "SLICEL",placed CLB_X6Y9 SLICE_X11Y17 , cfg " BXINV::BX BYINV::BY CEINV::#OFF CLKINV::CLK_B COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DXMUX::0 DYMUX::#OFF F::#OFF F5USED::#OFF FFX:u8/l2/En:#FF FFX_INIT_ATTR::INIT0 FFX_SR_ATTR::SRLOW FFY::#OFF FFY_INIT_ATTR::#OFF FFY_SR_ATTR::#OFF FXMUX::#OFF FXUSED::#OFF G::#OFF GYMUX::#OFF REVUSED::0 SRINV::SR SYNC_ATTR::ASYNC XBUSED::#OFF XUSED::#OFF YBUSED::#OFF YUSED::#OFF " ; inst "u2/u3/u1/u1/Q" "SLICEL",placed CLB_X6Y7 SLICE_X10Y12 , cfg " BXINV::#OFF BYINV::BY CEINV::#OFF CLKINV::CLK COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DXMUX::#OFF DYMUX::0 F::#OFF F5USED::#OFF FFX::#OFF FFX_INIT_ATTR::#OFF FFX_SR_ATTR::#OFF FFY:u2/u3/u1/u1/Q:#FF FFY_INIT_ATTR::INIT0 FFY_SR_ATTR::SRLOW FXMUX::#OFF FXUSED::#OFF G::#OFF GYMUX::#OFF REVUSED::#OFF SRINV::#OFF SYNC_ATTR::ASYNC XBUSED::#OFF XUSED::#OFF YBUSED::#OFF YUSED::#OFF " ; inst "u1/m5/m2/Done_AddrH" "SLICEL",placed CLB_X3Y4 SLICE_X4Y7 , cfg " BXINV::#OFF BYINV::#OFF CEINV::#OFF CLKINV::#OFF COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DXMUX::#OFF DYMUX::#OFF F::#OFF F5USED::#OFF FFX::#OFF FFX_INIT_ATTR::#OFF FFX_SR_ATTR::#OFF FFY::#OFF FFY_INIT_ATTR::#OFF FFY_SR_ATTR::#OFF FXMUX::#OFF FXUSED::#OFF G:u1/m5/m2/aH/En1:#LUT:D=(~A1*(~A2*A4)) GYMUX::G REVUSED::#OFF SRINV::#OFF SYNC_ATTR::#OFF XBUSED::#OFF XUSED::#OFF YBUSED::#OFF YUSED::0 " ; inst "u7/u8/Done_int_and0000" "SLICEL",placed CLB_X8Y11 SLICE_X14Y21 , cfg " BXINV::#OFF BYINV::#OFF CEINV::#OFF CLKINV::#OFF COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DXMUX::#OFF DYMUX::#OFF F::#OFF F5USED::#OFF FFX::#OFF FFX_INIT_ATTR::#OFF FFX_SR_ATTR::#OFF FFY::#OFF FFY_INIT_ATTR::#OFF FFY_SR_ATTR::#OFF FXMUX::#OFF FXUSED::#OFF G:u7/u8/Done_int_and00001:#LUT:D=(~A1*(~A4*(~A3*A2))) GYMUX::G REVUSED::#OFF SRINV::#OFF SYNC_ATTR::#OFF XBUSED::#OFF XUSED::#OFF YBUSED::#OFF YUSED::0 " ; inst "u1/Done_MACCF" "SLICEL",placed CLB_X5Y1 SLICE_X9Y0 , cfg " BXINV::#OFF BYINV::#OFF CEINV::#OFF CLKINV::#OFF COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DXMUX::#OFF DYMUX::#OFF F:u1/m2/m3/En1:#LUT:D=(~A1*(~A2*A3)) F5USED::#OFF FFX::#OFF FFX_INIT_ATTR::#OFF FFX_SR_ATTR::#OFF FFY::#OFF FFY_INIT_ATTR::#OFF FFY_SR_ATTR::#OFF FXMUX::F FXUSED::#OFF G:u1/m2/m2/aL/En1:#LUT:D=(~A3*((~A2+(A2*A1))*A4)) GYMUX::G REVUSED::#OFF SRINV::#OFF SYNC_ATTR::#OFF XBUSED::#OFF XUSED::0 YBUSED::#OFF YUSED::0 " ; inst "u6/u3/Qa" "SLICEL",placed CLB_X5Y12 SLICE_X8Y22 , cfg " BXINV::#OFF BYINV::BY CEINV::#OFF CLKINV::CLK_B COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DXMUX::#OFF DYMUX::0 F::#OFF F5USED::#OFF FFX::#OFF FFX_INIT_ATTR::#OFF FFX_SR_ATTR::#OFF FFY:u6/u3/Qa:#FF FFY_INIT_ATTR::INIT0 FFY_SR_ATTR::SRLOW FXMUX::#OFF FXUSED::#OFF G::#OFF GYMUX::#OFF REVUSED::#OFF SRINV::#OFF SYNC_ATTR::ASYNC XBUSED::#OFF XUSED::#OFF YBUSED::#OFF YUSED::#OFF " ; inst "u6/u3/Qb" "SLICEL",placed CLB_X5Y12 SLICE_X8Y23 , cfg " BXINV::#OFF BYINV::BY CEINV::#OFF CLKINV::CLK COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DXMUX::#OFF DYMUX::0 F::#OFF F5USED::#OFF FFX::#OFF FFX_INIT_ATTR::#OFF FFX_SR_ATTR::#OFF FFY:u6/u3/Qb:#FF FFY_INIT_ATTR::INIT0 FFY_SR_ATTR::SRLOW FXMUX::#OFF FXUSED::#OFF G::#OFF GYMUX::#OFF REVUSED::#OFF SRINV::#OFF SYNC_ATTR::ASYNC XBUSED::#OFF XUSED::#OFF YBUSED::#OFF YUSED::#OFF " ; inst "u1/m7/m2/Done_AddrH" "SLICEL",placed CLB_X8Y8 SLICE_X15Y14 , cfg " BXINV::#OFF BYINV::#OFF CEINV::#OFF CLKINV::#OFF COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DXMUX::#OFF DYMUX::#OFF F::#OFF F5USED::#OFF FFX::#OFF FFX_INIT_ATTR::#OFF FFX_SR_ATTR::#OFF FFY::#OFF FFY_INIT_ATTR::#OFF FFY_SR_ATTR::#OFF FXMUX::#OFF FXUSED::#OFF G:u1/m7/m2/aH/En1:#LUT:D=(~A2*(~A3*A1)) GYMUX::G REVUSED::#OFF SRINV::#OFF SYNC_ATTR::#OFF XBUSED::#OFF XUSED::#OFF YBUSED::#OFF YUSED::0 " ; inst "u1/i2/Working" "SLICEL",placed CLB_X15Y3 SLICE_X20Y4 , cfg " BXINV::BX BYINV::BY CEINV::CE CLKINV::CLK_B COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DXMUX::0 DYMUX::#OFF F::#OFF F5USED::#OFF FFX:u1/i2/Working:#FF FFX_INIT_ATTR::INIT0 FFX_SR_ATTR::SRLOW FFY::#OFF FFY_INIT_ATTR::#OFF FFY_SR_ATTR::#OFF FXMUX::#OFF FXUSED::#OFF G::#OFF GYMUX::#OFF REVUSED::0 SRINV::SR SYNC_ATTR::ASYNC XBUSED::#OFF XUSED::#OFF YBUSED::#OFF YUSED::#OFF _GND_SOURCE::X " ; inst "u1/Done_IPGT" "SLICEL",placed CLB_X2Y1 SLICE_X2Y1 , cfg " BXINV::#OFF BYINV::#OFF CEINV::#OFF CLKINV::#OFF COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DXMUX::#OFF DYMUX::#OFF F:u1/m3/m3/En1:#LUT:D=(~A4*(~A3*A2)) F5USED::#OFF FFX::#OFF FFX_INIT_ATTR::#OFF FFX_SR_ATTR::#OFF FFY::#OFF FFY_INIT_ATTR::#OFF FFY_SR_ATTR::#OFF FXMUX::F FXUSED::#OFF G:u1/m3/m2/aL/En1:#LUT:D=(~A4*((~A1+(A1*A3))*A2)) GYMUX::G REVUSED::#OFF SRINV::#OFF SYNC_ATTR::#OFF XBUSED::#OFF XUSED::0 YBUSED::#OFF YUSED::0 " ; inst "u6/u4/Q_int" "SLICEL",placed CLB_X13Y12 SLICE_X17Y23 , cfg " BXINV::#OFF BYINV::BY CEINV::#OFF CLKINV::CLK_B COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DXMUX::#OFF DYMUX::0 F::#OFF F5USED::#OFF FFX::#OFF FFX_INIT_ATTR::#OFF FFX_SR_ATTR::#OFF FFY:u6/u4/Q_int:#FF FFY_INIT_ATTR::INIT0 FFY_SR_ATTR::SRLOW FXMUX::#OFF FXUSED::#OFF G::#OFF GYMUX::#OFF REVUSED::#OFF SRINV::#OFF SYNC_ATTR::ASYNC XBUSED::#OFF XUSED::#OFF YBUSED::#OFF YUSED::#OFF " ; inst "u5/s2/u1/En" "SLICEL",placed CLB_X16Y12 SLICE_X23Y22 , cfg " BXINV::BX BYINV::BY CEINV::#OFF CLKINV::CLK_B COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DXMUX::0 DYMUX::#OFF F::#OFF F5USED::#OFF FFX:u5/s2/u1/En:#FF FFX_INIT_ATTR::INIT0 FFX_SR_ATTR::SRLOW FFY::#OFF FFY_INIT_ATTR::#OFF FFY_SR_ATTR::#OFF FXMUX::#OFF FXUSED::#OFF G::#OFF GYMUX::#OFF REVUSED::0 SRINV::SR SYNC_ATTR::ASYNC XBUSED::#OFF XUSED::#OFF YBUSED::#OFF YUSED::#OFF " ; inst "u1/Done_IPGR" "SLICEL",placed CLB_X1Y3 SLICE_X1Y5 , cfg " BXINV::#OFF BYINV::#OFF CEINV::#OFF CLKINV::#OFF COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DXMUX::#OFF DYMUX::#OFF F:u1/m4/m3/En1:#LUT:D=(~A1*(~A4*A3)) F5USED::#OFF FFX::#OFF FFX_INIT_ATTR::#OFF FFX_SR_ATTR::#OFF FFY::#OFF FFY_INIT_ATTR::#OFF FFY_SR_ATTR::#OFF FXMUX::F FXUSED::#OFF G:u1/m4/m2/aL/En1:#LUT:D=(~A3*((~A1+(A1*A2))*A4)) GYMUX::G REVUSED::#OFF SRINV::#OFF SYNC_ATTR::#OFF XBUSED::#OFF XUSED::0 YBUSED::#OFF YUSED::0 " ; inst "u7/u8/Wr_int_mux000363" "SLICEL",placed CLB_X5Y12 SLICE_X9Y23 , cfg " BXINV::#OFF BYINV::#OFF CEINV::#OFF CLKINV::#OFF COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DXMUX::#OFF DYMUX::#OFF F:u7/u8/Wr_int_mux000363:#LUT:D=(~A1*A4) F5USED::#OFF FFX::#OFF FFX_INIT_ATTR::#OFF FFX_SR_ATTR::#OFF FFY::#OFF FFY_INIT_ATTR::#OFF FFY_SR_ATTR::#OFF FXMUX::F FXUSED::#OFF G:u6/Go1:#LUT:D=((A3*~A2)+(A4*~A1)) GYMUX::G REVUSED::#OFF SRINV::#OFF SYNC_ATTR::#OFF XBUSED::#OFF XUSED::0 YBUSED::#OFF YUSED::0 " ; inst "state_D<0>LogicTrst19" "SLICEL",placed CLB_X15Y12 SLICE_X21Y23 , cfg " BXINV::#OFF BYINV::#OFF CEINV::#OFF CLKINV::#OFF COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DXMUX::#OFF DYMUX::#OFF F:state_D<0>LogicTrst19:#LUT:D=(~A3+(~A4+(A1*~A2))) F5USED::#OFF FFX::#OFF FFX_INIT_ATTR::#OFF FFX_SR_ATTR::#OFF FFY::#OFF FFY_INIT_ATTR::#OFF FFY_SR_ATTR::#OFF FXMUX::F FXUSED::#OFF G:state_D<0>LogicTrst19_SW0:#LUT:D=(A4*(A1*A2)) GYMUX::G REVUSED::#OFF SRINV::#OFF SYNC_ATTR::#OFF XBUSED::#OFF XUSED::0 YBUSED::#OFF YUSED::0 " ; inst "u1/m6/m/m2/u1/Q" "SLICEL",placed CLB_X4Y4 SLICE_X7Y6 , cfg " BXINV::#OFF BYINV::BY CEINV::#OFF CLKINV::CLK COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DXMUX::#OFF DYMUX::0 F::#OFF F5USED::#OFF FFX::#OFF FFX_INIT_ATTR::#OFF FFX_SR_ATTR::#OFF FFY:u1/m6/m/m2/u1/Q:#FF FFY_INIT_ATTR::INIT0 FFY_SR_ATTR::SRLOW FXMUX::#OFF FXUSED::#OFF G::#OFF GYMUX::#OFF REVUSED::#OFF SRINV::#OFF SYNC_ATTR::ASYNC XBUSED::#OFF XUSED::#OFF YBUSED::#OFF YUSED::#OFF " ; inst "u1/m6/a1/u1/Q_int" "SLICEL",placed CLB_X3Y3 SLICE_X5Y5 , cfg " BXINV::#OFF BYINV::#OFF CEINV::#OFF CLKINV::CLK_B COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DXMUX::1 DYMUX::#OFF F:u1/m5/m3/En1:#LUT:D=(~A2*(~A4*A1)) F5USED::#OFF FFX:u1/m6/a1/u1/Q_int:#FF FFX_INIT_ATTR::INIT0 FFX_SR_ATTR::SRLOW FFY::#OFF FFY_INIT_ATTR::#OFF FFY_SR_ATTR::#OFF FXMUX::F FXUSED::#OFF G:u1/m5/m2/aL/En1:#LUT:D=(~A2*((~A1+(A1*A3))*A4)) GYMUX::G REVUSED::#OFF SRINV::#OFF SYNC_ATTR::ASYNC XBUSED::#OFF XUSED::0 YBUSED::#OFF YUSED::0 " ; inst "u1/Done_EthiRST7" "SLICEL",placed CLB_X14Y10 SLICE_X19Y18 , cfg " BXINV::#OFF BYINV::#OFF CEINV::#OFF CLKINV::#OFF COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DXMUX::#OFF DYMUX::#OFF F:u1/Done_EthiRST7:#LUT:D=(A1*(A2*(A3*A4))) F5USED::#OFF FFX::#OFF FFX_INIT_ATTR::#OFF FFX_SR_ATTR::#OFF FFY::#OFF FFY_INIT_ATTR::#OFF FFY_SR_ATTR::#OFF FXMUX::F FXUSED::#OFF G::#OFF GYMUX::#OFF REVUSED::#OFF SRINV::#OFF SYNC_ATTR::#OFF XBUSED::#OFF XUSED::0 YBUSED::#OFF YUSED::#OFF " ; inst "u1/p0/Working" "SLICEL",placed CLB_X16Y2 SLICE_X22Y2 , cfg " BXINV::BX BYINV::BY CEINV::CE CLKINV::CLK_B COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DXMUX::0 DYMUX::#OFF F::#OFF F5USED::#OFF FFX:u1/p0/Working:#FF FFX_INIT_ATTR::INIT0 FFX_SR_ATTR::SRLOW FFY::#OFF FFY_INIT_ATTR::#OFF FFY_SR_ATTR::#OFF FXMUX::#OFF FXUSED::#OFF G::#OFF GYMUX::#OFF REVUSED::0 SRINV::SR SYNC_ATTR::ASYNC XBUSED::#OFF XUSED::#OFF YBUSED::#OFF YUSED::#OFF " ; inst "u8/ByteCount_or0000" "SLICEL",placed CLB_X3Y10 SLICE_X4Y19 , cfg " BXINV::#OFF BYINV::#OFF CEINV::#OFF CLKINV::#OFF COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DXMUX::#OFF DYMUX::#OFF F::#OFF F5USED::#OFF FFX::#OFF FFX_INIT_ATTR::#OFF FFX_SR_ATTR::#OFF FFY::#OFF FFY_INIT_ATTR::#OFF FFY_SR_ATTR::#OFF FXMUX::#OFF FXUSED::#OFF G:u8/ByteCount_or00001:#LUT:D=(A1+A4) GYMUX::G REVUSED::#OFF SRINV::#OFF SYNC_ATTR::#OFF XBUSED::#OFF XUSED::#OFF YBUSED::#OFF YUSED::0 " ; inst "u7/u9/CycNum" "SLICEL",placed CLB_X6Y12 SLICE_X10Y23 , cfg " BXINV::#OFF BYINV::BY_B CEINV::CE CLKINV::CLK COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DXMUX::#OFF DYMUX::0 F::#OFF F5USED::#OFF FFX::#OFF FFX_INIT_ATTR::#OFF FFX_SR_ATTR::#OFF FFY:u7/u9/CycNum:#FF FFY_INIT_ATTR::INIT0 FFY_SR_ATTR::SRLOW FXMUX::#OFF FXUSED::#OFF G::#OFF GYMUX::#OFF REVUSED::#OFF SRINV::SR SYNC_ATTR::ASYNC XBUSED::#OFF XUSED::#OFF YBUSED::#OFF YUSED::#OFF " ; inst "u7/u8/u1/Q" "SLICEL",placed CLB_X13Y16 SLICE_X16Y30 , cfg " BXINV::#OFF BYINV::BY CEINV::#OFF CLKINV::CLK COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DXMUX::#OFF DYMUX::0 F::#OFF F5USED::#OFF FFX::#OFF FFX_INIT_ATTR::#OFF FFX_SR_ATTR::#OFF FFY:u7/u8/u1/Q:#FF FFY_INIT_ATTR::INIT0 FFY_SR_ATTR::SRLOW FXMUX::#OFF FXUSED::#OFF G::#OFF GYMUX::#OFF REVUSED::#OFF SRINV::#OFF SYNC_ATTR::ASYNC XBUSED::#OFF XUSED::#OFF YBUSED::#OFF YUSED::#OFF " ; inst "u7/u8/u2/Q" "SLICEL",placed CLB_X14Y15 SLICE_X19Y28 , cfg " BXINV::#OFF BYINV::BY CEINV::#OFF CLKINV::CLK COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DXMUX::#OFF DYMUX::0 F::#OFF F5USED::#OFF FFX::#OFF FFX_INIT_ATTR::#OFF FFX_SR_ATTR::#OFF FFY:u7/u8/u2/Q:#FF FFY_INIT_ATTR::INIT0 FFY_SR_ATTR::SRLOW FXMUX::#OFF FXUSED::#OFF G::#OFF GYMUX::#OFF REVUSED::#OFF SRINV::#OFF SYNC_ATTR::ASYNC XBUSED::#OFF XUSED::#OFF YBUSED::#OFF YUSED::#OFF " ; inst "u8/u5/Working" "SLICEL",placed CLB_X7Y9 SLICE_X13Y17 , cfg " BXINV::BX BYINV::BY CEINV::CE CLKINV::CLK_B COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DXMUX::0 DYMUX::#OFF F::#OFF F5USED::#OFF FFX:u8/u5/Working:#FF FFX_INIT_ATTR::INIT0 FFX_SR_ATTR::SRLOW FFY::#OFF FFY_INIT_ATTR::#OFF FFY_SR_ATTR::#OFF FXMUX::#OFF FXUSED::#OFF G::#OFF GYMUX::#OFF REVUSED::0 SRINV::SR SYNC_ATTR::ASYNC XBUSED::#OFF XUSED::#OFF YBUSED::#OFF YUSED::#OFF " ; inst "u1/Done_MAC" "SLICEL",placed CLB_X8Y9 SLICE_X15Y17 , cfg " BXINV::#OFF BYINV::#OFF CEINV::#OFF CLKINV::#OFF COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DXMUX::#OFF DYMUX::#OFF F:u1/m7/m3/En1:#LUT:D=(~A1*(~A4*A2)) F5USED::#OFF FFX::#OFF FFX_INIT_ATTR::#OFF FFX_SR_ATTR::#OFF FFY::#OFF FFY_INIT_ATTR::#OFF FFY_SR_ATTR::#OFF FXMUX::F FXUSED::#OFF G:u1/m7/m2/aL/En1:#LUT:D=(~A1*((~A2+(A2*A3))*A4)) GYMUX::G REVUSED::#OFF SRINV::#OFF SYNC_ATTR::#OFF XBUSED::#OFF XUSED::0 YBUSED::#OFF YUSED::0 " ; inst "u1/p5/Mcount_count_eqn_010" "SLICEL",placed CLB_X16Y6 SLICE_X23Y11 , cfg " BXINV::#OFF BYINV::#OFF CEINV::#OFF CLKINV::#OFF COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DXMUX::#OFF DYMUX::#OFF F:u1/p5/Mcount_count_eqn_010:#LUT:D=(A1*(A2*(A4*A3))) F5USED::#OFF FFX::#OFF FFX_INIT_ATTR::#OFF FFX_SR_ATTR::#OFF FFY::#OFF FFY_INIT_ATTR::#OFF FFY_SR_ATTR::#OFF FXMUX::F FXUSED::#OFF G:u1/p4/count_not00014:#LUT:D=(A1+(A2+(A4+A3))) GYMUX::G REVUSED::#OFF SRINV::#OFF SYNC_ATTR::#OFF XBUSED::#OFF XUSED::0 YBUSED::#OFF YUSED::0 " ; inst "u1/p5/Mcount_count_eqn_015" "SLICEL",placed CLB_X15Y7 SLICE_X21Y12 , cfg " BXINV::#OFF BYINV::#OFF CEINV::#OFF CLKINV::#OFF COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DXMUX::#OFF DYMUX::#OFF F:u1/p5/Mcount_count_eqn_015:#LUT:D=(A1*(A2*(A3*A4))) F5USED::#OFF FFX::#OFF FFX_INIT_ATTR::#OFF FFX_SR_ATTR::#OFF FFY::#OFF FFY_INIT_ATTR::#OFF FFY_SR_ATTR::#OFF FXMUX::F FXUSED::#OFF G:u1/p4/count_not00019:#LUT:D=(A1+(A2+(A3+A4))) GYMUX::G REVUSED::#OFF SRINV::#OFF SYNC_ATTR::#OFF XBUSED::#OFF XUSED::0 YBUSED::#OFF YUSED::0 " ; inst "u7/u5/A_addr<1>" "SLICEL",placed CLB_X3Y14 SLICE_X4Y26 , cfg " BXINV::BX BYINV::BY CEINV::CE CLKINV::CLK COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DXMUX::0 DYMUX::0 F::#OFF F5USED::#OFF FFX:u7/u5/A_addr_1:#FF FFX_INIT_ATTR::INIT0 FFX_SR_ATTR::SRLOW FFY:u7/u5/A_addr_0:#FF FFY_INIT_ATTR::INIT0 FFY_SR_ATTR::SRLOW FXMUX::#OFF FXUSED::#OFF G::#OFF GYMUX::#OFF REVUSED::#OFF SRINV::SR SYNC_ATTR::ASYNC XBUSED::#OFF XUSED::#OFF YBUSED::#OFF YUSED::#OFF " ; inst "u7/u5/A_addr<2>" "SLICEL",placed CLB_X3Y14 SLICE_X4Y27 , cfg " BXINV::#OFF BYINV::BY CEINV::CE CLKINV::CLK COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DXMUX::#OFF DYMUX::0 F::#OFF F5USED::#OFF FFX::#OFF FFX_INIT_ATTR::#OFF FFX_SR_ATTR::#OFF FFY:u7/u5/A_addr_2:#FF FFY_INIT_ATTR::INIT0 FFY_SR_ATTR::SRLOW FXMUX::#OFF FXUSED::#OFF G::#OFF GYMUX::#OFF REVUSED::#OFF SRINV::SR SYNC_ATTR::ASYNC XBUSED::#OFF XUSED::#OFF YBUSED::#OFF YUSED::#OFF " ; inst "u9/u2/SReg<1>" "SLICEL",placed CLB_X1Y7 SLICE_X1Y12 , cfg " BXINV::BX BYINV::BY CEINV::#OFF CLKINV::CLK COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DXMUX::0 DYMUX::1 F::#OFF F5USED::#OFF FFX:u9/u2/SReg_1:#FF FFX_INIT_ATTR::INIT0 FFX_SR_ATTR::SRLOW FFY:u9/u2/SReg_0:#FF FFY_INIT_ATTR::INIT0 FFY_SR_ATTR::SRLOW FXMUX::#OFF FXUSED::#OFF G:u0/u2/Mtridata_AD<1>_101.SLICEL_G:#LUT:D=0 GYMUX::G REVUSED::0 SRINV::SR SYNC_ATTR::ASYNC XBUSED::#OFF XUSED::#OFF YBUSED::#OFF YUSED::#OFF " ; inst "u9/u2/SReg<3>" "SLICEL",placed CLB_X2Y7 SLICE_X3Y12 , cfg " BXINV::BX BYINV::BY CEINV::#OFF CLKINV::CLK COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DXMUX::0 DYMUX::1 F::#OFF F5USED::#OFF FFX:u9/u2/SReg_3:#FF FFX_INIT_ATTR::INIT0 FFX_SR_ATTR::SRLOW FFY:u9/u2/SReg_2:#FF FFY_INIT_ATTR::INIT0 FFY_SR_ATTR::SRLOW FXMUX::#OFF FXUSED::#OFF G:u9/u2/SReg<1>_rt:#LUT:D=A2 _BEL_PROP::G:PK_PACKTHRU: GYMUX::G REVUSED::0 SRINV::SR SYNC_ATTR::ASYNC XBUSED::#OFF XUSED::#OFF YBUSED::#OFF YUSED::#OFF " ; inst "u9/u2/SReg<5>" "SLICEL",placed CLB_X2Y7 SLICE_X2Y12 , cfg " BXINV::BX BYINV::BY CEINV::#OFF CLKINV::CLK COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DXMUX::0 DYMUX::1 F::#OFF F5USED::#OFF FFX:u9/u2/SReg_5:#FF FFX_INIT_ATTR::INIT0 FFX_SR_ATTR::SRLOW FFY:u9/u2/SReg_4:#FF FFY_INIT_ATTR::INIT0 FFY_SR_ATTR::SRLOW FXMUX::#OFF FXUSED::#OFF G:u9/u2/SReg<3>_rt:#LUT:D=A2 _BEL_PROP::G:PK_PACKTHRU: GYMUX::G REVUSED::0 SRINV::SR SYNC_ATTR::ASYNC XBUSED::#OFF XUSED::#OFF YBUSED::#OFF YUSED::#OFF " ; inst "u1/p7/u3/u1/Q_int" "SLICEL",placed CLB_X8Y5 SLICE_X15Y8 , cfg " BXINV::#OFF BYINV::BY CEINV::#OFF CLKINV::CLK_B COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DXMUX::#OFF DYMUX::0 F::#OFF F5USED::#OFF FFX::#OFF FFX_INIT_ATTR::#OFF FFX_SR_ATTR::#OFF FFY:u1/p7/u3/u1/Q_int:#FF FFY_INIT_ATTR::INIT0 FFY_SR_ATTR::SRLOW FXMUX::#OFF FXUSED::#OFF G::#OFF GYMUX::#OFF REVUSED::#OFF SRINV::#OFF SYNC_ATTR::ASYNC XBUSED::#OFF XUSED::#OFF YBUSED::#OFF YUSED::#OFF " ; inst "u9/u2/SReg<7>" "SLICEL",placed CLB_X2Y7 SLICE_X2Y13 , cfg " BXINV::BX BYINV::BY CEINV::#OFF CLKINV::CLK COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DXMUX::0 DYMUX::1 F::#OFF F5USED::#OFF FFX:u9/u2/SReg_7:#FF FFX_INIT_ATTR::INIT0 FFX_SR_ATTR::SRLOW FFY:u9/u2/SReg_6:#FF FFY_INIT_ATTR::INIT0 FFY_SR_ATTR::SRLOW FXMUX::#OFF FXUSED::#OFF G:u9/u2/SReg<5>_rt:#LUT:D=A3 _BEL_PROP::G:PK_PACKTHRU: GYMUX::G REVUSED::0 SRINV::SR SYNC_ATTR::ASYNC XBUSED::#OFF XUSED::#OFF YBUSED::#OFF YUSED::#OFF " ; inst "u4/u2/u0/Q" "SLICEL",placed CLB_X14Y6 SLICE_X18Y11 , cfg " BXINV::#OFF BYINV::BY CEINV::#OFF CLKINV::CLK COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DXMUX::#OFF DYMUX::0 F::#OFF F5USED::#OFF FFX::#OFF FFX_INIT_ATTR::#OFF FFX_SR_ATTR::#OFF FFY:u4/u2/u0/Q:#FF FFY_INIT_ATTR::INIT0 FFY_SR_ATTR::SRLOW FXMUX::#OFF FXUSED::#OFF G::#OFF GYMUX::#OFF REVUSED::#OFF SRINV::#OFF SYNC_ATTR::ASYNC XBUSED::#OFF XUSED::#OFF YBUSED::#OFF YUSED::#OFF " ; inst "u9/u2/SReg<9>" "SLICEL",placed CLB_X2Y6 SLICE_X2Y10 , cfg " BXINV::BX BYINV::BY CEINV::#OFF CLKINV::CLK COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DXMUX::0 DYMUX::1 F::#OFF F5USED::#OFF FFX:u9/u2/SReg_9:#FF FFX_INIT_ATTR::INIT0 FFX_SR_ATTR::SRLOW FFY:u9/u2/SReg_8:#FF FFY_INIT_ATTR::INIT0 FFY_SR_ATTR::SRLOW FXMUX::#OFF FXUSED::#OFF G:u9/u2/SReg<7>_rt:#LUT:D=A2 _BEL_PROP::G:PK_PACKTHRU: GYMUX::G REVUSED::0 SRINV::SR SYNC_ATTR::ASYNC XBUSED::#OFF XUSED::#OFF YBUSED::#OFF YUSED::#OFF " ; inst "u8/u1/Qa" "SLICEL",placed CLB_X8Y8 SLICE_X14Y14 , cfg " BXINV::#OFF BYINV::BY CEINV::#OFF CLKINV::CLK_B COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DXMUX::#OFF DYMUX::0 F::#OFF F5USED::#OFF FFX::#OFF FFX_INIT_ATTR::#OFF FFX_SR_ATTR::#OFF FFY:u8/u1/Qa:#FF FFY_INIT_ATTR::INIT0 FFY_SR_ATTR::SRLOW FXMUX::#OFF FXUSED::#OFF G::#OFF GYMUX::#OFF REVUSED::#OFF SRINV::#OFF SYNC_ATTR::ASYNC XBUSED::#OFF XUSED::#OFF YBUSED::#OFF YUSED::#OFF _GND_SOURCE::X " ; inst "u8/u1/Qb" "SLICEL",placed CLB_X8Y9 SLICE_X14Y16 , cfg " BXINV::#OFF BYINV::BY CEINV::#OFF CLKINV::CLK COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DXMUX::#OFF DYMUX::0 F::#OFF F5USED::#OFF FFX::#OFF FFX_INIT_ATTR::#OFF FFX_SR_ATTR::#OFF FFY:u8/u1/Qb:#FF FFY_INIT_ATTR::INIT0 FFY_SR_ATTR::SRLOW FXMUX::#OFF FXUSED::#OFF G::#OFF GYMUX::#OFF REVUSED::#OFF SRINV::#OFF SYNC_ATTR::ASYNC XBUSED::#OFF XUSED::#OFF YBUSED::#OFF YUSED::#OFF _GND_SOURCE::X " ; inst "u6/Addr<1>" "SLICEL",placed CLB_X7Y12 SLICE_X12Y22 , cfg " BXINV::#OFF BYINV::BY_B CEINV::CE CLKINV::CLK_B COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DXMUX::1 DYMUX::0 F:u6/Mcount_Addr_xor<1>11:#LUT:D=(A3@A4) F5USED::#OFF FFX:u6/Addr_1:#FF FFX_INIT_ATTR::INIT1 FFX_SR_ATTR::SRHIGH FFY:u6/Addr_0:#FF FFY_INIT_ATTR::INIT1 FFY_SR_ATTR::SRHIGH FXMUX::F FXUSED::#OFF G:u6/stateEn_and0000_inv_SW0:#LUT:D=(A3+A4) GYMUX::G REVUSED::#OFF SRINV::SR SYNC_ATTR::ASYNC XBUSED::#OFF XUSED::#OFF YBUSED::#OFF YUSED::0 " ; inst "u7/u4/ff" "SLICEL",placed CLB_X4Y16 SLICE_X7Y31 , cfg " BXINV::#OFF BYINV::BY CEINV::CE CLKINV::CLK COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DXMUX::#OFF DYMUX::0 F::#OFF F5USED::#OFF FFX::#OFF FFX_INIT_ATTR::#OFF FFX_SR_ATTR::#OFF FFY:u7/u4/ff:#FF FFY_INIT_ATTR::INIT0 FFY_SR_ATTR::SRLOW FXMUX::#OFF FXUSED::#OFF G::#OFF GYMUX::#OFF REVUSED::#OFF SRINV::SR SYNC_ATTR::ASYNC XBUSED::#OFF XUSED::#OFF YBUSED::#OFF YUSED::#OFF " ; inst "u7/u1/count_not0001" "SLICEL",placed CLB_X3Y16 SLICE_X5Y30 , cfg " BXINV::#OFF BYINV::#OFF CEINV::#OFF CLKINV::#OFF COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DXMUX::#OFF DYMUX::#OFF F:u7/u1/count_not0001:#LUT:D=(A4+(A2+(A1+A3))) F5USED::#OFF FFX::#OFF FFX_INIT_ATTR::#OFF FFX_SR_ATTR::#OFF FFY::#OFF FFY_INIT_ATTR::#OFF FFY_SR_ATTR::#OFF FXMUX::F FXUSED::#OFF G:u7/u1/count_not0001_SW0:#LUT:D=(A4+(A3+(A2+~A1))) GYMUX::G REVUSED::#OFF SRINV::#OFF SYNC_ATTR::#OFF XBUSED::#OFF XUSED::0 YBUSED::#OFF YUSED::0 " ; inst "u1/m4/m2/aH/Working" "SLICEL",placed CLB_X1Y3 SLICE_X0Y5 , cfg " BXINV::BX BYINV::BY CEINV::CE CLKINV::CLK_B COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DXMUX::0 DYMUX::#OFF F::#OFF F5USED::#OFF FFX:u1/m4/m2/aH/Working:#FF FFX_INIT_ATTR::INIT0 FFX_SR_ATTR::SRLOW FFY::#OFF FFY_INIT_ATTR::#OFF FFY_SR_ATTR::#OFF FXMUX::#OFF FXUSED::#OFF G::#OFF GYMUX::#OFF REVUSED::0 SRINV::SR SYNC_ATTR::ASYNC XBUSED::#OFF XUSED::#OFF YBUSED::#OFF YUSED::#OFF " ; inst "u8/VoltData_10_and0000" "SLICEL",placed CLB_X3Y9 SLICE_X4Y16 , cfg " BXINV::#OFF BYINV::#OFF CEINV::#OFF CLKINV::#OFF COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DXMUX::#OFF DYMUX::#OFF F:u8/VoltData_10_and00001:#LUT:D=(~A2*(~A3*(~A1*A4))) F5USED::#OFF FFX::#OFF FFX_INIT_ATTR::#OFF FFX_SR_ATTR::#OFF FFY::#OFF FFY_INIT_ATTR::#OFF FFY_SR_ATTR::#OFF FXMUX::F FXUSED::#OFF G:u8/En_and00001_SW0:#LUT:D=(~A3+(~A1+A2)) GYMUX::G REVUSED::#OFF SRINV::#OFF SYNC_ATTR::#OFF XBUSED::#OFF XUSED::0 YBUSED::#OFF YUSED::0 " ; inst "u9/u2/SReg_14_and0000" "SLICEL",placed CLB_X2Y6 SLICE_X3Y11 , cfg " BXINV::#OFF BYINV::#OFF CEINV::#OFF CLKINV::#OFF COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DXMUX::#OFF DYMUX::#OFF F:u9/u2/SReg_14_and00001:#LUT:D=(~A1*(~A4*A2)) F5USED::#OFF FFX::#OFF FFX_INIT_ATTR::#OFF FFX_SR_ATTR::#OFF FFY::#OFF FFY_INIT_ATTR::#OFF FFY_SR_ATTR::#OFF FXMUX::F FXUSED::#OFF G:u9/u2/SReg_14_or00001:#LUT:D=((~A2*(~A4+(A1+A3)))+(A2*A1)) GYMUX::G REVUSED::#OFF SRINV::#OFF SYNC_ATTR::#OFF XBUSED::#OFF XUSED::0 YBUSED::#OFF YUSED::0 " ; inst "u1/p5/Mcount_count_eqn_05" "SLICEL",placed CLB_X16Y5 SLICE_X22Y9 , cfg " BXINV::#OFF BYINV::#OFF CEINV::#OFF CLKINV::#OFF COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DXMUX::#OFF DYMUX::#OFF F:u1/p5/Mcount_count_eqn_05:#LUT:D=(A1*(A2*(A4*A3))) F5USED::#OFF FFX::#OFF FFX_INIT_ATTR::#OFF FFX_SR_ATTR::#OFF FFY::#OFF FFY_INIT_ATTR::#OFF FFY_SR_ATTR::#OFF FXMUX::F FXUSED::#OFF G::#OFF GYMUX::#OFF REVUSED::#OFF SRINV::#OFF SYNC_ATTR::#OFF XBUSED::#OFF XUSED::0 YBUSED::#OFF YUSED::#OFF " ; inst "u4/u2/u0/Q_int" "SLICEL",placed CLB_X13Y6 SLICE_X16Y11 , cfg " BXINV::#OFF BYINV::BY CEINV::#OFF CLKINV::CLK_B COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DXMUX::#OFF DYMUX::0 F::#OFF F5USED::#OFF FFX::#OFF FFX_INIT_ATTR::#OFF FFX_SR_ATTR::#OFF FFY:u4/u2/u0/Q_int:#FF FFY_INIT_ATTR::INIT0 FFY_SR_ATTR::SRLOW FXMUX::#OFF FXUSED::#OFF G::#OFF GYMUX::#OFF REVUSED::#OFF SRINV::SR SYNC_ATTR::SYNC XBUSED::#OFF XUSED::#OFF YBUSED::#OFF YUSED::#OFF " ; inst "u1/m4/m2/aL/Working" "SLICEL",placed CLB_X1Y3 SLICE_X0Y4 , cfg " BXINV::BX BYINV::BY CEINV::CE CLKINV::CLK_B COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DXMUX::0 DYMUX::#OFF F::#OFF F5USED::#OFF FFX:u1/m4/m2/aL/Working:#FF FFX_INIT_ATTR::INIT0 FFX_SR_ATTR::SRLOW FFY::#OFF FFY_INIT_ATTR::#OFF FFY_SR_ATTR::#OFF FXMUX::#OFF FXUSED::#OFF G::#OFF GYMUX::#OFF REVUSED::0 SRINV::SR SYNC_ATTR::ASYNC XBUSED::#OFF XUSED::#OFF YBUSED::#OFF YUSED::#OFF _VCC_SOURCE::X " ; inst "u8/u3/u1/u1/Q" "SLICEL",placed CLB_X14Y9 SLICE_X19Y17 , cfg " BXINV::#OFF BYINV::BY CEINV::#OFF CLKINV::CLK COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DXMUX::#OFF DYMUX::0 F::#OFF F5USED::#OFF FFX::#OFF FFX_INIT_ATTR::#OFF FFX_SR_ATTR::#OFF FFY:u8/u3/u1/u1/Q:#FF FFY_INIT_ATTR::INIT0 FFY_SR_ATTR::SRLOW FXMUX::#OFF FXUSED::#OFF G::#OFF GYMUX::#OFF REVUSED::#OFF SRINV::#OFF SYNC_ATTR::ASYNC XBUSED::#OFF XUSED::#OFF YBUSED::#OFF YUSED::#OFF " ; inst "u1/m2/m2/u1/Q" "SLICEL",placed CLB_X6Y1 SLICE_X11Y0 , cfg " BXINV::#OFF BYINV::BY CEINV::#OFF CLKINV::CLK COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DXMUX::#OFF DYMUX::0 F::#OFF F5USED::#OFF FFX::#OFF FFX_INIT_ATTR::#OFF FFX_SR_ATTR::#OFF FFY:u1/m2/m2/u1/Q:#FF FFY_INIT_ATTR::INIT0 FFY_SR_ATTR::SRLOW FXMUX::#OFF FXUSED::#OFF G::#OFF GYMUX::#OFF REVUSED::#OFF SRINV::#OFF SYNC_ATTR::ASYNC XBUSED::#OFF XUSED::#OFF YBUSED::#OFF YUSED::#OFF " ; inst "u9/u2/SReg_18_and0000" "SLICEL",placed CLB_X7Y11 SLICE_X13Y20 , cfg " BXINV::#OFF BYINV::#OFF CEINV::#OFF CLKINV::#OFF COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DXMUX::#OFF DYMUX::#OFF F:u9/u2/SReg_18_and00001:#LUT:D=(~A4*(~A1*A3)) F5USED::#OFF FFX::#OFF FFX_INIT_ATTR::#OFF FFX_SR_ATTR::#OFF FFY::#OFF FFY_INIT_ATTR::#OFF FFY_SR_ATTR::#OFF FXMUX::F FXUSED::#OFF G:u9/u2/SReg_18_or00001:#LUT:D=((~A2*(~A3+(A4+A1)))+(A2*A4)) GYMUX::G REVUSED::#OFF SRINV::#OFF SYNC_ATTR::#OFF XBUSED::#OFF XUSED::0 YBUSED::#OFF YUSED::0 " ; inst "u8/MaskStage" "SLICEL",placed CLB_X3Y8 SLICE_X4Y14 , cfg " BXINV::BX BYINV::BY CEINV::CE CLKINV::CLK_B COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DXMUX::0 DYMUX::#OFF F::#OFF F5USED::#OFF FFX:u8/MaskStage:#FF FFX_INIT_ATTR::INIT0 FFX_SR_ATTR::SRLOW FFY::#OFF FFY_INIT_ATTR::#OFF FFY_SR_ATTR::#OFF FXMUX::#OFF FXUSED::#OFF G::#OFF GYMUX::#OFF REVUSED::0 SRINV::SR SYNC_ATTR::ASYNC XBUSED::#OFF XUSED::#OFF YBUSED::#OFF YUSED::#OFF " ; inst "u1/m6/b1/En" "SLICEL",placed CLB_X6Y7 SLICE_X10Y13 , cfg " BXINV::BX BYINV::BY CEINV::#OFF CLKINV::CLK_B COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DXMUX::0 DYMUX::#OFF F::#OFF F5USED::#OFF FFX:u1/m6/b1/En:#FF FFX_INIT_ATTR::INIT0 FFX_SR_ATTR::SRLOW FFY::#OFF FFY_INIT_ATTR::#OFF FFY_SR_ATTR::#OFF FXMUX::#OFF FXUSED::#OFF G::#OFF GYMUX::#OFF REVUSED::0 SRINV::SR SYNC_ATTR::ASYNC XBUSED::#OFF XUSED::#OFF YBUSED::#OFF YUSED::#OFF " ; inst "u1/p7/u0/Q" "SLICEL",placed CLB_X7Y3 SLICE_X13Y5 , cfg " BXINV::#OFF BYINV::BY CEINV::#OFF CLKINV::CLK COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DXMUX::#OFF DYMUX::0 F::#OFF F5USED::#OFF FFX::#OFF FFX_INIT_ATTR::#OFF FFX_SR_ATTR::#OFF FFY:u1/p7/u0/Q:#FF FFY_INIT_ATTR::INIT0 FFY_SR_ATTR::SRLOW FXMUX::#OFF FXUSED::#OFF G::#OFF GYMUX::#OFF REVUSED::#OFF SRINV::#OFF SYNC_ATTR::ASYNC XBUSED::#OFF XUSED::#OFF YBUSED::#OFF YUSED::#OFF " ; inst "u9/u2/LineOut_not0001_inv" "SLICEL",placed CLB_X13Y15 SLICE_X17Y28 , cfg " BXINV::#OFF BYINV::#OFF CEINV::#OFF CLKINV::#OFF COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DXMUX::#OFF DYMUX::#OFF F::#OFF F5USED::#OFF FFX::#OFF FFX_INIT_ATTR::#OFF FFX_SR_ATTR::#OFF FFY::#OFF FFY_INIT_ATTR::#OFF FFY_SR_ATTR::#OFF FXMUX::#OFF FXUSED::#OFF G:u9/u2/LineOut_or00001:#LUT:D=(A3+~A1) GYMUX::G REVUSED::#OFF SRINV::#OFF SYNC_ATTR::#OFF XBUSED::#OFF XUSED::#OFF YBUSED::#OFF YUSED::0 " ; inst "u7/u7/reg<4>" "SLICEL",placed CLB_X3Y15 SLICE_X5Y29 , cfg " BXINV::BX_B BYINV::#OFF CEINV::#OFF CLKINV::CLK COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DXMUX::0 DYMUX::1 F::#OFF F5USED::#OFF FFX:u7/u7/reg_4:#FF FFX_INIT_ATTR::INIT0 FFX_SR_ATTR::SRLOW FFY:u7/u7/reg_5:#FF FFY_INIT_ATTR::INIT0 FFY_SR_ATTR::SRLOW FXMUX::#OFF FXUSED::#OFF G:u7/u7/reg_5_mux00011:#LUT:D=(A2+~A1) GYMUX::G REVUSED::#OFF SRINV::SR SYNC_ATTR::ASYNC XBUSED::#OFF XUSED::#OFF YBUSED::#OFF YUSED::#OFF " ; inst "u1/m6/b2/En" "SLICEL",placed CLB_X4Y5 SLICE_X6Y9 , cfg " BXINV::BX BYINV::BY CEINV::#OFF CLKINV::CLK_B COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DXMUX::0 DYMUX::#OFF F::#OFF F5USED::#OFF FFX:u1/m6/b2/En:#FF FFX_INIT_ATTR::INIT0 FFX_SR_ATTR::SRLOW FFY::#OFF FFY_INIT_ATTR::#OFF FFY_SR_ATTR::#OFF FXMUX::#OFF FXUSED::#OFF G::#OFF GYMUX::#OFF REVUSED::0 SRINV::SR SYNC_ATTR::ASYNC XBUSED::#OFF XUSED::#OFF YBUSED::#OFF YUSED::#OFF " ; inst "u5/Go_Cyc14Step_inv12" "SLICEL",placed CLB_X16Y14 SLICE_X22Y27 , cfg " BXINV::#OFF BYINV::#OFF CEINV::#OFF CLKINV::#OFF COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DXMUX::#OFF DYMUX::#OFF F:u5/Go_Cyc14Step_inv12:#LUT:D=(A2+(A4+(A1+A3))) F5USED::#OFF FFX::#OFF FFX_INIT_ATTR::#OFF FFX_SR_ATTR::#OFF FFY::#OFF FFY_INIT_ATTR::#OFF FFY_SR_ATTR::#OFF FXMUX::F FXUSED::#OFF G:u5/Go_Cyc14Step_inv9:#LUT:D=(A1+(A3+(A4+A2))) GYMUX::G REVUSED::#OFF SRINV::#OFF SYNC_ATTR::#OFF XBUSED::#OFF XUSED::0 YBUSED::#OFF YUSED::0 " ; inst "u9/u4/Qa" "SLICEL",placed CLB_X3Y11 SLICE_X4Y20 , cfg " BXINV::#OFF BYINV::BY CEINV::#OFF CLKINV::CLK_B COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DXMUX::#OFF DYMUX::0 F::#OFF F5USED::#OFF FFX::#OFF FFX_INIT_ATTR::#OFF FFX_SR_ATTR::#OFF FFY:u9/u4/Qa:#FF FFY_INIT_ATTR::INIT0 FFY_SR_ATTR::SRLOW FXMUX::#OFF FXUSED::#OFF G::#OFF GYMUX::#OFF REVUSED::#OFF SRINV::SR SYNC_ATTR::SYNC XBUSED::#OFF XUSED::#OFF YBUSED::#OFF YUSED::#OFF " ; inst "u9/u4/Qb" "SLICEL",placed CLB_X3Y11 SLICE_X5Y20 , cfg " BXINV::#OFF BYINV::BY CEINV::#OFF CLKINV::CLK COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DXMUX::#OFF DYMUX::0 F::#OFF F5USED::#OFF FFX::#OFF FFX_INIT_ATTR::#OFF FFX_SR_ATTR::#OFF FFY:u9/u4/Qb:#FF FFY_INIT_ATTR::INIT0 FFY_SR_ATTR::SRLOW FXMUX::#OFF FXUSED::#OFF G::#OFF GYMUX::#OFF REVUSED::#OFF SRINV::#OFF SYNC_ATTR::ASYNC XBUSED::#OFF XUSED::#OFF YBUSED::#OFF YUSED::#OFF " ; inst "u8/lenregH/Data<0>" "SLICEL",placed CLB_X5Y9 SLICE_X8Y17 , cfg " BXINV::#OFF BYINV::BY CEINV::CE CLKINV::CLK_B COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DXMUX::#OFF DYMUX::0 F::#OFF F5USED::#OFF FFX::#OFF FFX_INIT_ATTR::#OFF FFX_SR_ATTR::#OFF FFY:u8/lenregH/Data_0:#FF FFY_INIT_ATTR::INIT0 FFY_SR_ATTR::SRLOW FXMUX::#OFF FXUSED::#OFF G::#OFF GYMUX::#OFF REVUSED::#OFF SRINV::SR SYNC_ATTR::ASYNC XBUSED::#OFF XUSED::#OFF YBUSED::#OFF YUSED::#OFF _GND_SOURCE::X " ; inst "u1/f1/Working" "SLICEL",placed CLB_X8Y6 SLICE_X15Y10 , cfg " BXINV::BX BYINV::BY CEINV::CE CLKINV::CLK_B COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DXMUX::0 DYMUX::#OFF F::#OFF F5USED::#OFF FFX:u1/f1/Working:#FF FFX_INIT_ATTR::INIT0 FFX_SR_ATTR::SRLOW FFY::#OFF FFY_INIT_ATTR::#OFF FFY_SR_ATTR::#OFF FXMUX::#OFF FXUSED::#OFF G::#OFF GYMUX::#OFF REVUSED::0 SRINV::SR SYNC_ATTR::ASYNC XBUSED::#OFF XUSED::#OFF YBUSED::#OFF YUSED::#OFF " ; inst "u8/Mtrien_DAC_D" "SLICEL",placed CLB_X4Y7 SLICE_X7Y13 , cfg " BXINV::#OFF BYINV::BY CEINV::#OFF CLKINV::CLK COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DXMUX::#OFF DYMUX::0 F::#OFF F5USED::#OFF FFX::#OFF FFX_INIT_ATTR::#OFF FFX_SR_ATTR::#OFF FFY:u8/Mtrien_DAC_D:#LATCH FFY_INIT_ATTR::INIT0 FFY_SR_ATTR::SRLOW FXMUX::#OFF FXUSED::#OFF G::#OFF GYMUX::#OFF REVUSED::#OFF SRINV::#OFF SYNC_ATTR::ASYNC XBUSED::#OFF XUSED::#OFF YBUSED::#OFF YUSED::#OFF " ; inst "u1/m2/m1/Working" "SLICEL",placed CLB_X7Y1 SLICE_X13Y1 , cfg " BXINV::BX BYINV::BY CEINV::CE CLKINV::CLK_B COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DXMUX::0 DYMUX::#OFF F::#OFF F5USED::#OFF FFX:u1/m2/m1/Working:#FF FFX_INIT_ATTR::INIT0 FFX_SR_ATTR::SRLOW FFY::#OFF FFY_INIT_ATTR::#OFF FFY_SR_ATTR::#OFF FXMUX::#OFF FXUSED::#OFF G::#OFF GYMUX::#OFF REVUSED::0 SRINV::SR SYNC_ATTR::ASYNC XBUSED::#OFF XUSED::#OFF YBUSED::#OFF YUSED::#OFF " ; inst "u9/u2/LineOut" "SLICEL",placed CLB_X13Y15 SLICE_X16Y29 , cfg " BXINV::#OFF BYINV::BY CEINV::#OFF CLKINV::CLK COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DXMUX::#OFF DYMUX::0 F::#OFF F5USED::#OFF FFX::#OFF FFX_INIT_ATTR::#OFF FFX_SR_ATTR::#OFF FFY:u9/u2/LineOut:#FF FFY_INIT_ATTR::INIT0 FFY_SR_ATTR::SRLOW FXMUX::#OFF FXUSED::#OFF G::#OFF GYMUX::#OFF REVUSED::#OFF SRINV::SR SYNC_ATTR::ASYNC XBUSED::#OFF XUSED::#OFF YBUSED::#OFF YUSED::#OFF " ; inst "u1/g3/u0/Q_int" "SLICEL",placed CLB_X8Y3 SLICE_X15Y4 , cfg " BXINV::#OFF BYINV::BY CEINV::#OFF CLKINV::CLK_B COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DXMUX::#OFF DYMUX::0 F::#OFF F5USED::#OFF FFX::#OFF FFX_INIT_ATTR::#OFF FFX_SR_ATTR::#OFF FFY:u1/g3/u0/Q_int:#FF FFY_INIT_ATTR::INIT0 FFY_SR_ATTR::SRLOW FXMUX::#OFF FXUSED::#OFF G::#OFF GYMUX::#OFF REVUSED::#OFF SRINV::SR SYNC_ATTR::SYNC XBUSED::#OFF XUSED::#OFF YBUSED::#OFF YUSED::#OFF " ; inst "u1/m3/m1/Working" "SLICEL",placed CLB_X4Y1 SLICE_X7Y1 , cfg " BXINV::BX BYINV::BY CEINV::CE CLKINV::CLK_B COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DXMUX::0 DYMUX::#OFF F::#OFF F5USED::#OFF FFX:u1/m3/m1/Working:#FF FFX_INIT_ATTR::INIT0 FFX_SR_ATTR::SRLOW FFY::#OFF FFY_INIT_ATTR::#OFF FFY_SR_ATTR::#OFF FXMUX::#OFF FXUSED::#OFF G::#OFF GYMUX::#OFF REVUSED::0 SRINV::SR SYNC_ATTR::ASYNC XBUSED::#OFF XUSED::#OFF YBUSED::#OFF YUSED::#OFF " ; inst "u1/g3/u2/u1/Q_int" "SLICEL",placed CLB_X7Y3 SLICE_X13Y4 , cfg " BXINV::#OFF BYINV::BY CEINV::#OFF CLKINV::CLK_B COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DXMUX::#OFF DYMUX::0 F::#OFF F5USED::#OFF FFX::#OFF FFX_INIT_ATTR::#OFF FFX_SR_ATTR::#OFF FFY:u1/g3/u2/u1/Q_int:#FF FFY_INIT_ATTR::INIT0 FFY_SR_ATTR::SRLOW FXMUX::#OFF FXUSED::#OFF G::#OFF GYMUX::#OFF REVUSED::#OFF SRINV::SR SYNC_ATTR::SYNC XBUSED::#OFF XUSED::#OFF YBUSED::#OFF YUSED::#OFF " ; inst "u2/ReadCount_or0000" "SLICEL",placed CLB_X7Y10 SLICE_X13Y19 , cfg " BXINV::#OFF BYINV::#OFF CEINV::#OFF CLKINV::#OFF COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DXMUX::#OFF DYMUX::#OFF F::#OFF F5USED::#OFF FFX::#OFF FFX_INIT_ATTR::#OFF FFX_SR_ATTR::#OFF FFY::#OFF FFY_INIT_ATTR::#OFF FFY_SR_ATTR::#OFF FXMUX::#OFF FXUSED::#OFF G:u2/ReadCount_or00001:#LUT:D=((~A1*~A3)+A2) GYMUX::G REVUSED::#OFF SRINV::#OFF SYNC_ATTR::#OFF XBUSED::#OFF XUSED::#OFF YBUSED::#OFF YUSED::0 " ; inst "u8/u3/u1/u1/Q_int" "SLICEL",placed CLB_X6Y9 SLICE_X11Y16 , cfg " BXINV::#OFF BYINV::#OFF CEINV::#OFF CLKINV::CLK_B COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DXMUX::1 DYMUX::#OFF F:u8/Go_Byte:#LUT:D=(((~A2*(A1+A3))+A2)*A4) F5USED::#OFF FFX:u8/u3/u1/u1/Q_int:#FF FFX_INIT_ATTR::INIT0 FFX_SR_ATTR::SRLOW FFY::#OFF FFY_INIT_ATTR::#OFF FFY_SR_ATTR::#OFF FXMUX::F FXUSED::#OFF G:u8/Go_Byte_SW0:#LUT:D=((~A2+(A2*A1))*A3) GYMUX::G REVUSED::#OFF SRINV::#OFF SYNC_ATTR::ASYNC XBUSED::#OFF XUSED::#OFF YBUSED::#OFF YUSED::0 " ; inst "u1/m4/m1/Working" "SLICEL",placed CLB_X2Y2 SLICE_X3Y3 , cfg " BXINV::BX BYINV::BY CEINV::CE CLKINV::CLK_B COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DXMUX::0 DYMUX::#OFF F::#OFF F5USED::#OFF FFX:u1/m4/m1/Working:#FF FFX_INIT_ATTR::INIT0 FFX_SR_ATTR::SRLOW FFY::#OFF FFY_INIT_ATTR::#OFF FFY_SR_ATTR::#OFF FXMUX::#OFF FXUSED::#OFF G::#OFF GYMUX::#OFF REVUSED::0 SRINV::SR SYNC_ATTR::ASYNC XBUSED::#OFF XUSED::#OFF YBUSED::#OFF YUSED::#OFF " ; inst "u1/p1/Working" "SLICEL",placed CLB_X15Y3 SLICE_X20Y5 , cfg " BXINV::BX BYINV::BY CEINV::CE CLKINV::CLK_B COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DXMUX::0 DYMUX::#OFF F::#OFF F5USED::#OFF FFX:u1/p1/Working:#FF FFX_INIT_ATTR::INIT0 FFX_SR_ATTR::SRLOW FFY::#OFF FFY_INIT_ATTR::#OFF FFY_SR_ATTR::#OFF FXMUX::#OFF FXUSED::#OFF G::#OFF GYMUX::#OFF REVUSED::0 SRINV::SR SYNC_ATTR::ASYNC XBUSED::#OFF XUSED::#OFF YBUSED::#OFF YUSED::#OFF " ; inst "u8/l2/u1/Q_int" "SLICEL",placed CLB_X5Y6 SLICE_X9Y11 , cfg " BXINV::#OFF BYINV::BY CEINV::#OFF CLKINV::CLK_B COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DXMUX::#OFF DYMUX::0 F::#OFF F5USED::#OFF FFX::#OFF FFX_INIT_ATTR::#OFF FFX_SR_ATTR::#OFF FFY:u8/l2/u1/Q_int:#FF FFY_INIT_ATTR::INIT0 FFY_SR_ATTR::SRLOW FXMUX::#OFF FXUSED::#OFF G::#OFF GYMUX::#OFF REVUSED::#OFF SRINV::#OFF SYNC_ATTR::ASYNC XBUSED::#OFF XUSED::#OFF YBUSED::#OFF YUSED::#OFF " ; inst "u8/Addr_and0000" "SLICEL",placed CLB_X5Y10 SLICE_X8Y19 , cfg " BXINV::#OFF BYINV::#OFF CEINV::#OFF CLKINV::#OFF COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DXMUX::#OFF DYMUX::#OFF F::#OFF F5USED::#OFF FFX::#OFF FFX_INIT_ATTR::#OFF FFX_SR_ATTR::#OFF FFY::#OFF FFY_INIT_ATTR::#OFF FFY_SR_ATTR::#OFF FXMUX::#OFF FXUSED::#OFF G:u8/Addr_and00001:#LUT:D=(~A4*(A1*(~A2*A3))) GYMUX::G REVUSED::#OFF SRINV::#OFF SYNC_ATTR::#OFF XBUSED::#OFF XUSED::#OFF YBUSED::#OFF YUSED::0 " ; inst "u4/u2/u2/u1/Q_int" "SLICEL",placed CLB_X14Y6 SLICE_X19Y11 , cfg " BXINV::#OFF BYINV::BY CEINV::#OFF CLKINV::CLK_B COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DXMUX::#OFF DYMUX::0 F::#OFF F5USED::#OFF FFX::#OFF FFX_INIT_ATTR::#OFF FFX_SR_ATTR::#OFF FFY:u4/u2/u2/u1/Q_int:#FF FFY_INIT_ATTR::INIT0 FFY_SR_ATTR::SRLOW FXMUX::#OFF FXUSED::#OFF G::#OFF GYMUX::#OFF REVUSED::#OFF SRINV::SR SYNC_ATTR::SYNC XBUSED::#OFF XUSED::#OFF YBUSED::#OFF YUSED::#OFF " ; inst "u1/m5/m1/Working" "SLICEL",placed CLB_X1Y4 SLICE_X0Y7 , cfg " BXINV::BX BYINV::BY CEINV::CE CLKINV::CLK_B COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DXMUX::0 DYMUX::#OFF F::#OFF F5USED::#OFF FFX:u1/m5/m1/Working:#FF FFX_INIT_ATTR::INIT0 FFX_SR_ATTR::SRLOW FFY::#OFF FFY_INIT_ATTR::#OFF FFY_SR_ATTR::#OFF FXMUX::#OFF FXUSED::#OFF G::#OFF GYMUX::#OFF REVUSED::0 SRINV::SR SYNC_ATTR::ASYNC XBUSED::#OFF XUSED::#OFF YBUSED::#OFF YUSED::#OFF " ; inst "u1/m6/WordCount<0>" "SLICEL",placed CLB_X5Y4 SLICE_X8Y7 , cfg " BXINV::BX_B BYINV::#OFF CEINV::#OFF CLKINV::CLK COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DXMUX::0 DYMUX::1 F:u1/m6/m/m3/En1_SW0:#LUT:D=(A2+A4) F5USED::#OFF FFX:u1/m6/WordCount_0:#FF FFX_INIT_ATTR::INIT0 FFX_SR_ATTR::SRLOW FFY:u1/m6/WordCount_1:#FF FFY_INIT_ATTR::INIT1 FFY_SR_ATTR::SRHIGH FXMUX::F FXUSED::#OFF G:u1/m6/Mcount_WordCount_xor<1>11:#LUT:D=(A4@~A3) GYMUX::G REVUSED::#OFF SRINV::SR SYNC_ATTR::ASYNC XBUSED::#OFF XUSED::0 YBUSED::#OFF YUSED::#OFF " ; inst "u1/p9/Working" "SLICEL",placed CLB_X14Y2 SLICE_X18Y2 , cfg " BXINV::BX BYINV::BY CEINV::CE CLKINV::CLK_B COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DXMUX::0 DYMUX::#OFF F::#OFF F5USED::#OFF FFX:u1/p9/Working:#FF FFX_INIT_ATTR::INIT0 FFX_SR_ATTR::SRLOW FFY::#OFF FFY_INIT_ATTR::#OFF FFY_SR_ATTR::#OFF FXMUX::#OFF FXUSED::#OFF G::#OFF GYMUX::#OFF REVUSED::0 SRINV::SR SYNC_ATTR::ASYNC XBUSED::#OFF XUSED::#OFF YBUSED::#OFF YUSED::#OFF " ; inst "u1/Done_Hash1" "SLICEL",placed CLB_X8Y6 SLICE_X14Y10 , cfg " BXINV::#OFF BYINV::#OFF CEINV::#OFF CLKINV::#OFF COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DXMUX::#OFF DYMUX::#OFF F:u1/f2/En1:#LUT:D=(~A3*(~A4*A1)) F5USED::#OFF FFX::#OFF FFX_INIT_ATTR::#OFF FFX_SR_ATTR::#OFF FFY::#OFF FFY_INIT_ATTR::#OFF FFY_SR_ATTR::#OFF FXMUX::F FXUSED::#OFF G:u1/f1/En1:#LUT:D=(~A3*((~A2+(A2*A4))*A1)) GYMUX::G REVUSED::#OFF SRINV::#OFF SYNC_ATTR::#OFF XBUSED::#OFF XUSED::0 YBUSED::#OFF YUSED::0 " ; inst "u7/u8/Wr_int" "SLICEL",placed CLB_X4Y14 SLICE_X7Y26 , cfg " BXINV::#OFF BYINV::#OFF CEINV::CE CLKINV::CLK COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DXMUX::1 DYMUX::#OFF F:u7/u8/Wr_int_mux000366:#LUT:D=(A4*(A3+(A1@A2))) F5USED::#OFF FFX:u7/u8/Wr_int:#FF FFX_INIT_ATTR::INIT0 FFX_SR_ATTR::SRLOW FFY::#OFF FFY_INIT_ATTR::#OFF FFY_SR_ATTR::#OFF FXMUX::F FXUSED::#OFF G:u7/u8/Wr_int_mux000366_SW0:#LUT:D=((A2@A4)+(A1@A3)) GYMUX::G REVUSED::#OFF SRINV::SR SYNC_ATTR::ASYNC XBUSED::#OFF XUSED::#OFF YBUSED::#OFF YUSED::0 " ; inst "u1/m5/m2/aH/Working" "SLICEL",placed CLB_X3Y4 SLICE_X4Y6 , cfg " BXINV::BX BYINV::BY CEINV::CE CLKINV::CLK_B COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DXMUX::0 DYMUX::#OFF F::#OFF F5USED::#OFF FFX:u1/m5/m2/aH/Working:#FF FFX_INIT_ATTR::INIT0 FFX_SR_ATTR::SRLOW FFY::#OFF FFY_INIT_ATTR::#OFF FFY_SR_ATTR::#OFF FXMUX::#OFF FXUSED::#OFF G::#OFF GYMUX::#OFF REVUSED::0 SRINV::SR SYNC_ATTR::ASYNC XBUSED::#OFF XUSED::#OFF YBUSED::#OFF YUSED::#OFF " ; inst "u1/m6/a1/u1/Q" "SLICEL",placed CLB_X4Y3 SLICE_X7Y4 , cfg " BXINV::#OFF BYINV::BY CEINV::#OFF CLKINV::CLK COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DXMUX::#OFF DYMUX::0 F::#OFF F5USED::#OFF FFX::#OFF FFX_INIT_ATTR::#OFF FFX_SR_ATTR::#OFF FFY:u1/m6/a1/u1/Q:#FF FFY_INIT_ATTR::INIT0 FFY_SR_ATTR::SRLOW FXMUX::#OFF FXUSED::#OFF G::#OFF GYMUX::#OFF REVUSED::#OFF SRINV::#OFF SYNC_ATTR::ASYNC XBUSED::#OFF XUSED::#OFF YBUSED::#OFF YUSED::#OFF " ; inst "u1/m6/m/m1/Working" "SLICEL",placed CLB_X4Y4 SLICE_X6Y6 , cfg " BXINV::BX BYINV::BY CEINV::CE CLKINV::CLK_B COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DXMUX::0 DYMUX::#OFF F::#OFF F5USED::#OFF FFX:u1/m6/m/m1/Working:#FF FFX_INIT_ATTR::INIT0 FFX_SR_ATTR::SRLOW FFY::#OFF FFY_INIT_ATTR::#OFF FFY_SR_ATTR::#OFF FXMUX::#OFF FXUSED::#OFF G::#OFF GYMUX::#OFF REVUSED::0 SRINV::SR SYNC_ATTR::ASYNC XBUSED::#OFF XUSED::#OFF YBUSED::#OFF YUSED::#OFF " ; inst "r1/state<0>" "SLICEL",placed CLB_X8Y10 SLICE_X15Y19 , cfg " BXINV::#OFF BYINV::BY CEINV::#OFF CLKINV::CLK_B COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DXMUX::1 DYMUX::0 F:state_D<0>LogicTrst132:#LUT:D=(A1+(A2+(A3+A4))) F5USED::#OFF FFX:r1/state_0:#FF FFX_INIT_ATTR::INIT0 FFX_SR_ATTR::SRLOW FFY:r1/state_1:#FF FFY_INIT_ATTR::INIT0 FFY_SR_ATTR::SRLOW FXMUX::F FXUSED::#OFF G:u1/f3/En1:#LUT:D=((~A2*~A3)+(A2*((~A3*(~A1+A4))+(A3*(~A1*~A4))))) GYMUX::G REVUSED::#OFF SRINV::SR SYNC_ATTR::ASYNC XBUSED::#OFF XUSED::#OFF YBUSED::#OFF YUSED::0 " ; inst "u1/m5/m2/aL/Working" "SLICEL",placed CLB_X3Y3 SLICE_X5Y4 , cfg " BXINV::BX BYINV::BY CEINV::CE CLKINV::CLK_B COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DXMUX::0 DYMUX::#OFF F::#OFF F5USED::#OFF FFX:u1/m5/m2/aL/Working:#FF FFX_INIT_ATTR::INIT0 FFX_SR_ATTR::SRLOW FFY::#OFF FFY_INIT_ATTR::#OFF FFY_SR_ATTR::#OFF FXMUX::#OFF FXUSED::#OFF G::#OFF GYMUX::#OFF REVUSED::0 SRINV::SR SYNC_ATTR::ASYNC XBUSED::#OFF XUSED::#OFF YBUSED::#OFF YUSED::#OFF " ; inst "u1/m7/m1/Working" "SLICEL",placed CLB_X5Y5 SLICE_X9Y9 , cfg " BXINV::BX BYINV::BY CEINV::CE CLKINV::CLK_B COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DXMUX::0 DYMUX::#OFF F::#OFF F5USED::#OFF FFX:u1/m7/m1/Working:#FF FFX_INIT_ATTR::INIT0 FFX_SR_ATTR::SRLOW FFY::#OFF FFY_INIT_ATTR::#OFF FFY_SR_ATTR::#OFF FXMUX::#OFF FXUSED::#OFF G::#OFF GYMUX::#OFF REVUSED::0 SRINV::SR SYNC_ATTR::ASYNC XBUSED::#OFF XUSED::#OFF YBUSED::#OFF YUSED::#OFF " ; inst "u1/p5/count<0>" "SLICEL",placed CLB_X16Y7 SLICE_X23Y12 , cfg " BXINV::#OFF BYINV::#OFF CEINV::#OFF CLKINV::CLK COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DXMUX::1 DYMUX::#OFF F:u1/p5/Mcount_count_eqn_050:#LUT:D=((~A3*A4)+(A3*A1)) F5USED::#OFF FFX:u1/p5/count_0:#FF FFX_INIT_ATTR::INIT0 FFX_SR_ATTR::SRLOW FFY::#OFF FFY_INIT_ATTR::#OFF FFY_SR_ATTR::#OFF FXMUX::F FXUSED::#OFF G:u1/p5/Mcount_count_eqn_024:#LUT:D=(A1*(A4*A2)) GYMUX::G REVUSED::#OFF SRINV::SR SYNC_ATTR::ASYNC XBUSED::#OFF XUSED::#OFF YBUSED::#OFF YUSED::0 " ; inst "u7/u2/Q_int" "SLICEL",placed CLB_X1Y13 SLICE_X0Y24 , cfg " BXINV::#OFF BYINV::BY CEINV::#OFF CLKINV::CLK_B COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DXMUX::#OFF DYMUX::0 F::#OFF F5USED::#OFF FFX::#OFF FFX_INIT_ATTR::#OFF FFX_SR_ATTR::#OFF FFY:u7/u2/Q_int:#FF FFY_INIT_ATTR::INIT0 FFY_SR_ATTR::SRLOW FXMUX::#OFF FXUSED::#OFF G::#OFF GYMUX::#OFF REVUSED::#OFF SRINV::#OFF SYNC_ATTR::ASYNC XBUSED::#OFF XUSED::#OFF YBUSED::#OFF YUSED::#OFF " ; inst "u1/m3/m2/u1/Q" "SLICEL",placed CLB_X3Y1 SLICE_X5Y1 , cfg " BXINV::#OFF BYINV::BY CEINV::#OFF CLKINV::CLK COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DXMUX::#OFF DYMUX::0 F::#OFF F5USED::#OFF FFX::#OFF FFX_INIT_ATTR::#OFF FFX_SR_ATTR::#OFF FFY:u1/m3/m2/u1/Q:#FF FFY_INIT_ATTR::INIT0 FFY_SR_ATTR::SRLOW FXMUX::#OFF FXUSED::#OFF G::#OFF GYMUX::#OFF REVUSED::#OFF SRINV::#OFF SYNC_ATTR::ASYNC XBUSED::#OFF XUSED::#OFF YBUSED::#OFF YUSED::#OFF " ; inst "u1/m7/m2/u1/Q" "SLICEL",placed CLB_X8Y9 SLICE_X15Y16 , cfg " BXINV::#OFF BYINV::BY CEINV::#OFF CLKINV::CLK COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DXMUX::#OFF DYMUX::0 F::#OFF F5USED::#OFF FFX::#OFF FFX_INIT_ATTR::#OFF FFX_SR_ATTR::#OFF FFY:u1/m7/m2/u1/Q:#FF FFY_INIT_ATTR::INIT0 FFY_SR_ATTR::SRLOW FXMUX::#OFF FXUSED::#OFF G::#OFF GYMUX::#OFF REVUSED::#OFF SRINV::#OFF SYNC_ATTR::ASYNC XBUSED::#OFF XUSED::#OFF YBUSED::#OFF YUSED::#OFF " ; inst "u1/Eth_iRst_or0000_inv" "SLICEL",placed CLB_X14Y10 SLICE_X19Y19 , cfg " BXINV::#OFF BYINV::#OFF CEINV::#OFF CLKINV::#OFF COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DXMUX::#OFF DYMUX::#OFF F:u1/Eth_iRst_or0000_inv1:#LUT:D=((~A1+(A1*~A2))*A4) F5USED::#OFF FFX::#OFF FFX_INIT_ATTR::#OFF FFX_SR_ATTR::#OFF FFY::#OFF FFY_INIT_ATTR::#OFF FFY_SR_ATTR::#OFF FXMUX::F FXUSED::#OFF G:u1/Eth_iRst_or0000_inv2:#LUT:D=(~A3*(~A4*(~A1*~A2))) GYMUX::G REVUSED::#OFF SRINV::#OFF SYNC_ATTR::#OFF XBUSED::#OFF XUSED::0 YBUSED::#OFF YUSED::0 " ; inst "u1/p7/u0/Q_int" "SLICEL",placed CLB_X8Y3 SLICE_X14Y4 , cfg " BXINV::#OFF BYINV::BY CEINV::#OFF CLKINV::CLK_B COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DXMUX::#OFF DYMUX::0 F::#OFF F5USED::#OFF FFX::#OFF FFX_INIT_ATTR::#OFF FFX_SR_ATTR::#OFF FFY:u1/p7/u0/Q_int:#FF FFY_INIT_ATTR::INIT0 FFY_SR_ATTR::SRLOW FXMUX::#OFF FXUSED::#OFF G::#OFF GYMUX::#OFF REVUSED::#OFF SRINV::SR SYNC_ATTR::SYNC XBUSED::#OFF XUSED::#OFF YBUSED::#OFF YUSED::#OFF " ; inst "u7/u8/u1/Q_int" "SLICEL",placed CLB_X13Y16 SLICE_X17Y30 , cfg " BXINV::#OFF BYINV::BY CEINV::#OFF CLKINV::CLK_B COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DXMUX::#OFF DYMUX::0 F::#OFF F5USED::#OFF FFX::#OFF FFX_INIT_ATTR::#OFF FFX_SR_ATTR::#OFF FFY:u7/u8/u1/Q_int:#FF FFY_INIT_ATTR::INIT0 FFY_SR_ATTR::SRLOW FXMUX::#OFF FXUSED::#OFF G::#OFF GYMUX::#OFF REVUSED::#OFF SRINV::#OFF SYNC_ATTR::ASYNC XBUSED::#OFF XUSED::#OFF YBUSED::#OFF YUSED::#OFF " ; inst "u1/m6/b1/u1/Q" "SLICEL",placed CLB_X6Y6 SLICE_X10Y10 , cfg " BXINV::#OFF BYINV::BY CEINV::#OFF CLKINV::CLK COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DXMUX::#OFF DYMUX::0 F::#OFF F5USED::#OFF FFX::#OFF FFX_INIT_ATTR::#OFF FFX_SR_ATTR::#OFF FFY:u1/m6/b1/u1/Q:#FF FFY_INIT_ATTR::INIT0 FFY_SR_ATTR::SRLOW FXMUX::#OFF FXUSED::#OFF G::#OFF GYMUX::#OFF REVUSED::#OFF SRINV::#OFF SYNC_ATTR::ASYNC XBUSED::#OFF XUSED::#OFF YBUSED::#OFF YUSED::#OFF " ; inst "u8/Addr<0>" "SLICEL",placed CLB_X4Y7 SLICE_X6Y12 , cfg " BXINV::BX_B BYINV::#OFF CEINV::CE CLKINV::CLK COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DXMUX::0 DYMUX::1 F::#OFF F5USED::#OFF FFX:u8/Addr_0:#FF FFX_INIT_ATTR::INIT1 FFX_SR_ATTR::SRHIGH FFY:u8/Addr_1:#FF FFY_INIT_ATTR::INIT1 FFY_SR_ATTR::SRHIGH FXMUX::#OFF FXUSED::#OFF G:u8/Mcount_Addr_xor<1>11:#LUT:D=(A2@A1) GYMUX::G REVUSED::#OFF SRINV::SR SYNC_ATTR::ASYNC XBUSED::#OFF XUSED::#OFF YBUSED::#OFF YUSED::#OFF " ; inst "u1/Done_SelfInit" "SLICEL",placed CLB_X14Y3 SLICE_X19Y4 , cfg " BXINV::#OFF BYINV::#OFF CEINV::#OFF CLKINV::#OFF COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DXMUX::#OFF DYMUX::#OFF F:u1/g3/Done1:#LUT:D=(~A2*A3) F5USED::#OFF FFX::#OFF FFX_INIT_ATTR::#OFF FFX_SR_ATTR::#OFF FFY::#OFF FFY_INIT_ATTR::#OFF FFY_SR_ATTR::#OFF FXMUX::F FXUSED::#OFF G:u1/i1/En1:#LUT:D=(~A4*((~A1+(A1*A2))*A3)) GYMUX::G REVUSED::#OFF SRINV::#OFF SYNC_ATTR::#OFF XBUSED::#OFF XUSED::0 YBUSED::#OFF YUSED::0 " ; inst "u1/g1/Qb" "SLICEL",placed CLB_X14Y12 SLICE_X19Y23 , cfg " BXINV::#OFF BYINV::BY CEINV::#OFF CLKINV::CLK COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DXMUX::#OFF DYMUX::0 F::#OFF F5USED::#OFF FFX::#OFF FFX_INIT_ATTR::#OFF FFX_SR_ATTR::#OFF FFY:u1/g1/Qb:#FF FFY_INIT_ATTR::INIT0 FFY_SR_ATTR::SRLOW FXMUX::#OFF FXUSED::#OFF G::#OFF GYMUX::#OFF REVUSED::#OFF SRINV::#OFF SYNC_ATTR::ASYNC XBUSED::#OFF XUSED::#OFF YBUSED::#OFF YUSED::#OFF " ; inst "u1/p7/u2/u1/Q" "SLICEL",placed CLB_X6Y5 SLICE_X11Y8 , cfg " BXINV::#OFF BYINV::BY CEINV::#OFF CLKINV::CLK COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DXMUX::#OFF DYMUX::0 F::#OFF F5USED::#OFF FFX::#OFF FFX_INIT_ATTR::#OFF FFX_SR_ATTR::#OFF FFY:u1/p7/u2/u1/Q:#FF FFY_INIT_ATTR::INIT0 FFY_SR_ATTR::SRLOW FXMUX::#OFF FXUSED::#OFF G::#OFF GYMUX::#OFF REVUSED::#OFF SRINV::#OFF SYNC_ATTR::ASYNC XBUSED::#OFF XUSED::#OFF YBUSED::#OFF YUSED::#OFF " ; inst "u1/g3/En" "SLICEL",placed CLB_X14Y5 SLICE_X19Y8 , cfg " BXINV::BX BYINV::BY CEINV::#OFF CLKINV::CLK COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DXMUX::0 DYMUX::#OFF F::#OFF F5USED::#OFF FFX:u1/g3/En:#FF FFX_INIT_ATTR::INIT0 FFX_SR_ATTR::SRLOW FFY::#OFF FFY_INIT_ATTR::#OFF FFY_SR_ATTR::#OFF FXMUX::#OFF FXUSED::#OFF G::#OFF GYMUX::#OFF REVUSED::0 SRINV::SR SYNC_ATTR::ASYNC XBUSED::#OFF XUSED::#OFF YBUSED::#OFF YUSED::#OFF " ; inst "u1/m7/m2/u1/Q_int" "SLICEL",placed CLB_X5Y4 SLICE_X8Y6 , cfg " BXINV::#OFF BYINV::#OFF CEINV::#OFF CLKINV::CLK_B COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DXMUX::1 DYMUX::#OFF F:u1/m7/m1/En1:#LUT:D=(~A3*(A2*~A4)) F5USED::#OFF FFX:u1/m7/m2/u1/Q_int:#FF FFX_INIT_ATTR::INIT0 FFX_SR_ATTR::SRLOW FFY::#OFF FFY_INIT_ATTR::#OFF FFY_SR_ATTR::#OFF FXMUX::F FXUSED::#OFF G:u1/m6/Done1:#LUT:D=(~A1*(~A3*(A4*~A2))) GYMUX::G REVUSED::#OFF SRINV::#OFF SYNC_ATTR::ASYNC XBUSED::#OFF XUSED::0 YBUSED::#OFF YUSED::0 " ; inst "u1/Done_p1" "SLICEL",placed CLB_X15Y3 SLICE_X21Y4 , cfg " BXINV::#OFF BYINV::#OFF CEINV::#OFF CLKINV::#OFF COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DXMUX::#OFF DYMUX::#OFF F:u1/p1/En1:#LUT:D=(~A2*((~A1+(A1*A3))*A4)) F5USED::#OFF FFX::#OFF FFX_INIT_ATTR::#OFF FFX_SR_ATTR::#OFF FFY::#OFF FFY_INIT_ATTR::#OFF FFY_SR_ATTR::#OFF FXMUX::F FXUSED::#OFF G:u1/i2/En1:#LUT:D=(~A1*((~A3+(A3*A2))*A4)) GYMUX::G REVUSED::#OFF SRINV::#OFF SYNC_ATTR::#OFF XBUSED::#OFF XUSED::0 YBUSED::#OFF YUSED::0 " ; inst "u1/m6/b2/u1/Q" "SLICEL",placed CLB_X4Y7 SLICE_X7Y12 , cfg " BXINV::#OFF BYINV::BY CEINV::#OFF CLKINV::CLK COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DXMUX::#OFF DYMUX::0 F::#OFF F5USED::#OFF FFX::#OFF FFX_INIT_ATTR::#OFF FFX_SR_ATTR::#OFF FFY:u1/m6/b2/u1/Q:#FF FFY_INIT_ATTR::INIT0 FFY_SR_ATTR::SRLOW FXMUX::#OFF FXUSED::#OFF G::#OFF GYMUX::#OFF REVUSED::#OFF SRINV::#OFF SYNC_ATTR::ASYNC XBUSED::#OFF XUSED::#OFF YBUSED::#OFF YUSED::#OFF " ; inst "u1/p7/u3/u1/Q" "SLICEL",placed CLB_X13Y5 SLICE_X16Y8 , cfg " BXINV::#OFF BYINV::BY CEINV::#OFF CLKINV::CLK COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DXMUX::#OFF DYMUX::0 F::#OFF F5USED::#OFF FFX::#OFF FFX_INIT_ATTR::#OFF FFX_SR_ATTR::#OFF FFY:u1/p7/u3/u1/Q:#FF FFY_INIT_ATTR::INIT0 FFY_SR_ATTR::SRLOW FXMUX::#OFF FXUSED::#OFF G::#OFF GYMUX::#OFF REVUSED::#OFF SRINV::#OFF SYNC_ATTR::ASYNC XBUSED::#OFF XUSED::#OFF YBUSED::#OFF YUSED::#OFF " ; inst "u1/g2/count<4>" "SLICEL",placed CLB_X14Y10 SLICE_X18Y18 , cfg " BXINV::#OFF BYINV::#OFF CEINV::CE CLKINV::CLK COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DXMUX::1 DYMUX::#OFF F:u1/g2/Mcount_count42:#LUT:D=(A2@~A4) F5USED::#OFF FFX:u1/g2/count_4:#FF FFX_INIT_ATTR::INIT0 FFX_SR_ATTR::SRLOW FFY::#OFF FFY_INIT_ATTR::#OFF FFY_SR_ATTR::#OFF FXMUX::F FXUSED::#OFF G:u1/g2/Mcount_count411:#LUT:D=(~A1+(~A4+(~A3+~A2))) GYMUX::G REVUSED::#OFF SRINV::SR SYNC_ATTR::ASYNC XBUSED::#OFF XUSED::#OFF YBUSED::#OFF YUSED::0 " ; inst "state_D<0>LogicTrst40" "SLICEL",placed CLB_X16Y14 SLICE_X22Y26 , cfg " BXINV::#OFF BYINV::#OFF CEINV::#OFF CLKINV::#OFF COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DXMUX::#OFF DYMUX::#OFF F:state_D<0>LogicTrst40:#LUT:D=(~A1*(~A2*(~A3*~A4))) F5USED::#OFF FFX::#OFF FFX_INIT_ATTR::#OFF FFX_SR_ATTR::#OFF FFY::#OFF FFY_INIT_ATTR::#OFF FFY_SR_ATTR::#OFF FXMUX::F FXUSED::#OFF G::#OFF GYMUX::#OFF REVUSED::#OFF SRINV::#OFF SYNC_ATTR::#OFF XBUSED::#OFF XUSED::0 YBUSED::#OFF YUSED::#OFF " ; inst "u2/Done_Skip" "SLICEL",placed CLB_X8Y10 SLICE_X14Y19 , cfg " BXINV::#OFF BYINV::#OFF CEINV::#OFF CLKINV::#OFF COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DXMUX::#OFF DYMUX::#OFF F:u2/u4/En1:#LUT:D=(~A4*(A2*~A3)) F5USED::#OFF FFX::#OFF FFX_INIT_ATTR::#OFF FFX_SR_ATTR::#OFF FFY::#OFF FFY_INIT_ATTR::#OFF FFY_SR_ATTR::#OFF FXMUX::F FXUSED::#OFF G:u2/Go_Skip1:#LUT:D=(A2*(A3+(~A4*~A1))) GYMUX::G REVUSED::#OFF SRINV::#OFF SYNC_ATTR::#OFF XBUSED::#OFF XUSED::0 YBUSED::#OFF YUSED::0 " ; inst "u1/f2/Working" "SLICEL",placed CLB_X8Y6 SLICE_X14Y11 , cfg " BXINV::BX BYINV::BY CEINV::CE CLKINV::CLK_B COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DXMUX::0 DYMUX::#OFF F::#OFF F5USED::#OFF FFX:u1/f2/Working:#FF FFX_INIT_ATTR::INIT0 FFX_SR_ATTR::SRLOW FFY::#OFF FFY_INIT_ATTR::#OFF FFY_SR_ATTR::#OFF FXMUX::#OFF FXUSED::#OFF G::#OFF GYMUX::#OFF REVUSED::0 SRINV::SR SYNC_ATTR::ASYNC XBUSED::#OFF XUSED::#OFF YBUSED::#OFF YUSED::#OFF _VCC_SOURCE::X " ; inst "u1/g3/u0/Q" "SLICEL",placed CLB_X7Y3 SLICE_X12Y4 , cfg " BXINV::#OFF BYINV::BY CEINV::#OFF CLKINV::CLK COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DXMUX::#OFF DYMUX::0 F::#OFF F5USED::#OFF FFX::#OFF FFX_INIT_ATTR::#OFF FFX_SR_ATTR::#OFF FFY:u1/g3/u0/Q:#FF FFY_INIT_ATTR::INIT0 FFY_SR_ATTR::SRLOW FXMUX::#OFF FXUSED::#OFF G::#OFF GYMUX::#OFF REVUSED::#OFF SRINV::#OFF SYNC_ATTR::ASYNC XBUSED::#OFF XUSED::#OFF YBUSED::#OFF YUSED::#OFF " ; inst "u7/u8/u2/Q_int" "SLICEL",placed CLB_X14Y15 SLICE_X18Y28 , cfg " BXINV::#OFF BYINV::BY CEINV::#OFF CLKINV::CLK_B COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DXMUX::#OFF DYMUX::0 F::#OFF F5USED::#OFF FFX::#OFF FFX_INIT_ATTR::#OFF FFX_SR_ATTR::#OFF FFY:u7/u8/u2/Q_int:#FF FFY_INIT_ATTR::INIT0 FFY_SR_ATTR::SRLOW FXMUX::#OFF FXUSED::#OFF G::#OFF GYMUX::#OFF REVUSED::#OFF SRINV::#OFF SYNC_ATTR::ASYNC XBUSED::#OFF XUSED::#OFF YBUSED::#OFF YUSED::#OFF " ; inst "u1/m6/m/m2/Done_AddrH" "SLICEL",placed CLB_X5Y3 SLICE_X8Y5 , cfg " BXINV::#OFF BYINV::#OFF CEINV::#OFF CLKINV::#OFF COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DXMUX::#OFF DYMUX::#OFF F::#OFF F5USED::#OFF FFX::#OFF FFX_INIT_ATTR::#OFF FFX_SR_ATTR::#OFF FFY::#OFF FFY_INIT_ATTR::#OFF FFY_SR_ATTR::#OFF FXMUX::#OFF FXUSED::#OFF G:u1/m6/m/m2/aH/En1:#LUT:D=(~A2*(~A3*A4)) GYMUX::G REVUSED::#OFF SRINV::#OFF SYNC_ATTR::#OFF XBUSED::#OFF XUSED::#OFF YBUSED::#OFF YUSED::0 " ; inst "u8/l1/u1/Q" "SLICEL",placed CLB_X4Y8 SLICE_X6Y14 , cfg " BXINV::#OFF BYINV::BY CEINV::#OFF CLKINV::CLK COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DXMUX::#OFF DYMUX::0 F::#OFF F5USED::#OFF FFX::#OFF FFX_INIT_ATTR::#OFF FFX_SR_ATTR::#OFF FFY:u8/l1/u1/Q:#FF FFY_INIT_ATTR::INIT0 FFY_SR_ATTR::SRLOW FXMUX::#OFF FXUSED::#OFF G::#OFF GYMUX::#OFF REVUSED::#OFF SRINV::#OFF SYNC_ATTR::ASYNC XBUSED::#OFF XUSED::#OFF YBUSED::#OFF YUSED::#OFF " ; inst "u7/u9/RstCyc" "SLICEL",placed CLB_X8Y12 SLICE_X15Y22 , cfg " BXINV::#OFF BYINV::BY CEINV::CE CLKINV::CLK COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DXMUX::#OFF DYMUX::0 F::#OFF F5USED::#OFF FFX::#OFF FFX_INIT_ATTR::#OFF FFX_SR_ATTR::#OFF FFY:u7/u9/RstCyc:#FF FFY_INIT_ATTR::INIT1 FFY_SR_ATTR::SRHIGH FXMUX::#OFF FXUSED::#OFF G::#OFF GYMUX::#OFF REVUSED::#OFF SRINV::SR SYNC_ATTR::ASYNC XBUSED::#OFF XUSED::#OFF YBUSED::#OFF YUSED::#OFF " ; inst "u1/m1/En" "SLICEL",placed CLB_X8Y1 SLICE_X15Y1 , cfg " BXINV::BX BYINV::BY CEINV::#OFF CLKINV::CLK_B COUTUSED::#OFF CY0F::#OFF CY0G::#OFF CYINIT::#OFF CYSELF::#OFF CYSELG::#OFF DXMUX::0 DYMUX::#OFF F::#OFF F5USED::#OFF FFX:u1/m1/En:#FF FFX_INIT_ATTR::INIT0 FFX_SR_ATTR::SRLOW FFY::#OFF FFY_INIT_ATTR::#OFF FFY_SR_ATTR::#OFF FXMUX::#OFF FXUSED::#OFF G::#OFF GYMUX::#OFF REVUSED::0 SRINV::SR SYNC_ATTR::ASYNC XBUSED::#OFF XUSED::#OFF YBUSED::#OFF YUSED::#OFF " ; inst "XDL_DUMMY_CLB_X1Y12_VCC_X2Y14" "VCC",placed CLB_X1Y12 VCC_X2Y14 , cfg "_NO_USER_LOGIC:: _VCC_SOURCE::VCCOUT " ; inst "XDL_DUMMY_CLB_X1Y14_VCC_X2Y16" "VCC",placed CLB_X1Y14 VCC_X2Y16 , cfg "_NO_USER_LOGIC:: _VCC_SOURCE::VCCOUT " ; inst "XDL_DUMMY_CLB_X1Y4_SLICE_X1Y7" "SLICEL",placed CLB_X1Y4 SLICE_X1Y7 , cfg "_NO_USER_LOGIC:: _GND_SOURCE::Y " ; inst "XDL_DUMMY_CLB_X1Y14_SLICE_X1Y27" "SLICEL",placed CLB_X1Y14 SLICE_X1Y27 , cfg "_NO_USER_LOGIC:: _GND_SOURCE::Y " ; inst "XDL_DUMMY_CLB_X2Y2_SLICE_X3Y2" "SLICEL",placed CLB_X2Y2 SLICE_X3Y2 , cfg "_NO_USER_LOGIC:: _GND_SOURCE::Y " ; inst "XDL_DUMMY_CLB_X3Y11_VCC_X4Y13" "VCC",placed CLB_X3Y11 VCC_X4Y13 , cfg "_NO_USER_LOGIC:: _VCC_SOURCE::VCCOUT " ; inst "XDL_DUMMY_CLB_X3Y3_SLICE_X4Y4" "SLICEM",placed CLB_X3Y3 SLICE_X4Y4 , cfg "_NO_USER_LOGIC:: _VCC_SOURCE::X _GND_SOURCE::Y " ; inst "XDL_DUMMY_CLB_X4Y1_SLICE_X6Y1" "SLICEM",placed CLB_X4Y1 SLICE_X6Y1 , cfg "_NO_USER_LOGIC:: _VCC_SOURCE::X _GND_SOURCE::Y " ; inst "XDL_DUMMY_CLB_X4Y4_SLICE_X6Y7" "SLICEM",placed CLB_X4Y4 SLICE_X6Y7 , cfg "_NO_USER_LOGIC:: _VCC_SOURCE::X _GND_SOURCE::Y " ; inst "XDL_DUMMY_CLB_X4Y5_SLICE_X7Y9" "SLICEL",placed CLB_X4Y5 SLICE_X7Y9 , cfg "_NO_USER_LOGIC:: _VCC_SOURCE::X _GND_SOURCE::Y " ; inst "XDL_DUMMY_CLB_X5Y1_SLICE_X8Y0" "SLICEM",placed CLB_X5Y1 SLICE_X8Y0 , cfg "_NO_USER_LOGIC:: _GND_SOURCE::Y " ; inst "XDL_DUMMY_CLB_X5Y3_SLICE_X9Y5" "SLICEL",placed CLB_X5Y3 SLICE_X9Y5 , cfg "_NO_USER_LOGIC:: _GND_SOURCE::Y " ; inst "XDL_DUMMY_CLB_X5Y7_SLICE_X9Y12" "SLICEL",placed CLB_X5Y7 SLICE_X9Y12 , cfg "_NO_USER_LOGIC:: _GND_SOURCE::Y " ; inst "XDL_DUMMY_CLB_X6Y9_SLICE_X10Y17" "SLICEM",placed CLB_X6Y9 SLICE_X10Y17 , cfg "_NO_USER_LOGIC:: _VCC_SOURCE::X _GND_SOURCE::Y " ; inst "XDL_DUMMY_CLB_X7Y1_SLICE_X12Y1" "SLICEM",placed CLB_X7Y1 SLICE_X12Y1 , cfg "_NO_USER_LOGIC:: _VCC_SOURCE::X _GND_SOURCE::Y " ; inst "XDL_DUMMY_CLB_X7Y4_SLICE_X12Y6" "SLICEM",placed CLB_X7Y4 SLICE_X12Y6 , cfg "_NO_USER_LOGIC:: _GND_SOURCE::Y " ; inst "XDL_DUMMY_CLB_X7Y9_SLICE_X12Y17" "SLICEM",placed CLB_X7Y9 SLICE_X12Y17 , cfg "_NO_USER_LOGIC:: _VCC_SOURCE::X _GND_SOURCE::Y " ; inst "XDL_DUMMY_CLB_X7Y5_SLICE_X13Y9" "SLICEL",placed CLB_X7Y5 SLICE_X13Y9 , cfg "_NO_USER_LOGIC:: _VCC_SOURCE::X _GND_SOURCE::Y " ; inst "XDL_DUMMY_CLB_X8Y10_VCC_X9Y12" "VCC",placed CLB_X8Y10 VCC_X9Y12 , cfg "_NO_USER_LOGIC:: _VCC_SOURCE::VCCOUT " ; inst "XDL_DUMMY_CLB_X8Y1_SLICE_X14Y1" "SLICEM",placed CLB_X8Y1 SLICE_X14Y1 , cfg "_NO_USER_LOGIC:: _VCC_SOURCE::X " ; inst "XDL_DUMMY_CLB_X8Y5_SLICE_X15Y9" "SLICEL",placed CLB_X8Y5 SLICE_X15Y9 , cfg "_NO_USER_LOGIC:: _GND_SOURCE::Y " ; inst "XDL_DUMMY_CLB_X8Y7_SLICE_X15Y13" "SLICEL",placed CLB_X8Y7 SLICE_X15Y13 , cfg "_NO_USER_LOGIC:: _VCC_SOURCE::X _GND_SOURCE::Y " ; inst "XDL_DUMMY_CLKB_X8Y0_VCC_X10Y0" "VCC",placed CLKB_X8Y0 VCC_X10Y0 , cfg "_NO_USER_LOGIC:: _VCC_SOURCE::VCCOUT " ; inst "XDL_DUMMY_CLKT_X8Y17_VCC_X10Y19" "VCC",placed CLKT_X8Y17 VCC_X10Y19 , cfg "_NO_USER_LOGIC:: _VCC_SOURCE::VCCOUT " ; inst "XDL_DUMMY_TIOIB_X9Y17_VCC_X11Y19" "VCC",placed TIOIB_X9Y17 VCC_X11Y19 , cfg "_NO_USER_LOGIC:: _VCC_SOURCE::VCCOUT " ; inst "XDL_DUMMY_CLB_X13Y1_SLICE_X17Y1" "SLICEL",placed CLB_X13Y1 SLICE_X17Y1 , cfg "_NO_USER_LOGIC:: _GND_SOURCE::Y " ; inst "XDL_DUMMY_CLB_X13Y2_SLICE_X17Y2" "SLICEL",placed CLB_X13Y2 SLICE_X17Y2 , cfg "_NO_USER_LOGIC:: _GND_SOURCE::Y " ; inst "XDL_DUMMY_CLB_X14Y2_SLICE_X19Y3" "SLICEL",placed CLB_X14Y2 SLICE_X19Y3 , cfg "_NO_USER_LOGIC:: _VCC_SOURCE::X " ; inst "XDL_DUMMY_CLB_X14Y4_SLICE_X19Y7" "SLICEL",placed CLB_X14Y4 SLICE_X19Y7 , cfg "_NO_USER_LOGIC:: _VCC_SOURCE::X _GND_SOURCE::Y " ; inst "XDL_DUMMY_CLB_X15Y12_SLICE_X20Y23" "SLICEM",placed CLB_X15Y12 SLICE_X20Y23 , cfg "_NO_USER_LOGIC:: _VCC_SOURCE::X _GND_SOURCE::Y " ; inst "XDL_DUMMY_CLB_X15Y1_SLICE_X21Y1" "SLICEL",placed CLB_X15Y1 SLICE_X21Y1 , cfg "_NO_USER_LOGIC:: _GND_SOURCE::Y " ; inst "XDL_DUMMY_CLB_X15Y4_SLICE_X21Y6" "SLICEL",placed CLB_X15Y4 SLICE_X21Y6 , cfg "_NO_USER_LOGIC:: _GND_SOURCE::Y " ; inst "XDL_DUMMY_CLB_X15Y5_SLICE_X21Y9" "SLICEL",placed CLB_X15Y5 SLICE_X21Y9 , cfg "_NO_USER_LOGIC:: _VCC_SOURCE::X _GND_SOURCE::Y " ; inst "XDL_DUMMY_CLB_X15Y6_SLICE_X21Y11" "SLICEL",placed CLB_X15Y6 SLICE_X21Y11 , cfg "_NO_USER_LOGIC:: _GND_SOURCE::Y " ; inst "XDL_DUMMY_CLB_X15Y8_SLICE_X21Y14" "SLICEL",placed CLB_X15Y8 SLICE_X21Y14 , cfg "_NO_USER_LOGIC:: _VCC_SOURCE::X " ; inst "XDL_DUMMY_CLB_X16Y2_SLICE_X23Y3" "SLICEL",placed CLB_X16Y2 SLICE_X23Y3 , cfg "_NO_USER_LOGIC:: _VCC_SOURCE::X " ; inst "XDL_DUMMY_CLB_X16Y3_SLICE_X23Y4" "SLICEL",placed CLB_X16Y3 SLICE_X23Y4 , cfg "_NO_USER_LOGIC:: _GND_SOURCE::Y " ; inst "XDL_DUMMY_CLB_X16Y7_SLICE_X23Y13" "SLICEL",placed CLB_X16Y7 SLICE_X23Y13 , cfg "_NO_USER_LOGIC:: _GND_SOURCE::Y " ; # ================================================ # The syntax for nets is: # net , # outpin , # . # . # inpin , # . # . # pip , # [] # . # . # ; # # There are three available wire types: wire, power and ground. # If no type is specified, wire is assumed. # # Wire indicates that this a normal wire. # Power indicates that this net is tied to a DC power source. # You can use "power", "vcc" or "vdd" to specify a power net. # # Ground indicates that this net is tied to ground. # You can use "ground", or "gnd" to specify a ground net. # # The token will be one of the following: # # Symbol Description # ====== ========================================== # == Bidirectional, unbuffered. # => Bidirectional, buffered in one direction. # =- Bidirectional, buffered in both directions. # -> Directional, buffered. # # No pips exist for unrouted nets. # ================================================ net "AD<0>" , cfg " _BELSIG:PAD,PAD,AD<0>:AD<0>", ; net "AD<1>" , cfg " _BELSIG:PAD,PAD,AD<1>:AD<1>", ; net "AD<2>" , cfg " _BELSIG:PAD,PAD,AD<2>:AD<2>", ; net "AD<3>" , cfg " _BELSIG:PAD,PAD,AD<3>:AD<3>", ; net "AD<4>" , cfg " _BELSIG:PAD,PAD,AD<4>:AD<4>", ; net "AD<5>" , cfg " _BELSIG:PAD,PAD,AD<5>:AD<5>", ; net "AD<6>" , cfg " _BELSIG:PAD,PAD,AD<6>:AD<6>", ; net "AD<7>" , cfg " _BELSIG:PAD,PAD,AD<7>:AD<7>", ; net "ALE" , cfg " _BELSIG:PAD,PAD,ALE:ALE", ; net "DAC_iRst" , cfg " _BELSIG:PAD,PAD,DAC_iRst:DAC_iRst", ; net "DAC_iRst_OBUF" , outpin "DAC_iRst_OBUF" X , inpin "DAC_iRst" O1 , inpin "SPI_iRst" F1 , inpin "SPI_iRst" G1 , inpin "u7/u8/Done_int_and0000" G2 , ; net "DAC_serData" , cfg " _BELSIG:PAD,PAD,DAC_serData:DAC_serData", ; net "DAC_serISync" , cfg " _BELSIG:PAD,PAD,DAC_serISync:DAC_serISync", ; net "Eth_iINT" , cfg " _BELSIG:PAD,PAD,Eth_iINT:Eth_iINT", ; net "Eth_iINT_IBUF" , outpin "Eth_iINT" I , inpin "u1/g3/u0/Q_int" SR , inpin "u1/p7/u0/Q_int" SR , inpin "u4/u2/u0/Q_int" SR , ; net "Eth_iRst" , cfg " _BELSIG:PAD,PAD,Eth_iRst:Eth_iRst", ; net "GLOBAL_LOGIC0_0" gnd, outpin "XDL_DUMMY_CLB_X5Y3_SLICE_X9Y5" Y , inpin "u1/m6/m/m2/aH/Working" BX , ; net "GLOBAL_LOGIC0_1" gnd, outpin "XDL_DUMMY_CLB_X5Y7_SLICE_X9Y12" Y , inpin "u1/m6/b1/En" BX , inpin "u8/l1/En" BX , ; net "GLOBAL_LOGIC0_2" gnd, outpin "XDL_DUMMY_CLB_X5Y1_SLICE_X8Y0" Y , inpin "u1/m2/m2/aH/Working" BX , inpin "u1/m2/m2/aL/Working" BX , ; net "GLOBAL_LOGIC0_3" gnd, outpin "u8/lenregH/Data<0>" X , inpin "u2/u3/u1/En" BX , ; net "GLOBAL_LOGIC0_4" gnd, outpin "XDL_DUMMY_CLB_X4Y5_SLICE_X7Y9" Y , inpin "u1/m6/b2/En" BX , inpin "u1/m6/m/m3/Working" BX , inpin "u1/m7/m1/Working" BX , ; net "GLOBAL_LOGIC0_5" gnd, outpin "XDL_DUMMY_CLB_X4Y4_SLICE_X6Y7" Y , inpin "u1/m5/m2/aH/Working" BX , inpin "u1/m5/m2/aL/Working" BX , inpin "u1/m6/a1/aL/Working" BX , inpin "u1/m6/m/m1/Working" BX , ; net "GLOBAL_LOGIC0_6" gnd, outpin "XDL_DUMMY_CLB_X4Y1_SLICE_X6Y1" Y , inpin "u1/m2/m3/Working" BX , inpin "u1/m3/m1/Working" BX , ; net "GLOBAL_LOGIC0_7" gnd, outpin "u8/VoltData<7>" X , inpin "u8/MaskStage" BX , ; net "GLOBAL_LOGIC0_8" gnd, outpin "XDL_DUMMY_CLB_X3Y3_SLICE_X4Y4" Y , inpin "u1/m5/m3/Working" BX , inpin "u1/m6/a1/aH/Working" BX , inpin "u1/m6/m/m2/aL/Working" BX , ; net "GLOBAL_LOGIC0_9" gnd, outpin "XDL_DUMMY_CLB_X2Y2_SLICE_X3Y2" Y , inpin "u1/m4/m1/Working" BX , ; net "GLOBAL_LOGIC0_10" gnd, outpin "u1/m3/m2/aL/Working" X , inpin "u1/m3/m2/aH/Working" BX , inpin "u1/m3/m2/aL/Working" BX , inpin "u1/m3/m3/Working" BX , ; net "GLOBAL_LOGIC0_11" gnd, outpin "XDL_DUMMY_CLB_X1Y4_SLICE_X1Y7" Y , inpin "u1/m4/m2/aH/Working" BX , inpin "u1/m4/m2/aL/Working" BX , inpin "u1/m4/m3/Working" BX , inpin "u1/m5/m1/Working" BX , ; net "GLOBAL_LOGIC0_12" gnd, outpin "XDL_DUMMY_CLB_X1Y14_SLICE_X1Y27" Y , inpin "u7/u6/reg_121" G1 , inpin "u7/u6/reg_121" G3 , ; net "GLOBAL_LOGIC0_13" gnd, outpin "XDL_DUMMY_CLB_X7Y5_SLICE_X13Y9" Y , inpin "u1/f2/Working" BX , ; net "GLOBAL_LOGIC0_14" gnd, outpin "XDL_DUMMY_CLB_X8Y5_SLICE_X15Y9" Y , inpin "u1/f1/Working" BX , ; net "GLOBAL_LOGIC0_15" gnd, outpin "XDL_DUMMY_CLB_X8Y7_SLICE_X15Y13" Y , inpin "u1/m7/m3/Working" BX , ; net "GLOBAL_LOGIC0_16" gnd, outpin "XDL_DUMMY_CLB_X7Y4_SLICE_X12Y6" Y , inpin "u1/f3/Working" BX , inpin "u1/g3/u2/En" BX , inpin "u1/p7/u2/En" BX , ; net "GLOBAL_LOGIC0_17" gnd, outpin "XDL_DUMMY_CLB_X7Y1_SLICE_X12Y1" Y , inpin "u1/m1/En" BX , inpin "u1/m2/m1/Working" BX , ; net "GLOBAL_LOGIC0_18" gnd, outpin "XDL_DUMMY_CLB_X7Y9_SLICE_X12Y17" Y , inpin "u8/u3/u1/En1" BX , ; net "GLOBAL_LOGIC0_19" gnd, outpin "u8/u1/Qa" X , inpin "u1/m7/m2/aH/Working" BX , inpin "u1/m7/m2/aL/Working" BX , ; net "GLOBAL_LOGIC0_20" gnd, outpin "u6/u4/Q" X , inpin "DAC_serISync" O1 , inpin "u7/u9/RstCyc" BY , ; net "GLOBAL_LOGIC0_21" gnd, outpin "u8/u1/Qb" X , inpin "u8/l2/En" BX , inpin "u8/u5/Working" BX , ; net "GLOBAL_LOGIC0_22" gnd, outpin "r1/state<2>" X , inpin "u2/u4/Working" BX , ; net "GLOBAL_LOGIC0_23" gnd, outpin "XDL_DUMMY_CLB_X6Y9_SLICE_X10Y17" Y , inpin "u8/ByteCount<0>" BX , inpin "u8/Mcompar_En_cmp_ne0000_cy<1>" BX , ; net "GLOBAL_LOGIC0_24" gnd, outpin "XDL_DUMMY_CLB_X13Y2_SLICE_X17Y2" Y , inpin "Eth_iRst" O1 , inpin "u1/p7/En" CLK , ; net "GLOBAL_LOGIC0_25" gnd, outpin "XDL_DUMMY_CLB_X13Y1_SLICE_X17Y1" Y , inpin "u1/g3/u3/En" BX , ; net "GLOBAL_LOGIC0_26" gnd, outpin "XDL_DUMMY_CLB_X14Y4_SLICE_X19Y7" Y , inpin "u1/p3/Working" BX , inpin "u1/p7/En" BX , inpin "u1/p7/u3/En" BX , ; net "GLOBAL_LOGIC0_27" gnd, outpin "u1/i2/Working" X , inpin "u1/i2/Working" BX , inpin "u1/p1/Working" BX , ; net "GLOBAL_LOGIC0_28" gnd, outpin "XDL_DUMMY_CLB_X15Y12_SLICE_X20Y23" Y , inpin "u4/u2/En" BX , inpin "u4/u2/u3/En" BX , inpin "u5/s2/u1/En" BX , ; net "GLOBAL_LOGIC0_29" gnd, outpin "XDL_DUMMY_CLB_X15Y5_SLICE_X21Y9" Y , inpin "u1/i1/Working" BX , inpin "u1/p2/Working" BX , ; net "GLOBAL_LOGIC0_30" gnd, outpin "XDL_DUMMY_CLB_X15Y4_SLICE_X21Y6" Y , inpin "u1/Result<0>2" BX , inpin "u1/g3/En" CLK , ; net "GLOBAL_LOGIC0_31" gnd, outpin "XDL_DUMMY_CLB_X15Y1_SLICE_X21Y1" Y , inpin "AD<1>" O1 , inpin "AD<2>" O1 , inpin "u1/p0/Working" BX , inpin "u1/p10/Working" BX , inpin "u1/p9/Working" BX , ; net "GLOBAL_LOGIC0_32" gnd, outpin "XDL_DUMMY_CLB_X15Y6_SLICE_X21Y11" Y , inpin "AD<6>" O1 , inpin "u1/g3/En" BX , ; net "GLOBAL_LOGIC0_33" gnd, outpin "u1/p5/count<1>" X , inpin "u1/Result<0>1" BX , inpin "u4/u2/u2/En" BX , ; net "GLOBAL_LOGIC0_34" gnd, outpin "XDL_DUMMY_CLB_X16Y3_SLICE_X23Y4" Y , inpin "AD<4>" O1 , ; net "GLOBAL_LOGIC0_35" gnd, outpin "XDL_DUMMY_CLB_X16Y7_SLICE_X23Y13" Y , inpin "AD<5>" O1 , inpin "AD<7>" O1 , ; net "LocStamp<0>" , cfg " _BELSIG:PAD,PAD,LocStamp<0>:LocStamp<0>", ; net "LocStamp<1>" , cfg " _BELSIG:PAD,PAD,LocStamp<1>:LocStamp<1>", ; net "LocStamp<2>" , cfg " _BELSIG:PAD,PAD,LocStamp<2>:LocStamp<2>", ; net "LocStamp<3>" , cfg " _BELSIG:PAD,PAD,LocStamp<3>:LocStamp<3>", ; net "LocStamp<4>" , cfg " _BELSIG:PAD,PAD,LocStamp<4>:LocStamp<4>", ; net "LocStamp<5>" , cfg " _BELSIG:PAD,PAD,LocStamp<5>:LocStamp<5>", ; net "LocStamp_0_IBUF" , outpin "LocStamp<0>" I , inpin "u5/Go_Cyc14Step_inv12" F4 , inpin "u5/count<0>" F4 , ; net "LocStamp_1_IBUF" , outpin "LocStamp<1>" I , inpin "state_D<0>LogicTrst40" F2 , inpin "u5/Go_Cyc14Step_inv12" F2 , ; net "LocStamp_2_IBUF" , outpin "LocStamp<2>" I , inpin "state_D<0>LogicTrst40" F3 , inpin "u5/Go_Cyc14Step_inv12" G2 , ; net "LocStamp_3_IBUF" , outpin "LocStamp<3>" I , inpin "state_D<0>LogicTrst40" F4 , inpin "u5/Go_Cyc14Step_inv12" G4 , ; net "LocStamp_4_IBUF" , outpin "LocStamp<4>" I , inpin "u5/Go_Cyc14Step_inv12" G3 , inpin "u5/count<0>" F1 , ; net "LocStamp_5_IBUF" , outpin "LocStamp<5>" I , inpin "state_D<0>LogicTrst40" F1 , inpin "u5/Go_Cyc14Step_inv12" G1 , ; net "N14" , outpin "u7/u1/count_not0001" Y , inpin "u7/u1/count_not0001" F3 , ; net "N22" , outpin "u1/g2/count<0>" X , inpin "u1/Eth_iRst_or0000_inv" G2 , ; net "N24" , outpin "u8/u3/u1/u1/Q_int" Y , inpin "u8/u3/u1/u1/Q_int" F3 , ; net "N28" , outpin "u6/Addr<1>" Y , inpin "state_D<0>LogicTrst82" G2 , ; net "N39" , outpin "u1/m6/WordCount<0>" X , inpin "u1/m7/m2/u1/Q_int" G1 , ; net "N41" , outpin "u8/VoltData_10_and0000" Y , inpin "u8/Addr_and0000" G4 , inpin "u8/VoltData_10_and0000" F1 , ; net "N45" , outpin "u2/ReadCount<1>" Y , inpin "u2/Done_Skip" G2 , ; net "N47" , outpin "N48" Y , inpin "r1/state<0>" G3 , ; net "N48" , outpin "N48" X , inpin "r1/state<0>" G1 , ; net "N50" , outpin "u7/u8/Wr_int" Y , inpin "u7/u8/Wr_int" F3 , ; net "N54" , outpin "u1/Done_EthiRST" Y , inpin "u1/Done_EthiRST" F3 , ; net "N56" , outpin "state_D<0>LogicTrst19" Y , inpin "state_D<0>LogicTrst19" F4 , ; net "Rst" , cfg " _BELSIG:PAD,PAD,Rst:Rst", ; net "Rst_IBUF" , outpin "Rst_IBUF_BUFG" O , inpin "u0/u2/RWflag" CLK , inpin "u8/Mtridata_DAC_Addr<1>" CLK , inpin "u8/Mtridata_DAC_Addr<3>" CLK , inpin "u8/Mtridata_DAC_Addr<4>" CLK , inpin "u8/Mtridata_DAC_D<10>" CLK , inpin "u8/Mtrien_DAC_Addr" CLK , inpin "u8/Mtrien_DAC_D" CLK , ; net "Rst_IBUF1" , outpin "Rst" I , inpin "N48" F1 , inpin "N48" G1 , inpin "Rst_IBUF_BUFG" I0 , inpin "SPI_iRst" F2 , inpin "SPI_iRst" G2 , inpin "r1/state<0>" SR , inpin "r1/state<2>" SR , inpin "u0/u2/ALE_mux0001" G2 , inpin "u0/u2/ALE_not0001" F2 , inpin "u0/u2/ALE_not0001" G1 , inpin "u0/u2/Mtridata_AD_mux0000<0>" G4 , inpin "u0/u2/Mtrien_AD_mux0000" F1 , inpin "u0/u2/Mtrien_AD_mux0000" G1 , inpin "u0/u2/Mtrien_AD_not0001" F4 , inpin "u0/u2/Mtrien_AD_not0001" G4 , inpin "u0/u2/TickCount<0>" SR , inpin "u0/u2/TickCount_11" SR , inpin "u1/Done_Hash1" F3 , inpin "u1/Done_Hash1" G3 , inpin "u1/Done_IPGR" F1 , inpin "u1/Done_IPGR" G3 , inpin "u1/Done_IPGT" F4 , inpin "u1/Done_IPGT" G4 , inpin "u1/Done_MAC" F1 , inpin "u1/Done_MAC" G1 , inpin "u1/Done_MACCF" F1 , inpin "u1/Done_MACCF" G3 , inpin "u1/Done_ResCfg" G3 , inpin "u1/Done_SelfInit" G4 , inpin "u1/Done_p0" G2 , inpin "u1/Done_p1" F2 , inpin "u1/Done_p1" G1 , inpin "u1/Done_p2" G1 , inpin "u1/InitDelay<0>" SR , inpin "u1/f1/Working" SR , inpin "u1/f2/Working" SR , inpin "u1/f3/Working" SR , inpin "u1/g2/count<0>" SR , inpin "u1/g2/count<3>" SR , inpin "u1/g2/count<4>" SR , inpin "u1/g2/count<6>" SR , inpin "u1/g3/En" SR , inpin "u1/g3/u2/En" SR , inpin "u1/g3/u3/En" SR , inpin "u1/i1/Working" SR , inpin "u1/i2/Working" SR , inpin "u1/m1/En" SR , inpin "u1/m1/u1/Q_int" F2 , inpin "u1/m2/m1/Working" SR , inpin "u1/m2/m2/Done_AddrH" G3 , inpin "u1/m2/m2/aH/Working" SR , inpin "u1/m2/m2/aL/Working" SR , inpin "u1/m2/m2/u1/Q_int" G3 , inpin "u1/m2/m3/Working" SR , inpin "u1/m3/m1/Working" SR , inpin "u1/m3/m2/Done_AddrH" G1 , inpin "u1/m3/m2/aH/Working" SR , inpin "u1/m3/m2/aL/Working" SR , inpin "u1/m3/m2/u1/Q_int" G2 , inpin "u1/m3/m3/Working" SR , inpin "u1/m4/m1/Working" SR , inpin "u1/m4/m2/Done_AddrH" G3 , inpin "u1/m4/m2/aH/Working" SR , inpin "u1/m4/m2/aL/Working" SR , inpin "u1/m4/m2/u1/Q_int" G3 , inpin "u1/m4/m3/Working" SR , inpin "u1/m5/m1/Working" SR , inpin "u1/m5/m2/Done_AddrH" G1 , inpin "u1/m5/m2/aH/Working" SR , inpin "u1/m5/m2/aL/Working" SR , inpin "u1/m5/m2/u1/Q_int" G1 , inpin "u1/m5/m3/Working" SR , inpin "u1/m6/Done_FlashAddr" F4 , inpin "u1/m6/Done_FlashAddr" G3 , inpin "u1/m6/Done_Word_inv" F2 , inpin "u1/m6/Done_Word_inv" G3 , inpin "u1/m6/WordCount<0>" F4 , inpin "u1/m6/a1/aH/Working" SR , inpin "u1/m6/a1/aL/Working" SR , inpin "u1/m6/a1/u1/Q_int" F2 , inpin "u1/m6/a1/u1/Q_int" G2 , inpin "u1/m6/b1/En" SR , inpin "u1/m6/b1/u1/Q_int" G2 , inpin "u1/m6/b2/En" SR , inpin "u1/m6/m/m1/Working" SR , inpin "u1/m6/m/m2/Done_AddrH" G2 , inpin "u1/m6/m/m2/aH/Working" SR , inpin "u1/m6/m/m2/aL/Working" SR , inpin "u1/m6/m/m2/u1/Q_int" G2 , inpin "u1/m6/m/m3/Working" SR , inpin "u1/m7/m1/Working" SR , inpin "u1/m7/m2/Done_AddrH" G2 , inpin "u1/m7/m2/aH/Working" SR , inpin "u1/m7/m2/aL/Working" SR , inpin "u1/m7/m2/u1/Q_int" F3 , inpin "u1/m7/m3/Working" SR , inpin "u1/p0/Working" SR , inpin "u1/p1/Working" SR , inpin "u1/p10/Working" SR , inpin "u1/p2/Working" SR , inpin "u1/p3/Working" SR , inpin "u1/p4/count<0>" G2 , inpin "u1/p4/count<0>" SR , inpin "u1/p4/count<11>" SR , inpin "u1/p4/count<1>" SR , inpin "u1/p4/count<3>" SR , inpin "u1/p4/count<5>" SR , inpin "u1/p4/count<7>" SR , inpin "u1/p4/count<9>" SR , inpin "u1/p5/count<0>" SR , inpin "u1/p5/count<11>" SR , inpin "u1/p5/count<1>" SR , inpin "u1/p5/count<3>" SR , inpin "u1/p5/count<5>" SR , inpin "u1/p5/count<7>" SR , inpin "u1/p5/count<9>" SR , inpin "u1/p7/En" SR , inpin "u1/p7/u2/En" SR , inpin "u1/p7/u3/En" SR , inpin "u1/p9/Working" SR , inpin "u2/Done_Skip" F4 , inpin "u2/ReadCount_or0000" G2 , inpin "u2/u3/u1/En" SR , inpin "u2/u4/Working" SR , inpin "u4/u2/En" SR , inpin "u4/u2/u2/En" SR , inpin "u4/u2/u3/En" SR , inpin "u5/s2/u1/En" SR , inpin "u6/Addr_or0000" G3 , inpin "u7/u8/Done_int_and0000" G3 , inpin "u8/Addr<0>" SR , inpin "u8/Addr<3>" SR , inpin "u8/Addr<4>" SR , inpin "u8/ByteCount_or0000" G4 , inpin "u8/MaskStage" SR , inpin "u8/Mtrien_DAC_Addr" G3 , inpin "u8/VoltData<7>" SR , inpin "u8/VoltData<9>" SR , inpin "u8/intMaskByteNum<0>" SR , inpin "u8/l1/En" SR , inpin "u8/l2/En" SR , inpin "u8/lenregH/Data<0>" SR , inpin "u8/lenregL/Data<0>" SR , inpin "u8/u2/Q_int" F1 , inpin "u8/u3/u1/En1" SR , inpin "u8/u5/Working" SR , inpin "u9/u1/count<0>" SR , inpin "u9/u1/count<2>" SR , inpin "u9/u1/count<4>" SR , inpin "u9/u2/LineOut_not0001_inv" G3 , inpin "u9/u2/SReg_0_or0000" F1 , inpin "u9/u2/SReg_10_or0000" F1 , inpin "u9/u2/SReg_14_and0000" G1 , inpin "u9/u2/SReg_15_or0000" F3 , inpin "u9/u2/SReg_16_and0000" G4 , inpin "u9/u2/SReg_17_and0000" G4 , inpin "u9/u2/SReg_18_and0000" G4 , ; net "SPI_A_iCS" , cfg " _BELSIG:PAD,PAD,SPI_A_iCS:SPI_A_iCS", ; net "SPI_Go" , outpin "u7/u8/Wr_int_mux000363" Y , inpin "u7/u8/Done_int_and0000" G4 , inpin "u7/u8/Go_next_clk" G4 , inpin "u7/u8/Wr_int_and0000" G1 , inpin "u7/u8/Wr_int_mux000363" F4 , inpin "u7/u9/T_iA_int" F3 , ; net "SPI_SCLK" , cfg " _BELSIG:PAD,PAD,SPI_SCLK:SPI_SCLK", ; net "SPI_SDI" , cfg " _BELSIG:PAD,PAD,SPI_SDI:SPI_SDI", ; net "SPI_SDI_OBUF" , outpin "u7/Go_int" Y , inpin "SPI_SDI" O1 , ; net "SPI_SDO" , cfg " _BELSIG:PAD,PAD,SPI_SDO:SPI_SDO", ; net "SPI_SDO_IBUF" , outpin "SPI_SDO" I , inpin "u7/u6/reg_121" BY , ; net "SPI_T_CE" , cfg " _BELSIG:PAD,PAD,SPI_T_CE:SPI_T_CE", ; net "SPI_T_CE_OBUF" , outpin "u7/u7/line" X , inpin "SPI_T_CE" O1 , ; net "SPI_iRst" , outpin "SPI_iRst" X , inpin "SPI_iRst_out" O1 , inpin "u7/u9/T_iA_int" CLK , ; net "SPI_iRst_out" , cfg " _BELSIG:PAD,PAD,SPI_iRst_out:SPI_iRst_out", ; net "dbShort" , cfg " _BELSIG:PAD,PAD,dbShort:dbShort", ; net "dbShort_IBUF" , outpin "dbShort" I , inpin "u1/Done_EthiRST" F4 , inpin "u1/Done_Wait20" F3 , inpin "u1/Done_Wait20" G1 , inpin "u1/Eth_iRst_or0000_inv" F1 , inpin "u1/p4/count<0>" F4 , ; net "fClk" , cfg " _BELSIG:PAD,PAD,fClk:fClk", ; net "fClk_BUFGP" , outpin "fClk_BUFGP/BUFG" O , inpin "u0/u2/TickCount<0>" CLK , inpin "u0/u2/TickCount_11" CLK , inpin "u0/u2/u2/count<0>" CLK , inpin "u0/u2/u2/count<3>" CLK , ; net "fClk_BUFGP/IBUFG" , outpin "fClk" I , inpin "fClk_BUFGP/BUFG" I0 , ; net "iRD" , cfg " _BELSIG:PAD,PAD,iRD:iRD", ; net "iWR" , cfg " _BELSIG:PAD,PAD,iWR:iWR", ; net "r1/state<0>" , outpin "r1/state<0>" XQ , inpin "DAC_iRst_OBUF" G1 , inpin "u1/Go" G4 , inpin "u1/g1/Qa" F3 , inpin "u1/g1/Qa" G3 , inpin "u4/u1/Qa" F3 , inpin "u4/u1/Qa" G1 , inpin "u6/u1/Q_int" F2 , inpin "u6/u1/Q_int" SR , inpin "u8/VoltData_10_and0000" G2 , inpin "u8/u2/Q_int" G1 , ; net "r1/state<1>" , outpin "r1/state<0>" YQ , inpin "DAC_iRst_OBUF" G2 , inpin "u1/Go" G2 , inpin "u1/g1/Qa" F2 , inpin "u1/g1/Qa" G2 , inpin "u4/u1/Qa" F1 , inpin "u4/u1/Qa" G3 , inpin "u6/u1/Q_int" F4 , inpin "u6/u1/Q_int" G2 , inpin "u8/VoltData_10_and0000" G1 , inpin "u8/u2/Q_int" G3 , ; net "r1/state<2>" , outpin "r1/state<2>" YQ , inpin "DAC_iRst_OBUF" G4 , inpin "u1/Go" G3 , inpin "u1/g1/Qa" SR , inpin "u4/u1/Qa" F4 , inpin "u4/u1/Qa" G4 , inpin "u6/u1/Q_int" F3 , inpin "u6/u1/Q_int" G3 , inpin "u8/VoltData_10_and0000" G3 , inpin "u8/u2/Q_int" G2 , ; net "state_D<0>LogicTrst19" , outpin "state_D<0>LogicTrst19" X , inpin "state_D<0>LogicTrst82" F2 , ; net "state_D<0>LogicTrst40" , outpin "state_D<0>LogicTrst40" X , inpin "state_D<0>LogicTrst82" F1 , ; net "state_D<0>LogicTrst49" , outpin "u5/count<0>" X , inpin "state_D<0>LogicTrst82" F3 , ; net "state_D<0>LogicTrst82" , outpin "state_D<0>LogicTrst82" X , inpin "r1/state<0>" F2 , ; net "u0/u2/ALE_mux0001" , outpin "u0/u2/ALE_mux0001" X , inpin "ALE" O1 , ; net "u0/u2/ALE_not0001" , outpin "u0/u2/ALE_not0001" X , inpin "ALE" OTCLK1 , ; net "u0/u2/Mtridata_AD_mux0000<0>" , outpin "u0/u2/Mtridata_AD_mux0000<0>" X , inpin "AD<0>" O1 , inpin "AD<3>" O1 , ; net "u0/u2/Mtrien_AD_mux0000" , outpin "u0/u2/Mtrien_AD_mux0000" X , inpin "AD<0>" T1 , inpin "AD<1>" T1 , inpin "AD<2>" T1 , inpin "AD<3>" T1 , inpin "AD<4>" T1 , inpin "AD<5>" T1 , inpin "AD<6>" T1 , inpin "AD<7>" T1 , ; net "u0/u2/Mtrien_AD_not0001" , outpin "u0/u2/Mtrien_AD_not0001" X , inpin "AD<0>" OTCLK1 , inpin "AD<1>" OTCLK1 , inpin "AD<2>" OTCLK1 , inpin "AD<3>" OTCLK1 , inpin "AD<4>" OTCLK1 , inpin "AD<5>" OTCLK1 , inpin "AD<6>" OTCLK1 , inpin "AD<7>" OTCLK1 , ; net "u0/u2/RWflag" , outpin "u0/u2/RWflag" XQ , inpin "iWR" O1 , inpin "u0/u2/RWflag" BX , ; net "u0/u2/TickCount<0>" , outpin "u0/u2/TickCount<0>" YQ , inpin "u0/u2/TickCount<0>" BY , inpin "u0/u2/TickCount_11" G2 , ; net "u0/u2/TickCount<1>" , outpin "u0/u2/TickCount_1_BUFG" O , inpin "r1/state<0>" CLK , inpin "r1/state<2>" CLK , inpin "u1/InitDelay<0>" CLK , inpin "u1/g1/Qa" CLK , inpin "u1/g1/Qb" CLK , inpin "u1/g2/count<0>" CLK , inpin "u1/g2/count<3>" CLK , inpin "u1/g2/count<4>" CLK , inpin "u1/g2/count<6>" CLK , inpin "u1/g3/u0/Q" CLK , inpin "u1/g3/u0/Q_int" CLK , inpin "u1/g3/u1/Qa" CLK , inpin "u1/g3/u1/Qb" CLK , inpin "u1/g3/u2/u1/Q" CLK , inpin "u1/g3/u2/u1/Q_int" CLK , inpin "u1/g3/u3/u1/Q" CLK , inpin "u1/g3/u3/u1/Q_int" CLK , inpin "u1/m1/u1/Q" CLK , inpin "u1/m1/u1/Q_int" CLK , inpin "u1/m2/m2/u1/Q" CLK , inpin "u1/m2/m2/u1/Q_int" CLK , inpin "u1/m3/m2/u1/Q" CLK , inpin "u1/m3/m2/u1/Q_int" CLK , inpin "u1/m4/m2/u1/Q" CLK , inpin "u1/m4/m2/u1/Q_int" CLK , inpin "u1/m5/m2/u1/Q" CLK , inpin "u1/m5/m2/u1/Q_int" CLK , inpin "u1/m6/a1/u1/Q" CLK , inpin "u1/m6/a1/u1/Q_int" CLK , inpin "u1/m6/b1/u1/Q" CLK , inpin "u1/m6/b1/u1/Q_int" CLK , inpin "u1/m6/b2/u1/Q" CLK , inpin "u1/m6/b2/u1/Q_int" CLK , inpin "u1/m6/m/m2/u1/Q" CLK , inpin "u1/m6/m/m2/u1/Q_int" CLK , inpin "u1/m7/m2/u1/Q" CLK , inpin "u1/m7/m2/u1/Q_int" CLK , inpin "u1/p4/count<0>" CLK , inpin "u1/p4/count<11>" CLK , inpin "u1/p4/count<1>" CLK , inpin "u1/p4/count<3>" CLK , inpin "u1/p4/count<5>" CLK , inpin "u1/p4/count<7>" CLK , inpin "u1/p4/count<9>" CLK , inpin "u1/p5/count<0>" CLK , inpin "u1/p5/count<11>" CLK , inpin "u1/p5/count<1>" CLK , inpin "u1/p5/count<3>" CLK , inpin "u1/p5/count<5>" CLK , inpin "u1/p5/count<7>" CLK , inpin "u1/p5/count<9>" CLK , inpin "u1/p6b/Q" CLK , inpin "u1/p6b/Q_int" CLK , inpin "u1/p7/u0/Q" CLK , inpin "u1/p7/u0/Q_int" CLK , inpin "u1/p7/u1/Qa" CLK , inpin "u1/p7/u1/Qb" CLK , inpin "u1/p7/u2/u1/Q" CLK , inpin "u1/p7/u2/u1/Q_int" CLK , inpin "u1/p7/u3/u1/Q" CLK , inpin "u1/p7/u3/u1/Q_int" CLK , inpin "u2/u1/Qb" CLK , inpin "u2/u3/u1/u1/Q" CLK , inpin "u2/u3/u1/u1/Q_int" CLK , inpin "u4/u1/Qa" CLK , inpin "u4/u1/Qb" CLK , inpin "u4/u2/u0/Q" CLK , inpin "u4/u2/u0/Q_int" CLK , inpin "u4/u2/u1/Qa" CLK , inpin "u4/u2/u1/Qb" CLK , inpin "u4/u2/u2/u1/Q" CLK , inpin "u4/u2/u2/u1/Q_int" CLK , inpin "u4/u2/u3/u1/Q" CLK , inpin "u4/u2/u3/u1/Q_int" CLK , inpin "u5/u1/Q" CLK , inpin "u5/u2/Qa" CLK , inpin "u5/u2/Qb" CLK , inpin "u6/u1/Q" CLK , inpin "u6/u1/Q_int" CLK , inpin "u6/u3/Qa" CLK , inpin "u6/u3/Qb" CLK , inpin "u6/u4/Q" CLK , inpin "u6/u4/Q_int" CLK , inpin "u7/iRst_out_inv_shift10" CLK , inpin "u7/iRst_out_inv_shift12" CLK , inpin "u7/iRst_out_inv_shift2" CLK , inpin "u7/iRst_out_inv_shift4" CLK , inpin "u7/iRst_out_inv_shift6" CLK , inpin "u7/iRst_out_inv_shift8" CLK , inpin "u7/u1/count<0>" CLK , inpin "u7/u1/count<1>" CLK , inpin "u7/u1/count<3>" CLK , inpin "u7/u1/count<4>" CLK , inpin "u7/u2/Q" CLK , inpin "u7/u2/Q_int" CLK , inpin "u7/u3/u1/Q" CLK , inpin "u7/u3/u1/Q_int" CLK , inpin "u7/u4/ff" CLK , inpin "u7/u5/A_addr<1>" CLK , inpin "u7/u5/A_addr<2>" CLK , inpin "u7/u6/reg<13>" CLK , inpin "u7/u6/reg<14>" CLK , inpin "u7/u6/reg_121" CLK , inpin "u7/u7/line" CLK , inpin "u7/u7/reg<11>" CLK , inpin "u7/u7/reg<4>" CLK , inpin "u7/u7/reg<7>" CLK , inpin "u7/u7/reg<9>" CLK , inpin "u7/u8/Addr_mem<1>" CLK , inpin "u7/u8/Addr_mem<2>" CLK , inpin "u7/u8/Done_int" CLK , inpin "u7/u8/Go_next_clk" CLK , inpin "u7/u8/Wr_int" CLK , inpin "u7/u8/u1/Q" CLK , inpin "u7/u8/u1/Q_int" CLK , inpin "u7/u8/u2/Q" CLK , inpin "u7/u8/u2/Q_int" CLK , inpin "u7/u9/CycNum" CLK , inpin "u7/u9/RstCyc" CLK , inpin "u8/l1/u1/Q" CLK , inpin "u8/l1/u1/Q_int" CLK , inpin "u8/l2/u1/Q" CLK , inpin "u8/l2/u1/Q_int" CLK , inpin "u8/lenregH/Data<0>" CLK , inpin "u8/lenregL/Data<0>" CLK , inpin "u8/u1/Qa" CLK , inpin "u8/u1/Qb" CLK , inpin "u8/u2/Q" CLK , inpin "u8/u2/Q_int" CLK , inpin "u8/u3/u1/u1/Q" CLK , inpin "u8/u3/u1/u1/Q_int" CLK , inpin "u9/u1/count<0>" CLK , inpin "u9/u1/count<2>" CLK , inpin "u9/u1/count<4>" CLK , inpin "u9/u2/LineOut" CLK , inpin "u9/u2/SReg<11>" CLK , inpin "u9/u2/SReg<13>" CLK , inpin "u9/u2/SReg<14>" CLK , inpin "u9/u2/SReg<15>" CLK , inpin "u9/u2/SReg<16>" CLK , inpin "u9/u2/SReg<17>" CLK , inpin "u9/u2/SReg<18>" CLK , inpin "u9/u2/SReg<1>" CLK , inpin "u9/u2/SReg<3>" CLK , inpin "u9/u2/SReg<5>" CLK , inpin "u9/u2/SReg<7>" CLK , inpin "u9/u2/SReg<9>" CLK , inpin "u9/u4/Qa" CLK , inpin "u9/u4/Qb" CLK , inpin "u9/u5/Q" CLK , inpin "u9/u5/Q_int" CLK , ; net "u0/u2/TickCount_11" , outpin "u0/u2/TickCount_11" YQ , inpin "SPI_SCLK" O1 , inpin "u0/u2/TickCount_11" F2 , inpin "u0/u2/TickCount_11" G4 , inpin "u0/u2/TickCount_1_BUFG" I0 , inpin "u1/m1/En_and0000" F2 , inpin "u1/m1/En_and0000" G4 , inpin "u1/m6/b1/En_and0000" F2 , inpin "u1/m6/b1/En_and0000" G2 , inpin "u1/m6/b2/En_and0000" F3 , inpin "u1/m6/b2/En_and0000" G3 , inpin "u1/p7/u2/En_and0000" F1 , inpin "u1/p7/u2/En_and0000" G2 , inpin "u1/p7/u3/En_and0000" F1 , inpin "u1/p7/u3/En_and0000" G1 , inpin "u5/s2/u1/En" BY , inpin "u8/u3/u1/En_and0000" F3 , inpin "u8/u3/u1/En_and0000" G3 , ; net "u0/u2/u2/En_int" , outpin "u0/u2/u2/count<0>" X , inpin "u0/u2/u2/count<0>" CE , inpin "u0/u2/u2/count<3>" CE , ; net "u0/u2/u2/count<0>" , outpin "u0/u2/u2/count<0>" XQ , inpin "u0/u2/ALE_mux0001" G3 , inpin "u0/u2/ALE_not0001" G2 , inpin "u0/u2/Mtridata_AD_mux0000<0>" G3 , inpin "u0/u2/Mtrien_AD_mux0000" F4 , inpin "u0/u2/Mtrien_AD_mux0000" G4 , inpin "u0/u2/Mtrien_AD_not0001" F1 , inpin "u0/u2/Mtrien_AD_not0001" G1 , inpin "u0/u2/RWflag" F3 , inpin "u0/u2/RWflag" G3 , inpin "u0/u2/u2/count<0>" BX , inpin "u0/u2/u2/count<0>" F4 , inpin "u0/u2/u2/count<0>" G2 , inpin "u0/u2/u2/count<3>" F2 , inpin "u0/u2/u2/count<3>" G2 , ; net "u0/u2/u2/count<1>" , outpin "u0/u2/u2/count<0>" YQ , inpin "u0/u2/ALE_mux0001" G4 , inpin "u0/u2/ALE_not0001" G3 , inpin "u0/u2/Mtridata_AD_mux0000<0>" G2 , inpin "u0/u2/Mtrien_AD_mux0000" F3 , inpin "u0/u2/Mtrien_AD_mux0000" G3 , inpin "u0/u2/Mtrien_AD_not0001" F2 , inpin "u0/u2/Mtrien_AD_not0001" G2 , inpin "u0/u2/RWflag" F2 , inpin "u0/u2/RWflag" G2 , inpin "u0/u2/u2/count<0>" F3 , inpin "u0/u2/u2/count<0>" G4 , inpin "u0/u2/u2/count<3>" F4 , inpin "u0/u2/u2/count<3>" G4 , ; net "u0/u2/u2/count<2>" , outpin "u0/u2/u2/count<3>" YQ , inpin "u0/u2/ALE_mux0001" G1 , inpin "u0/u2/ALE_not0001" G4 , inpin "u0/u2/Mtridata_AD_mux0000<0>" G1 , inpin "u0/u2/Mtrien_AD_mux0000" F2 , inpin "u0/u2/Mtrien_AD_mux0000" G2 , inpin "u0/u2/Mtrien_AD_not0001" F3 , inpin "u0/u2/Mtrien_AD_not0001" G3 , inpin "u0/u2/RWflag" F1 , inpin "u0/u2/RWflag" G1 , inpin "u0/u2/u2/count<0>" F1 , inpin "u0/u2/u2/count<3>" F1 , inpin "u0/u2/u2/count<3>" G1 , ; net "u0/u2/u2/count<3>" , outpin "u0/u2/u2/count<3>" XQ , inpin "u0/u2/ALE_mux0001" BX , inpin "u0/u2/ALE_not0001" BX , inpin "u0/u2/Mtridata_AD_mux0000<0>" BX , inpin "u0/u2/Mtrien_AD_mux0000" BX , inpin "u0/u2/Mtrien_AD_not0001" BX , inpin "u0/u2/RWflag" F4 , inpin "u0/u2/RWflag" G4 , inpin "u0/u2/u2/count<0>" F2 , inpin "u0/u2/u2/count<3>" F3 , ; net "u1/Done_EthiRST" , outpin "u1/Done_EthiRST" X , inpin "u1/g3/En" BY , ; net "u1/Done_EthiRST7" , outpin "u1/Done_EthiRST7" X , inpin "u1/Done_EthiRST" F1 , ; net "u1/Done_Filt" , outpin "u1/Done_Hash1" Y , inpin "u1/Done_Hash1" F4 , inpin "u1/f1/Working" CE , inpin "u1/f2/Working" BY , ; net "u1/Done_Hash1" , outpin "u1/Done_Hash1" X , inpin "u1/f2/Working" CE , inpin "u1/f3/Working" BY , ; net "u1/Done_Hash2" , outpin "r1/state<0>" Y , inpin "r1/state<0>" F4 , inpin "r1/state<2>" G1 , inpin "u1/f3/Working" CE , ; net "u1/Done_INT0" , outpin "u1/Done_SelfInit" Y , inpin "u1/i1/Working" CE , inpin "u1/i2/Working" BY , ; net "u1/Done_INT1" , outpin "u1/Done_p1" Y , inpin "u1/Done_p0" G3 , inpin "u1/Done_p1" F3 , inpin "u1/i2/Working" CE , inpin "u1/p0/Working" BY , ; net "u1/Done_IPGR" , outpin "u1/Done_IPGR" X , inpin "u1/m4/m3/Working" CE , inpin "u1/m5/m1/Working" BY , ; net "u1/Done_IPGT" , outpin "u1/Done_IPGT" X , inpin "u1/m3/m3/Working" CE , inpin "u1/m4/m1/Working" BY , ; net "u1/Done_LEDdis" , outpin "u1/m1/u1/Q_int" X , inpin "u1/p10/Working" CE , ; net "u1/Done_MAC" , outpin "u1/Done_MAC" X , inpin "u1/f1/Working" BY , inpin "u1/m7/m3/Working" CE , ; net "u1/Done_MACAddr" , outpin "u1/m7/m2/u1/Q_int" Y , inpin "u1/m7/m1/Working" BY , inpin "u1/m7/m2/u1/Q_int" F4 , ; net "u1/Done_MACCF" , outpin "u1/Done_MACCF" X , inpin "u1/m2/m3/Working" CE , inpin "u1/m3/m1/Working" BY , ; net "u1/Done_MAXLEN" , outpin "u1/m6/a1/u1/Q_int" X , inpin "u1/m5/m3/Working" CE , inpin "u1/m6/WordCount<0>" SR , ; net "u1/Done_Phy" , outpin "u1/m1/u1/Q_int" Y , inpin "u1/m1/u1/Q_int" F3 , inpin "u1/p9/Working" BY , ; net "u1/Done_ResCfg" , outpin "u1/Done_ResCfg" Y , inpin "u1/p10/Working" BY , inpin "u1/p9/Working" CE , ; net "u1/Done_SelfInit" , outpin "u1/Done_SelfInit" X , inpin "u1/Done_p1" G2 , inpin "u1/i1/Working" BY , ; net "u1/Done_Wait20" , outpin "u1/Done_Wait20" X , inpin "u1/p6b/Q_int" SR , ; net "u1/Done_Wait210" , outpin "u1/Done_Wait210" X , inpin "u1/p6b/Q_int" F1 , ; net "u1/Done_Wait215" , outpin "u1/Done_Wait215" X , inpin "u1/p6b/Q_int" F4 , ; net "u1/Done_Wait25/O" , outpin "u1/p6b/Q_int" Y , inpin "u1/p6b/Q_int" F3 , ; net "u1/Done_p0" , outpin "u1/Done_p0" Y , inpin "u1/p0/Working" CE , inpin "u1/p1/Working" BY , ; net "u1/Done_p1" , outpin "u1/Done_p1" X , inpin "u1/Done_p2" G2 , inpin "u1/p1/Working" CE , inpin "u1/p3/Working" BY , inpin "u1/p4/count<0>" G3 , ; net "u1/Done_p2" , outpin "u1/Done_p2" Y , inpin "u1/p2/Working" BY , inpin "u1/p3/Working" CE , ; net "u1/Done_p3" , outpin "u1/p4/count<0>" Y , inpin "u1/Done_Wait20" F1 , inpin "u1/p2/Working" CE , inpin "u1/p4/count<0>" F2 , ; net "u1/Eth_iRst_or0000_inv" , outpin "u1/Eth_iRst_or0000_inv" X , inpin "Eth_iRst" T1 , ; net "u1/Go" , outpin "u1/Go" X , inpin "u1/Done_EthiRST" F2 , inpin "u1/Done_Wait20" G3 , inpin "u1/Eth_iRst_or0000_inv" F2 , ; net "u1/InitDelay<0>" , outpin "u1/InitDelay<0>" XQ , inpin "u1/Go" BX , inpin "u1/InitDelay<0>" BX , inpin "u1/InitDelay<0>" G1 , ; net "u1/InitDelay<1>" , outpin "u1/InitDelay<0>" YQ , inpin "u1/InitDelay<0>" CE , inpin "u1/InitDelay<0>" G4 , ; net "u1/Result<0>1" , outpin "u1/Result<0>1" X , inpin "u1/p5/count<0>" F1 , ; net "u1/Result<0>1/ProtoComp0.C1VDD.1_0" vcc, outpin "XDL_DUMMY_CLB_X4Y5_SLICE_X7Y9" X , inpin "u1/m7/m1/Working" CLK , ; net "u1/Result<0>1/ProtoComp0.C1VDD.1_1" vcc, outpin "XDL_DUMMY_CLB_X4Y4_SLICE_X6Y7" X , inpin "u1/m4/m3/Working" CLK , inpin "u1/m5/m1/Working" CLK , inpin "u1/m5/m2/aH/Working" CLK , ; net "u1/Result<0>1/ProtoComp0.C1VDD.1_2" vcc, outpin "u1/m6/a1/aH/Working" X , inpin "u1/m4/m1/Working" CLK , inpin "u1/m4/m2/aH/Working" CLK , inpin "u1/m4/m2/aL/Working" CLK , inpin "u1/m5/m3/Working" CLK , inpin "u1/m6/m/m2/aL/Working" CLK , ; net "u1/Result<0>1/ProtoComp0.C1VDD.1_3" vcc, outpin "XDL_DUMMY_CLB_X4Y1_SLICE_X6Y1" X , inpin "u1/m2/m3/Working" CLK , inpin "u1/m3/m1/Working" CLK , inpin "u1/m3/m2/aL/Working" CLK , inpin "u1/m3/m3/Working" CLK , inpin "u1/m6/a1/aH/Working" CLK , inpin "u1/m6/a1/aL/Working" CLK , inpin "u1/m6/b2/En" CLK , inpin "u1/m6/m/m1/Working" CLK , ; net "u1/Result<0>1/ProtoComp0.C1VDD.1_4" vcc, outpin "XDL_DUMMY_CLB_X3Y3_SLICE_X4Y4" X , inpin "u1/m3/m2/aH/Working" CLK , inpin "u1/m6/m/m2/aH/Working" CLK , ; net "u1/Result<0>1/ProtoComp0.C1VDD.1_5" vcc, outpin "u1/m4/m2/aL/Working" X , inpin "u1/m5/m2/aL/Working" CLK , ; net "u1/Result<0>1/ProtoComp0.C1VDD.1_6" vcc, outpin "XDL_DUMMY_CLB_X7Y5_SLICE_X13Y9" X , inpin "u1/m6/m/m3/Working" CLK , ; net "u1/Result<0>1/ProtoComp0.C1VDD.1_7" vcc, outpin "XDL_DUMMY_CLB_X8Y7_SLICE_X15Y13" X , inpin "u8/l1/En" CLK , ; net "u1/Result<0>1/ProtoComp0.C1VDD.1_8" vcc, outpin "XDL_DUMMY_CLB_X7Y1_SLICE_X12Y1" X , inpin "u1/g3/u2/En" CLK , inpin "u1/m2/m1/Working" CLK , inpin "u1/m2/m2/aH/Working" CLK , inpin "u1/m2/m2/aL/Working" CLK , inpin "u1/p7/u2/En" CLK , ; net "u1/Result<0>1/ProtoComp0.C1VDD.1_9" vcc, outpin "XDL_DUMMY_CLB_X7Y9_SLICE_X12Y17" X , inpin "u8/u5/Working" CLK , ; net "u1/Result<0>1/ProtoComp0.C1VDD.1_10" vcc, outpin "XDL_DUMMY_CLB_X8Y1_SLICE_X14Y1" X , inpin "u1/f1/Working" CLK , inpin "u1/f2/Working" CLK , inpin "u1/f3/Working" CLK , inpin "u1/m1/En" CLK , ; net "u1/Result<0>1/ProtoComp0.C1VDD.1_11" vcc, outpin "u1/f2/Working" X , inpin "u1/m7/m2/aH/Working" CLK , inpin "u1/m7/m2/aL/Working" CLK , inpin "u1/m7/m3/Working" CLK , inpin "u2/u4/Working" CLK , inpin "u8/u3/u1/En1" CLK , ; net "u1/Result<0>1/ProtoComp0.C1VDD.1_12" vcc, outpin "XDL_DUMMY_CLB_X6Y9_SLICE_X10Y17" X , inpin "u1/m6/b1/En" CLK , inpin "u2/u3/u1/En" CLK , inpin "u8/l2/En" CLK , ; net "u1/Result<0>1/ProtoComp0.C1VDD.1_13" vcc, outpin "XDL_DUMMY_CLB_X14Y4_SLICE_X19Y7" X , inpin "u1/g3/u3/En" CLK , ; net "u1/Result<0>1/ProtoComp0.C1VDD.1_14" vcc, outpin "XDL_DUMMY_CLB_X14Y2_SLICE_X19Y3" X , inpin "u1/i2/Working" CLK , inpin "u1/p1/Working" CLK , inpin "u1/p7/u3/En" CLK , ; net "u1/Result<0>1/ProtoComp0.C1VDD.1_15" vcc, outpin "XDL_DUMMY_CLB_X15Y12_SLICE_X20Y23" X , inpin "u4/u2/u2/En" CLK , inpin "u4/u2/u3/En" CLK , inpin "u5/s2/u1/En" CLK , ; net "u1/Result<0>1/ProtoComp0.C1VDD.1_16" vcc, outpin "XDL_DUMMY_CLB_X15Y5_SLICE_X21Y9" X , inpin "u1/p0/Working" CLK , inpin "u1/p3/Working" CLK , ; net "u1/Result<0>1/ProtoComp0.C1VDD.1_17" vcc, outpin "XDL_DUMMY_CLB_X15Y8_SLICE_X21Y14" X , inpin "u1/p2/Working" CLK , ; net "u1/Result<0>1/ProtoComp0.C1VDD.1_18" vcc, outpin "XDL_DUMMY_CLB_X16Y2_SLICE_X23Y3" X , inpin "u1/i1/Working" CLK , inpin "u1/p10/Working" CLK , inpin "u1/p9/Working" CLK , ; net "u1/Result<0>1/ProtoComp0.C1VDD.1_19" vcc, outpin "XDL_DUMMY_CLB_X3Y11_VCC_X4Y13" VCCOUT , inpin "u9/u4/Qa" BY , ; net "u1/Result<0>1/ProtoComp0.C1VDD.1_20" vcc, outpin "XDL_DUMMY_CLB_X1Y12_VCC_X2Y14" VCCOUT , inpin "u7/iRst_out_inv_shift2" BY , ; net "u1/Result<0>1/ProtoComp0.C1VDD.1_21" vcc, outpin "XDL_DUMMY_CLB_X1Y14_VCC_X2Y16" VCCOUT , inpin "u7/u6/reg_121" G2 , inpin "u7/u6/reg_121" G4 , ; net "u1/Result<0>1/ProtoComp0.C1VDD.1_22" vcc, outpin "XDL_DUMMY_CLB_X8Y10_VCC_X9Y12" VCCOUT , inpin "r1/state<0>" BY , ; net "u1/Result<0>1/ProtoComp0.C1VDD.1_23" vcc, outpin "XDL_DUMMY_TIOIB_X9Y17_VCC_X11Y19" VCCOUT , inpin "iRD" O1 , ; net "u1/Result<0>1/ProtoComp0.C1VDD.1_24" vcc, outpin "XDL_DUMMY_CLKB_X8Y0_VCC_X10Y0" VCCOUT , inpin "Rst_IBUF_BUFG" S , inpin "fClk_BUFGP/BUFG" S , ; net "u1/Result<0>1/ProtoComp0.C1VDD.1_25" vcc, outpin "XDL_DUMMY_CLKT_X8Y17_VCC_X10Y19" VCCOUT , inpin "u0/u2/TickCount_1_BUFG" S , inpin "u8/u3/u1/En_BUFG" S , ; net "u1/Result<0>2" , outpin "u1/Result<0>2" X , inpin "u1/p4/count<0>" F3 , ; net "u1/Result<10>" , outpin "u1/Result<10>" X , inpin "u1/p5/count<11>" G3 , ; net "u1/Result<10>1" , outpin "u1/Result<10>1" X , inpin "u1/p4/count<11>" G3 , ; net "u1/Result<11>" , outpin "u1/Result<10>" Y , inpin "u1/p5/count<11>" F2 , ; net "u1/Result<11>1" , outpin "u1/Result<10>1" Y , inpin "u1/p4/count<11>" F2 , ; net "u1/Result<1>1" , outpin "u1/Result<0>1" Y , inpin "u1/p5/count<1>" G1 , ; net "u1/Result<1>2" , outpin "u1/Result<0>2" Y , inpin "u1/p4/count<1>" G2 , ; net "u1/Result<2>" , outpin "u1/Result<2>" X , inpin "u1/p5/count<3>" G3 , ; net "u1/Result<2>1" , outpin "u1/Result<2>1" X , inpin "u1/p4/count<3>" G3 , ; net "u1/Result<3>" , outpin "u1/Result<2>" Y , inpin "u1/p5/count<3>" F2 , ; net "u1/Result<3>1" , outpin "u1/Result<2>1" Y , inpin "u1/p4/count<3>" F2 , ; net "u1/Result<4>" , outpin "u1/Result<4>" X , inpin "u1/p5/count<5>" G4 , ; net "u1/Result<4>1" , outpin "u1/Result<4>1" X , inpin "u1/p4/count<5>" G4 , ; net "u1/Result<5>" , outpin "u1/Result<4>" Y , inpin "u1/p5/count<5>" F1 , ; net "u1/Result<5>1" , outpin "u1/Result<4>1" Y , inpin "u1/p4/count<5>" F1 , ; net "u1/Result<6>" , outpin "u1/Result<6>" X , inpin "u1/p5/count<7>" G3 , ; net "u1/Result<6>1" , outpin "u1/Result<6>1" X , inpin "u1/p4/count<7>" G3 , ; net "u1/Result<7>" , outpin "u1/Result<6>" Y , inpin "u1/p5/count<7>" F2 , ; net "u1/Result<7>1" , outpin "u1/Result<6>1" Y , inpin "u1/p4/count<7>" F2 , ; net "u1/Result<8>" , outpin "u1/Result<8>" X , inpin "u1/p5/count<9>" G4 , ; net "u1/Result<8>1" , outpin "u1/Result<8>1" X , inpin "u1/p4/count<9>" G3 , ; net "u1/Result<9>" , outpin "u1/Result<8>" Y , inpin "u1/p5/count<9>" F1 , ; net "u1/Result<9>1" , outpin "u1/Result<8>1" Y , inpin "u1/p4/count<9>" F1 , ; net "u1/f1/Working" , outpin "u1/f1/Working" XQ , inpin "N48" G4 , inpin "u1/Done_Hash1" G1 , ; net "u1/f2/Working" , outpin "u1/f2/Working" XQ , inpin "N48" F4 , inpin "N48" G2 , inpin "u1/Done_Hash1" F1 , ; net "u1/f3/Working" , outpin "u1/f3/Working" XQ , inpin "N48" F2 , inpin "N48" G3 , ; net "u1/g1/Qa" , outpin "u1/g1/Qa" XQ , inpin "u1/g1/Qb" BY , ; net "u1/g1/Qb" , outpin "u1/g1/Qb" YQ , inpin "u1/Go" G1 , ; net "u1/g2/Mcount_count4_bdd0" , outpin "u1/g2/count<4>" Y , inpin "u1/g2/count<4>" F4 , inpin "u1/g2/count<6>" F2 , inpin "u1/g2/count<6>" G2 , ; net "u1/g2/count<0>" , outpin "u1/g2/count<0>" XQ , inpin "u1/Done_EthiRST" G1 , inpin "u1/g2/count<0>" BX , inpin "u1/g2/count<0>" F4 , inpin "u1/g2/count<0>" G4 , inpin "u1/g2/count<3>" F2 , inpin "u1/g2/count<3>" G1 , inpin "u1/g2/count<4>" G1 , ; net "u1/g2/count<1>" , outpin "u1/g2/count<0>" YQ , inpin "u1/Done_EthiRST" G4 , inpin "u1/g2/count<0>" F2 , inpin "u1/g2/count<0>" G1 , inpin "u1/g2/count<3>" F3 , inpin "u1/g2/count<3>" G3 , inpin "u1/g2/count<4>" G4 , ; net "u1/g2/count<2>" , outpin "u1/g2/count<3>" YQ , inpin "u1/Done_EthiRST7" F4 , inpin "u1/g2/count<0>" F1 , inpin "u1/g2/count<3>" F1 , inpin "u1/g2/count<3>" G4 , inpin "u1/g2/count<4>" G3 , ; net "u1/g2/count<3>" , outpin "u1/g2/count<3>" XQ , inpin "u1/Done_EthiRST7" F3 , inpin "u1/g2/count<0>" F3 , inpin "u1/g2/count<3>" F4 , inpin "u1/g2/count<4>" G2 , ; net "u1/g2/count<4>" , outpin "u1/g2/count<4>" XQ , inpin "u1/Done_EthiRST7" F2 , inpin "u1/Eth_iRst_or0000_inv" G1 , inpin "u1/g2/count<4>" F2 , inpin "u1/g2/count<6>" F1 , inpin "u1/g2/count<6>" G1 , ; net "u1/g2/count<5>" , outpin "u1/g2/count<6>" YQ , inpin "u1/Done_EthiRST7" F1 , inpin "u1/Eth_iRst_or0000_inv" G4 , inpin "u1/g2/count<6>" F4 , inpin "u1/g2/count<6>" G4 , ; net "u1/g2/count<6>" , outpin "u1/g2/count<6>" XQ , inpin "u1/Done_EthiRST" G2 , inpin "u1/Eth_iRst_or0000_inv" G3 , inpin "u1/g2/count<6>" F3 , ; net "u1/g2/count_cmp_eq0000" , outpin "u1/Eth_iRst_or0000_inv" Y , inpin "u1/Done_Wait20" G2 , inpin "u1/Eth_iRst_or0000_inv" F4 , ; net "u1/g2/count_not0003" , outpin "u1/Done_Wait20" Y , inpin "u1/g2/count<0>" CE , inpin "u1/g2/count<3>" CE , inpin "u1/g2/count<4>" CE , inpin "u1/g2/count<6>" CE , ; net "u1/g3/En" , outpin "u1/g3/En" XQ , inpin "u1/Done_SelfInit" F2 , inpin "u1/Done_SelfInit" G2 , inpin "u1/g3/u0/Q_int" BY , ; net "u1/g3/u0/Q" , outpin "u1/g3/u0/Q" YQ , inpin "u1/g3/u1/Qa" BY , inpin "u1/g3/u2/u1/Q_int" BY , ; net "u1/g3/u0/Q_int" , outpin "u1/g3/u0/Q_int" YQ , inpin "u1/g3/u0/Q" BY , ; net "u1/g3/u1/Qa" , outpin "u1/g3/u1/Qa" YQ , inpin "u1/g3/u1/Qb" BY , ; net "u1/g3/u1/Qb" , outpin "u1/g3/u1/Qb" YQ , inpin "u1/g3/u2/u1/Q_int" SR , ; net "u1/g3/u2/En" , outpin "u1/g3/u2/En" XQ , inpin "u1/g3/u3/u1/Q_int" BY , ; net "u1/g3/u2/En_and0000" , outpin "u0/u2/TickCount_11" X , inpin "u1/g3/u2/En" BY , ; net "u1/g3/u2/u1/Q" , outpin "u1/g3/u2/u1/Q" YQ , inpin "u0/u2/TickCount_11" F4 , ; net "u1/g3/u2/u1/Q_int" , outpin "u1/g3/u2/u1/Q_int" YQ , inpin "u1/g3/u2/u1/Q" BY , ; net "u1/g3/u3/En" , outpin "u1/g3/u3/En" XQ , inpin "u1/Done_SelfInit" F3 , inpin "u1/Done_SelfInit" G1 , ; net "u1/g3/u3/En_and0000" , outpin "u1/m1/En_and0000" Y , inpin "u1/g3/u3/En" BY , ; net "u1/g3/u3/u1/Q" , outpin "u1/g3/u3/u1/Q" YQ , inpin "u1/m1/En_and0000" G2 , ; net "u1/g3/u3/u1/Q_int" , outpin "u1/g3/u3/u1/Q_int" YQ , inpin "u1/g3/u3/u1/Q" BY , ; net "u1/i1/Working" , outpin "u1/i1/Working" XQ , inpin "u1/Done_SelfInit" G3 , inpin "u1/Done_p1" G3 , ; net "u1/i2/Working" , outpin "u1/i2/Working" XQ , inpin "u1/Done_p1" G4 , ; net "u1/m1/En" , outpin "u1/m1/En" XQ , inpin "u1/m2/m1/Working" BY , inpin "u1/m2/m2/u1/Q_int" G2 , ; net "u1/m1/En_and0000" , outpin "u1/m1/En_and0000" X , inpin "u1/m1/En" BY , ; net "u1/m1/u1/Q" , outpin "u1/m1/u1/Q" YQ , inpin "u1/m1/En_and0000" F4 , ; net "u1/m1/u1/Q_int" , outpin "u1/m1/u1/Q_int" XQ , inpin "u1/m1/u1/Q" BY , ; net "u1/m2/Done_MAC2B" , outpin "u1/Done_MACCF" Y , inpin "u1/Done_MACCF" F2 , inpin "u1/m2/m2/aL/Working" CE , inpin "u1/m2/m3/Working" BY , inpin "u1/m3/m2/u1/Q_int" G4 , ; net "u1/m2/Done_SetMACAddr" , outpin "u1/m2/m2/u1/Q_int" Y , inpin "u1/m2/m1/Working" CE , ; net "u1/m2/m1/Working" , outpin "u1/m2/m1/Working" XQ , inpin "u1/m2/m2/u1/Q_int" G1 , ; net "u1/m2/m2/Done_AddrH" , outpin "u1/m2/m2/Done_AddrH" Y , inpin "u1/m2/m2/aH/Working" CE , inpin "u1/m2/m2/aL/Working" BY , ; net "u1/m2/m2/aH/Working" , outpin "u1/m2/m2/aH/Working" XQ , inpin "u1/Done_MACCF" G2 , inpin "u1/m2/m2/Done_AddrH" G4 , ; net "u1/m2/m2/aL/Working" , outpin "u1/m2/m2/aL/Working" XQ , inpin "u1/Done_MACCF" G4 , ; net "u1/m2/m2/u1/Q" , outpin "u1/m2/m2/u1/Q" YQ , inpin "u1/Done_MACCF" G1 , inpin "u1/m2/m2/Done_AddrH" G1 , inpin "u1/m2/m2/aH/Working" BY , ; net "u1/m2/m2/u1/Q_int" , outpin "u1/m2/m2/u1/Q_int" YQ , inpin "u1/m2/m2/u1/Q" BY , ; net "u1/m2/m3/Working" , outpin "u1/m2/m3/Working" XQ , inpin "u1/Done_MACCF" F3 , inpin "u1/m3/m2/u1/Q_int" G3 , ; net "u1/m3/Done_MAC2B" , outpin "u1/Done_IPGT" Y , inpin "u1/Done_IPGT" F3 , inpin "u1/m3/m2/aL/Working" CE , inpin "u1/m3/m3/Working" BY , inpin "u1/m4/m2/u1/Q_int" G1 , ; net "u1/m3/Done_SetMACAddr" , outpin "u1/m3/m2/u1/Q_int" Y , inpin "u1/m3/m1/Working" CE , ; net "u1/m3/m1/Working" , outpin "u1/m3/m1/Working" XQ , inpin "u1/m3/m2/u1/Q_int" G1 , ; net "u1/m3/m2/Done_AddrH" , outpin "u1/m3/m2/Done_AddrH" Y , inpin "u1/m3/m2/aH/Working" CE , inpin "u1/m3/m2/aL/Working" BY , ; net "u1/m3/m2/aH/Working" , outpin "u1/m3/m2/aH/Working" XQ , inpin "u1/Done_IPGT" G1 , inpin "u1/m3/m2/Done_AddrH" G4 , ; net "u1/m3/m2/aL/Working" , outpin "u1/m3/m2/aL/Working" XQ , inpin "u1/Done_IPGT" G2 , ; net "u1/m3/m2/u1/Q" , outpin "u1/m3/m2/u1/Q" YQ , inpin "u1/Done_IPGT" G3 , inpin "u1/m3/m2/Done_AddrH" G2 , inpin "u1/m3/m2/aH/Working" BY , ; net "u1/m3/m2/u1/Q_int" , outpin "u1/m3/m2/u1/Q_int" YQ , inpin "u1/m3/m2/u1/Q" BY , ; net "u1/m3/m3/Working" , outpin "u1/m3/m3/Working" XQ , inpin "u1/Done_IPGT" F2 , inpin "u1/m4/m2/u1/Q_int" G2 , ; net "u1/m4/Done_MAC2B" , outpin "u1/Done_IPGR" Y , inpin "u1/Done_IPGR" F4 , inpin "u1/m4/m2/aL/Working" CE , inpin "u1/m4/m3/Working" BY , inpin "u1/m5/m2/u1/Q_int" G2 , ; net "u1/m4/Done_SetMACAddr" , outpin "u1/m4/m2/u1/Q_int" Y , inpin "u1/m4/m1/Working" CE , ; net "u1/m4/m1/Working" , outpin "u1/m4/m1/Working" XQ , inpin "u1/m4/m2/u1/Q_int" G4 , ; net "u1/m4/m2/Done_AddrH" , outpin "u1/m4/m2/Done_AddrH" Y , inpin "u1/m4/m2/aH/Working" CE , inpin "u1/m4/m2/aL/Working" BY , ; net "u1/m4/m2/aH/Working" , outpin "u1/m4/m2/aH/Working" XQ , inpin "u1/Done_IPGR" G1 , inpin "u1/m4/m2/Done_AddrH" G1 , ; net "u1/m4/m2/aL/Working" , outpin "u1/m4/m2/aL/Working" XQ , inpin "u1/Done_IPGR" G4 , ; net "u1/m4/m2/u1/Q" , outpin "u1/m4/m2/u1/Q" YQ , inpin "u1/Done_IPGR" G2 , inpin "u1/m4/m2/Done_AddrH" G4 , inpin "u1/m4/m2/aH/Working" BY , ; net "u1/m4/m2/u1/Q_int" , outpin "u1/m4/m2/u1/Q_int" YQ , inpin "u1/m4/m2/u1/Q" BY , ; net "u1/m4/m3/Working" , outpin "u1/m4/m3/Working" XQ , inpin "u1/Done_IPGR" F3 , inpin "u1/m5/m2/u1/Q_int" G4 , ; net "u1/m5/Done_MAC2B" , outpin "u1/m6/a1/u1/Q_int" Y , inpin "u1/m5/m2/aL/Working" CE , inpin "u1/m5/m3/Working" BY , inpin "u1/m6/a1/u1/Q_int" F4 , ; net "u1/m5/Done_SetMACAddr" , outpin "u1/m5/m2/u1/Q_int" Y , inpin "u1/m5/m1/Working" CE , ; net "u1/m5/m1/Working" , outpin "u1/m5/m1/Working" XQ , inpin "u1/m5/m2/u1/Q_int" G3 , ; net "u1/m5/m2/Done_AddrH" , outpin "u1/m5/m2/Done_AddrH" Y , inpin "u1/m5/m2/aH/Working" CE , inpin "u1/m5/m2/aL/Working" BY , ; net "u1/m5/m2/aH/Working" , outpin "u1/m5/m2/aH/Working" XQ , inpin "u1/m5/m2/Done_AddrH" G4 , inpin "u1/m6/a1/u1/Q_int" G1 , ; net "u1/m5/m2/aL/Working" , outpin "u1/m5/m2/aL/Working" XQ , inpin "u1/m6/a1/u1/Q_int" G4 , ; net "u1/m5/m2/u1/Q" , outpin "u1/m5/m2/u1/Q" YQ , inpin "u1/m5/m2/Done_AddrH" G2 , inpin "u1/m5/m2/aH/Working" BY , inpin "u1/m6/a1/u1/Q_int" G3 , ; net "u1/m5/m2/u1/Q_int" , outpin "u1/m5/m2/u1/Q_int" YQ , inpin "u1/m5/m2/u1/Q" BY , ; net "u1/m5/m3/Working" , outpin "u1/m5/m3/Working" XQ , inpin "u1/m6/a1/u1/Q_int" F1 , ; net "u1/m6/Done_FlashAddr" , outpin "u1/m6/Done_FlashAddr" X , inpin "u1/m6/a1/aL/Working" CE , inpin "u1/m6/b1/u1/Q_int" SR , ; net "u1/m6/Done_Word" , outpin "u1/m6/b1/u1/Q_int" Y , inpin "u1/m6/b1/u1/Q_int" F4 , inpin "u1/m6/m/m3/Working" CE , ; net "u1/m6/Done_Word_inv" , outpin "u1/m6/Done_Word_inv" X , inpin "u1/m6/WordCount<0>" CLK , ; net "u1/m6/WordCount<0>" , outpin "u1/m6/WordCount<0>" XQ , inpin "u1/m6/WordCount<0>" BX , inpin "u1/m6/WordCount<0>" F2 , inpin "u1/m6/WordCount<0>" G4 , inpin "u1/m6/b1/u1/Q_int" F1 , ; net "u1/m6/WordCount<1>" , outpin "u1/m6/WordCount<0>" YQ , inpin "u1/m6/WordCount<0>" G3 , inpin "u1/m6/b1/u1/Q_int" F2 , inpin "u1/m7/m2/u1/Q_int" G3 , ; net "u1/m6/a1/Done_AddrH" , outpin "u1/m6/Done_FlashAddr" Y , inpin "u1/m6/a1/aH/Working" CE , inpin "u1/m6/a1/aL/Working" BY , ; net "u1/m6/a1/aH/Working" , outpin "u1/m6/a1/aH/Working" XQ , inpin "u1/m6/Done_FlashAddr" F1 , inpin "u1/m6/Done_FlashAddr" G1 , ; net "u1/m6/a1/aL/Working" , outpin "u1/m6/a1/aL/Working" XQ , inpin "u1/m6/Done_FlashAddr" F2 , ; net "u1/m6/a1/u1/Q" , outpin "u1/m6/a1/u1/Q" YQ , inpin "u1/m6/Done_FlashAddr" F3 , inpin "u1/m6/Done_FlashAddr" G4 , inpin "u1/m6/a1/aH/Working" BY , ; net "u1/m6/a1/u1/Q_int" , outpin "u1/m6/a1/u1/Q_int" XQ , inpin "u1/m6/a1/u1/Q" BY , ; net "u1/m6/b1/En" , outpin "u1/m6/b1/En" XQ , inpin "u1/m6/b2/u1/Q_int" BY , ; net "u1/m6/b1/En_and0000" , outpin "u1/m6/b1/En_and0000" X , inpin "u1/m6/b1/En" BY , ; net "u1/m6/b1/u1/Q" , outpin "u1/m6/b1/u1/Q" YQ , inpin "u1/m6/b1/En_and0000" F4 , ; net "u1/m6/b1/u1/Q_int" , outpin "u1/m6/b1/u1/Q_int" XQ , inpin "u1/m6/b1/u1/Q" BY , ; net "u1/m6/b2/En" , outpin "u1/m6/b2/En" XQ , inpin "u1/m6/m/m1/Working" BY , inpin "u1/m6/m/m2/u1/Q_int" G1 , ; net "u1/m6/b2/En_and0000" , outpin "u1/m6/b2/En_and0000" X , inpin "u1/m6/b2/En" BY , ; net "u1/m6/b2/u1/Q" , outpin "u1/m6/b2/u1/Q" YQ , inpin "u1/m6/b2/En_and0000" F4 , ; net "u1/m6/b2/u1/Q_int" , outpin "u1/m6/b2/u1/Q_int" YQ , inpin "u1/m6/b2/u1/Q" BY , ; net "u1/m6/m/Done_MAC2B" , outpin "u1/m6/Done_Word_inv" Y , inpin "u1/m6/Done_Word_inv" F3 , inpin "u1/m6/b1/u1/Q_int" G3 , inpin "u1/m6/m/m2/aL/Working" CE , inpin "u1/m6/m/m3/Working" BY , inpin "u1/m7/m2/u1/Q_int" G2 , ; net "u1/m6/m/Done_SetMACAddr" , outpin "u1/m6/m/m2/u1/Q_int" Y , inpin "u1/m6/m/m1/Working" CE , ; net "u1/m6/m/m1/Working" , outpin "u1/m6/m/m1/Working" XQ , inpin "u1/m6/m/m2/u1/Q_int" G4 , ; net "u1/m6/m/m2/Done_AddrH" , outpin "u1/m6/m/m2/Done_AddrH" Y , inpin "u1/m6/m/m2/aH/Working" CE , inpin "u1/m6/m/m2/aL/Working" BY , ; net "u1/m6/m/m2/aH/Working" , outpin "u1/m6/m/m2/aH/Working" XQ , inpin "u1/m6/Done_Word_inv" G2 , inpin "u1/m6/m/m2/Done_AddrH" G4 , ; net "u1/m6/m/m2/aL/Working" , outpin "u1/m6/m/m2/aL/Working" XQ , inpin "u1/m6/Done_Word_inv" G4 , ; net "u1/m6/m/m2/u1/Q" , outpin "u1/m6/m/m2/u1/Q" YQ , inpin "u1/m6/Done_Word_inv" G1 , inpin "u1/m6/m/m2/Done_AddrH" G3 , inpin "u1/m6/m/m2/aH/Working" BY , ; net "u1/m6/m/m2/u1/Q_int" , outpin "u1/m6/m/m2/u1/Q_int" YQ , inpin "u1/m6/m/m2/u1/Q" BY , ; net "u1/m6/m/m3/Working" , outpin "u1/m6/m/m3/Working" XQ , inpin "u1/m6/Done_Word_inv" F1 , inpin "u1/m6/b1/u1/Q_int" G1 , inpin "u1/m7/m2/u1/Q_int" G4 , ; net "u1/m7/Done_MAC2B" , outpin "u1/Done_MAC" Y , inpin "r1/state<0>" G4 , inpin "u1/Done_Hash1" G4 , inpin "u1/Done_MAC" F4 , inpin "u1/m7/m2/aL/Working" CE , inpin "u1/m7/m3/Working" BY , ; net "u1/m7/Done_SetMACAddr" , outpin "u1/m7/m2/u1/Q_int" X , inpin "u1/m7/m1/Working" CE , ; net "u1/m7/m1/Working" , outpin "u1/m7/m1/Working" XQ , inpin "u1/m7/m2/u1/Q_int" F2 , ; net "u1/m7/m2/Done_AddrH" , outpin "u1/m7/m2/Done_AddrH" Y , inpin "u1/m7/m2/aH/Working" CE , inpin "u1/m7/m2/aL/Working" BY , ; net "u1/m7/m2/aH/Working" , outpin "u1/m7/m2/aH/Working" XQ , inpin "u1/Done_MAC" G2 , inpin "u1/m7/m2/Done_AddrH" G1 , ; net "u1/m7/m2/aL/Working" , outpin "u1/m7/m2/aL/Working" XQ , inpin "u1/Done_MAC" G4 , ; net "u1/m7/m2/u1/Q" , outpin "u1/m7/m2/u1/Q" YQ , inpin "u1/Done_MAC" G3 , inpin "u1/m7/m2/Done_AddrH" G3 , inpin "u1/m7/m2/aH/Working" BY , ; net "u1/m7/m2/u1/Q_int" , outpin "u1/m7/m2/u1/Q_int" XQ , inpin "u1/m7/m2/u1/Q" BY , ; net "u1/m7/m3/Working" , outpin "u1/m7/m3/Working" XQ , inpin "r1/state<0>" G2 , inpin "u1/Done_Hash1" G2 , inpin "u1/Done_MAC" F2 , ; net "u1/p0/Working" , outpin "u1/p0/Working" XQ , inpin "u1/Done_p0" G4 , inpin "u1/Done_p1" F1 , ; net "u1/p10/Working" , outpin "u1/p10/Working" XQ , inpin "u1/m1/u1/Q_int" F1 , ; net "u1/p1/Working" , outpin "u1/p1/Working" XQ , inpin "u1/Done_p1" F4 , ; net "u1/p2/Working" , outpin "u1/p2/Working" XQ , inpin "u1/p4/count<0>" G4 , ; net "u1/p3/Working" , outpin "u1/p3/Working" XQ , inpin "u1/Done_p2" G4 , inpin "u1/p4/count<0>" G1 , ; net "u1/p4/Mcount_count_cy<1>" , outpin "u1/Result<0>2" COUT , inpin "u1/Result<2>1" CIN , ; net "u1/p4/Mcount_count_cy<3>" , outpin "u1/Result<2>1" COUT , inpin "u1/Result<4>1" CIN , ; net "u1/p4/Mcount_count_cy<5>" , outpin "u1/Result<4>1" COUT , inpin "u1/Result<6>1" CIN , ; net "u1/p4/Mcount_count_cy<7>" , outpin "u1/Result<6>1" COUT , inpin "u1/Result<8>1" CIN , ; net "u1/p4/Mcount_count_cy<9>" , outpin "u1/Result<8>1" COUT , inpin "u1/Result<10>1" CIN , ; net "u1/p4/count<0>" , outpin "u1/p4/count<0>" XQ , inpin "u1/Result<0>2" F4 , inpin "u1/p4/count_not0001" G1 , inpin "u1/p5/Mcount_count_eqn_05" F1 , ; net "u1/p4/count<10>" , outpin "u1/p4/count<11>" YQ , inpin "u1/Result<10>1" F4 , inpin "u1/p5/Mcount_count_eqn_015" F3 , inpin "u1/p5/Mcount_count_eqn_015" G3 , ; net "u1/p4/count<11>" , outpin "u1/p4/count<11>" XQ , inpin "u1/Result<10>1" G1 , inpin "u1/p5/Mcount_count_eqn_015" F4 , inpin "u1/p5/Mcount_count_eqn_015" G4 , ; net "u1/p4/count<1>" , outpin "u1/p4/count<1>" YQ , inpin "u1/Result<0>2" G4 , inpin "u1/p4/count_not0001" G2 , inpin "u1/p5/Mcount_count_eqn_05" F2 , ; net "u1/p4/count<2>" , outpin "u1/p4/count<3>" YQ , inpin "u1/Result<2>1" F1 , inpin "u1/p4/count_not0001" G4 , inpin "u1/p5/Mcount_count_eqn_05" F4 , ; net "u1/p4/count<3>" , outpin "u1/p4/count<3>" XQ , inpin "u1/Result<2>1" G4 , inpin "u1/p4/count_not0001" G3 , inpin "u1/p5/Mcount_count_eqn_05" F3 , ; net "u1/p4/count<4>" , outpin "u1/p4/count<5>" YQ , inpin "u1/Result<4>1" F2 , inpin "u1/p5/Mcount_count_eqn_010" F1 , inpin "u1/p5/Mcount_count_eqn_010" G1 , ; net "u1/p4/count<5>" , outpin "u1/p4/count<5>" XQ , inpin "u1/Result<4>1" G3 , inpin "u1/p5/Mcount_count_eqn_010" F2 , inpin "u1/p5/Mcount_count_eqn_010" G2 , ; net "u1/p4/count<6>" , outpin "u1/p4/count<7>" YQ , inpin "u1/Result<6>1" F4 , inpin "u1/p5/Mcount_count_eqn_010" F4 , inpin "u1/p5/Mcount_count_eqn_010" G4 , ; net "u1/p4/count<7>" , outpin "u1/p4/count<7>" XQ , inpin "u1/Result<6>1" G1 , inpin "u1/p5/Mcount_count_eqn_010" F3 , inpin "u1/p5/Mcount_count_eqn_010" G3 , ; net "u1/p4/count<8>" , outpin "u1/p4/count<9>" YQ , inpin "u1/Result<8>1" F3 , inpin "u1/p5/Mcount_count_eqn_015" F1 , inpin "u1/p5/Mcount_count_eqn_015" G1 , ; net "u1/p4/count<9>" , outpin "u1/p4/count<9>" XQ , inpin "u1/Result<8>1" G1 , inpin "u1/p5/Mcount_count_eqn_015" F2 , inpin "u1/p5/Mcount_count_eqn_015" G2 , ; net "u1/p4/count_not0001" , outpin "u1/p4/count_not0001" X , inpin "u1/p4/count<0>" F1 , ; net "u1/p4/count_not000114" , outpin "u1/p4/count_not0001" Y , inpin "u1/p4/count<11>" F3 , inpin "u1/p4/count<11>" G2 , inpin "u1/p4/count<1>" G1 , inpin "u1/p4/count<3>" F4 , inpin "u1/p4/count<3>" G1 , inpin "u1/p4/count<5>" F4 , inpin "u1/p4/count<5>" G1 , inpin "u1/p4/count<7>" F4 , inpin "u1/p4/count<7>" G4 , inpin "u1/p4/count<9>" F2 , inpin "u1/p4/count<9>" G2 , inpin "u1/p4/count_not0001" F4 , ; net "u1/p4/count_not00014" , outpin "u1/p5/Mcount_count_eqn_010" Y , inpin "u1/p4/count<11>" F1 , inpin "u1/p4/count<11>" G1 , inpin "u1/p4/count<1>" G3 , inpin "u1/p4/count<3>" F1 , inpin "u1/p4/count<3>" G2 , inpin "u1/p4/count<5>" F2 , inpin "u1/p4/count<5>" G2 , inpin "u1/p4/count<7>" F1 , inpin "u1/p4/count<7>" G1 , inpin "u1/p4/count<9>" F4 , inpin "u1/p4/count<9>" G1 , inpin "u1/p4/count_not0001" F1 , ; net "u1/p4/count_not00019" , outpin "u1/p5/Mcount_count_eqn_015" Y , inpin "u1/p4/count<11>" F4 , inpin "u1/p4/count<11>" G4 , inpin "u1/p4/count<1>" G4 , inpin "u1/p4/count<3>" F3 , inpin "u1/p4/count<3>" G4 , inpin "u1/p4/count<5>" F3 , inpin "u1/p4/count<5>" G3 , inpin "u1/p4/count<7>" F3 , inpin "u1/p4/count<7>" G2 , inpin "u1/p4/count<9>" F3 , inpin "u1/p4/count<9>" G4 , inpin "u1/p4/count_not0001" F3 , ; net "u1/p5/Mcount_count_cy<1>" , outpin "u1/Result<0>1" COUT , inpin "u1/Result<2>" CIN , ; net "u1/p5/Mcount_count_cy<3>" , outpin "u1/Result<2>" COUT , inpin "u1/Result<4>" CIN , ; net "u1/p5/Mcount_count_cy<5>" , outpin "u1/Result<4>" COUT , inpin "u1/Result<6>" CIN , ; net "u1/p5/Mcount_count_cy<7>" , outpin "u1/Result<6>" COUT , inpin "u1/Result<8>" CIN , ; net "u1/p5/Mcount_count_cy<9>" , outpin "u1/Result<8>" COUT , inpin "u1/Result<10>" CIN , ; net "u1/p5/Mcount_count_eqn_010" , outpin "u1/p5/Mcount_count_eqn_010" X , inpin "u1/p5/count<0>" G4 , ; net "u1/p5/Mcount_count_eqn_015" , outpin "u1/p5/Mcount_count_eqn_015" X , inpin "u1/p5/count<0>" G2 , ; net "u1/p5/Mcount_count_eqn_024" , outpin "u1/p5/count<0>" Y , inpin "u1/p5/count<0>" F4 , ; net "u1/p5/Mcount_count_eqn_05" , outpin "u1/p5/Mcount_count_eqn_05" X , inpin "u1/p5/count<0>" G1 , ; net "u1/p5/count<0>" , outpin "u1/p5/count<0>" XQ , inpin "u1/Result<0>1" F4 , inpin "u1/p5/count_not0001" G2 , inpin "u1/p6b/Q_int" G3 , ; net "u1/p5/count<10>" , outpin "u1/p5/count<11>" YQ , inpin "u1/Done_Wait215" F4 , inpin "u1/Done_Wait215" G4 , inpin "u1/Result<10>" F1 , ; net "u1/p5/count<11>" , outpin "u1/p5/count<11>" XQ , inpin "u1/Done_Wait215" F2 , inpin "u1/Done_Wait215" G2 , inpin "u1/Result<10>" G4 , ; net "u1/p5/count<1>" , outpin "u1/p5/count<1>" YQ , inpin "u1/Result<0>1" G4 , inpin "u1/p5/count_not0001" G4 , inpin "u1/p6b/Q_int" G1 , ; net "u1/p5/count<2>" , outpin "u1/p5/count<3>" YQ , inpin "u1/Result<2>" F4 , inpin "u1/p5/count_not0001" G1 , inpin "u1/p6b/Q_int" G4 , ; net "u1/p5/count<3>" , outpin "u1/p5/count<3>" XQ , inpin "u1/Result<2>" G1 , inpin "u1/p5/count_not0001" G3 , inpin "u1/p6b/Q_int" G2 , ; net "u1/p5/count<4>" , outpin "u1/p5/count<5>" YQ , inpin "u1/Done_Wait210" F4 , inpin "u1/Done_Wait210" G3 , inpin "u1/Result<4>" F3 , ; net "u1/p5/count<5>" , outpin "u1/p5/count<5>" XQ , inpin "u1/Done_Wait210" F2 , inpin "u1/Done_Wait210" G2 , inpin "u1/Result<4>" G2 , ; net "u1/p5/count<6>" , outpin "u1/p5/count<7>" YQ , inpin "u1/Done_Wait210" F1 , inpin "u1/Done_Wait210" G1 , inpin "u1/Result<6>" F3 , ; net "u1/p5/count<7>" , outpin "u1/p5/count<7>" XQ , inpin "u1/Done_Wait210" F3 , inpin "u1/Done_Wait210" G4 , inpin "u1/Result<6>" G2 , ; net "u1/p5/count<8>" , outpin "u1/p5/count<9>" YQ , inpin "u1/Done_Wait215" F1 , inpin "u1/Done_Wait215" G1 , inpin "u1/Result<8>" F4 , ; net "u1/p5/count<9>" , outpin "u1/p5/count<9>" XQ , inpin "u1/Done_Wait215" F3 , inpin "u1/Done_Wait215" G3 , inpin "u1/Result<8>" G1 , ; net "u1/p5/count_not0001" , outpin "u1/p5/count_not0001" X , inpin "u1/p5/count<0>" F3 , ; net "u1/p5/count_not000114" , outpin "u1/p5/count_not0001" Y , inpin "u1/p5/count<11>" F1 , inpin "u1/p5/count<11>" G1 , inpin "u1/p5/count<1>" G2 , inpin "u1/p5/count<3>" F3 , inpin "u1/p5/count<3>" G1 , inpin "u1/p5/count<5>" F3 , inpin "u1/p5/count<5>" G3 , inpin "u1/p5/count<7>" F4 , inpin "u1/p5/count<7>" G4 , inpin "u1/p5/count<9>" F2 , inpin "u1/p5/count<9>" G2 , inpin "u1/p5/count_not0001" F3 , ; net "u1/p5/count_not00014" , outpin "u1/Done_Wait210" Y , inpin "u1/p5/count<11>" F4 , inpin "u1/p5/count<11>" G4 , inpin "u1/p5/count<1>" G3 , inpin "u1/p5/count<3>" F1 , inpin "u1/p5/count<3>" G2 , inpin "u1/p5/count<5>" F2 , inpin "u1/p5/count<5>" G1 , inpin "u1/p5/count<7>" F1 , inpin "u1/p5/count<7>" G1 , inpin "u1/p5/count<9>" F3 , inpin "u1/p5/count<9>" G1 , inpin "u1/p5/count_not0001" F2 , ; net "u1/p5/count_not00019" , outpin "u1/Done_Wait215" Y , inpin "u1/p5/count<11>" F3 , inpin "u1/p5/count<11>" G2 , inpin "u1/p5/count<1>" G4 , inpin "u1/p5/count<3>" F4 , inpin "u1/p5/count<3>" G4 , inpin "u1/p5/count<5>" F4 , inpin "u1/p5/count<5>" G2 , inpin "u1/p5/count<7>" F3 , inpin "u1/p5/count<7>" G2 , inpin "u1/p5/count<9>" F4 , inpin "u1/p5/count<9>" G3 , inpin "u1/p5/count_not0001" F1 , ; net "u1/p6b/Q" , outpin "u1/p6b/Q" YQ , inpin "u1/p7/En" BY , ; net "u1/p6b/Q_int" , outpin "u1/p6b/Q_int" XQ , inpin "u1/p6b/Q" BY , ; net "u1/p7/En" , outpin "u1/p7/En" XQ , inpin "u1/Done_ResCfg" G4 , inpin "u1/m1/u1/Q_int" G1 , inpin "u1/p7/u0/Q_int" BY , ; net "u1/p7/u0/Q" , outpin "u1/p7/u0/Q" YQ , inpin "u1/p7/u1/Qa" BY , inpin "u1/p7/u2/u1/Q_int" BY , ; net "u1/p7/u0/Q_int" , outpin "u1/p7/u0/Q_int" YQ , inpin "u1/p7/u0/Q" BY , ; net "u1/p7/u1/Qa" , outpin "u1/p7/u1/Qa" YQ , inpin "u1/p7/u1/Qb" BY , ; net "u1/p7/u1/Qb" , outpin "u1/p7/u1/Qb" YQ , inpin "u1/p7/u2/u1/Q_int" SR , ; net "u1/p7/u2/En" , outpin "u1/p7/u2/En" XQ , inpin "u1/p7/u3/u1/Q_int" BY , ; net "u1/p7/u2/En_and0000" , outpin "u1/p7/u2/En_and0000" X , inpin "u1/p7/u2/En" BY , ; net "u1/p7/u2/u1/Q" , outpin "u1/p7/u2/u1/Q" YQ , inpin "u1/p7/u2/En_and0000" F4 , ; net "u1/p7/u2/u1/Q_int" , outpin "u1/p7/u2/u1/Q_int" YQ , inpin "u1/p7/u2/u1/Q" BY , ; net "u1/p7/u3/En" , outpin "u1/p7/u3/En" XQ , inpin "u1/Done_ResCfg" G2 , inpin "u1/m1/u1/Q_int" G3 , ; net "u1/p7/u3/En_and0000" , outpin "u1/p7/u3/En_and0000" X , inpin "u1/p7/u3/En" BY , ; net "u1/p7/u3/u1/Q" , outpin "u1/p7/u3/u1/Q" YQ , inpin "u1/p7/u3/En_and0000" F2 , ; net "u1/p7/u3/u1/Q_int" , outpin "u1/p7/u3/u1/Q_int" YQ , inpin "u1/p7/u3/u1/Q" BY , ; net "u1/p9/Working" , outpin "u1/p9/Working" XQ , inpin "u1/Done_ResCfg" G1 , inpin "u1/m1/u1/Q_int" F4 , ; net "u2/Done_Skip" , outpin "u2/Done_Skip" X , inpin "r1/state<0>" F3 , inpin "r1/state<2>" G4 , inpin "u2/u4/Working" CE , ; net "u2/En" , outpin "u4/u1/Qa" Y , inpin "u2/ReadCount<1>" CE , inpin "u2/ReadCount<3>" CE , ; net "u2/En_or0000" , outpin "DAC_iRst_OBUF" Y , inpin "DAC_iRst_OBUF" F4 , inpin "u2/Done_Skip" G4 , inpin "u2/ReadCount_or0000" G1 , inpin "u2/u3/u1/u1/Q_int" G4 , ; net "u2/Go_Skip" , outpin "u2/Done_Skip" Y , inpin "u2/Done_Skip" F3 , inpin "u2/u4/Working" BY , ; net "u2/ReadCount<0>" , outpin "u2/ReadCount<1>" YQ , inpin "DAC_iRst_OBUF" F2 , inpin "u2/ReadCount<1>" BY , inpin "u2/ReadCount<1>" F2 , inpin "u2/ReadCount<1>" G4 , inpin "u2/ReadCount<3>" F3 , inpin "u2/ReadCount<3>" G3 , inpin "u2/u3/u1/u1/Q_int" F3 , inpin "u2/u3/u1/u1/Q_int" G3 , ; net "u2/ReadCount<1>" , outpin "u2/ReadCount<1>" XQ , inpin "u2/ReadCount<1>" F4 , inpin "u2/ReadCount<3>" F1 , inpin "u2/ReadCount<3>" G1 , ; net "u2/ReadCount<2>" , outpin "u2/ReadCount<3>" YQ , inpin "u2/ReadCount<3>" F2 , inpin "u2/ReadCount<3>" G2 , ; net "u2/ReadCount<3>" , outpin "u2/ReadCount<3>" XQ , inpin "DAC_iRst_OBUF" F1 , inpin "u2/ReadCount<1>" G2 , inpin "u2/ReadCount<3>" F4 , inpin "u2/u3/u1/u1/Q_int" F1 , inpin "u2/u3/u1/u1/Q_int" G1 , ; net "u2/ReadCount_or0000" , outpin "u2/ReadCount_or0000" Y , inpin "u2/ReadCount<1>" SR , inpin "u2/ReadCount<3>" SR , ; net "u2/u1/Qa" , outpin "u4/u1/Qa" YQ , inpin "u2/u1/Qb" BY , ; net "u2/u1/Qb" , outpin "u2/u1/Qb" YQ , inpin "u2/Done_Skip" G1 , inpin "u2/ReadCount_or0000" G3 , inpin "u2/u3/u1/u1/Q_int" G2 , ; net "u2/u3/u1/En" , outpin "u2/u3/u1/En" XQ , inpin "DAC_iRst_OBUF" F3 , inpin "u2/Done_Skip" G3 , inpin "u2/ReadCount<1>" CLK , inpin "u2/ReadCount<3>" CLK , inpin "u2/u3/u1/u1/Q_int" BX , ; net "u2/u3/u1/En_and0000" , outpin "u1/m6/b1/En_and0000" Y , inpin "u2/u3/u1/En" BY , ; net "u2/u3/u1/u1/Q" , outpin "u2/u3/u1/u1/Q" YQ , inpin "u1/m6/b1/En_and0000" G4 , ; net "u2/u3/u1/u1/Q_int" , outpin "u2/u3/u1/u1/Q_int" XQ , inpin "u2/u3/u1/u1/Q" BY , ; net "u2/u4/Working" , outpin "u2/u4/Working" XQ , inpin "u2/Done_Skip" F2 , ; net "u4/Go" , outpin "u6/u1/Q_int" X , inpin "u4/u2/En" BY , ; net "u4/u1/Qa" , outpin "u4/u1/Qa" XQ , inpin "u4/u1/Qb" BY , ; net "u4/u1/Qb" , outpin "u4/u1/Qb" YQ , inpin "u6/u1/Q_int" F1 , ; net "u4/u2/En" , outpin "u4/u2/En" XQ , inpin "state_D<0>LogicTrst19" F2 , inpin "u4/u2/u0/Q_int" BY , ; net "u4/u2/u0/Q" , outpin "u4/u2/u0/Q" YQ , inpin "u4/u2/u1/Qa" BY , inpin "u4/u2/u2/u1/Q_int" BY , ; net "u4/u2/u0/Q_int" , outpin "u4/u2/u0/Q_int" YQ , inpin "u4/u2/u0/Q" BY , ; net "u4/u2/u1/Qa" , outpin "u4/u2/u1/Qa" YQ , inpin "u4/u2/u1/Qb" BY , ; net "u4/u2/u1/Qb" , outpin "u4/u2/u1/Qb" YQ , inpin "u4/u2/u2/u1/Q_int" SR , ; net "u4/u2/u2/En" , outpin "u4/u2/u2/En" XQ , inpin "u4/u2/En" CLK , inpin "u4/u2/u3/u1/Q_int" BY , ; net "u4/u2/u2/En_and0000" , outpin "u1/p7/u3/En_and0000" Y , inpin "u4/u2/u2/En" BY , ; net "u4/u2/u2/u1/Q" , outpin "u4/u2/u2/u1/Q" YQ , inpin "u1/p7/u3/En_and0000" G2 , ; net "u4/u2/u2/u1/Q_int" , outpin "u4/u2/u2/u1/Q_int" YQ , inpin "u4/u2/u2/u1/Q" BY , ; net "u4/u2/u3/En" , outpin "u4/u2/u3/En" XQ , inpin "state_D<0>LogicTrst19" F1 , ; net "u4/u2/u3/En_and0000" , outpin "u8/u3/u1/En_and0000" Y , inpin "u4/u2/u3/En" BY , ; net "u4/u2/u3/u1/Q" , outpin "u4/u2/u3/u1/Q" YQ , inpin "u8/u3/u1/En_and0000" G4 , ; net "u4/u2/u3/u1/Q_int" , outpin "u4/u2/u3/u1/Q_int" YQ , inpin "u4/u2/u3/u1/Q" BY , ; net "u5/Go_Cyc14Step_inv" , outpin "u5/Go_Cyc14Step_inv" X , inpin "u5/count<0>" CLK , inpin "u5/count<3>" CLK , ; net "u5/Go_Cyc14Step_inv12" , outpin "u5/Go_Cyc14Step_inv12" X , inpin "u5/Go_Cyc14Step_inv" F1 , ; net "u5/Go_Cyc14Step_inv9" , outpin "u5/Go_Cyc14Step_inv12" Y , inpin "u5/Go_Cyc14Step_inv12" F3 , ; net "u5/InitGo" , outpin "u5/InitGo" Y , inpin "u5/count<0>" SR , inpin "u5/count<3>" SR , ; net "u5/count<0>" , outpin "u5/count<0>" XQ , inpin "u5/Go_Cyc14Step_inv12" F1 , inpin "u5/count<0>" BX , inpin "u5/count<0>" F2 , inpin "u5/count<0>" G1 , inpin "u5/count<3>" F4 , inpin "u5/count<3>" G4 , ; net "u5/count<1>" , outpin "u5/count<0>" YQ , inpin "state_D<0>LogicTrst19" F3 , inpin "u5/Go_Cyc14Step_inv" F4 , inpin "u5/count<0>" G4 , inpin "u5/count<3>" F1 , inpin "u5/count<3>" G1 , ; net "u5/count<2>" , outpin "u5/count<3>" YQ , inpin "state_D<0>LogicTrst19" G4 , inpin "u5/Go_Cyc14Step_inv" F3 , inpin "u5/count<3>" F3 , inpin "u5/count<3>" G3 , ; net "u5/count<3>" , outpin "u5/count<3>" XQ , inpin "state_D<0>LogicTrst19" G1 , inpin "u5/Go_Cyc14Step_inv" F2 , inpin "u5/count<3>" F2 , ; net "u5/s2/u1/En" , outpin "u5/s2/u1/En" XQ , inpin "state_D<0>LogicTrst19" G2 , inpin "u5/Go_Cyc14Step_inv" BX , ; net "u5/u1/Q" , outpin "u5/u1/Q" YQ , inpin "u5/InitGo" G4 , inpin "u5/u2/Qa" BY , ; net "u5/u1/Q_int" , outpin "u1/g1/Qa" YQ , inpin "u5/u1/Q" BY , ; net "u5/u2/Qa" , outpin "u5/u2/Qa" YQ , inpin "u5/u2/Qb" BY , ; net "u5/u2/Qb" , outpin "u5/u2/Qb" YQ , inpin "u5/InitGo" G1 , ; net "u6/Addr<0>" , outpin "u6/Addr<1>" YQ , inpin "u6/Addr<1>" BY , inpin "u6/Addr<1>" F4 , inpin "u6/Addr<1>" G4 , inpin "u6/Addr<3>" F3 , inpin "u6/Addr<3>" G3 , inpin "u7/u8/Addr_mem<1>" BY , inpin "u7/u8/Wr_int" F1 , ; net "u6/Addr<1>" , outpin "u6/Addr<1>" XQ , inpin "u6/Addr<1>" F3 , inpin "u6/Addr<1>" G3 , inpin "u6/Addr<3>" F4 , inpin "u6/Addr<3>" G4 , inpin "u7/u8/Addr_mem<1>" BX , inpin "u7/u8/Wr_int" G3 , ; net "u6/Addr<2>" , outpin "u6/Addr<3>" YQ , inpin "state_D<0>LogicTrst82" G3 , inpin "u6/Addr<3>" F2 , inpin "u6/Addr<3>" G2 , inpin "u7/u8/Addr_mem<2>" BY , inpin "u7/u8/Wr_int" G4 , ; net "u6/Addr<3>" , outpin "u6/Addr<3>" XQ , inpin "state_D<0>LogicTrst82" G1 , inpin "u6/Addr<3>" F1 , inpin "u7/u8/Wr_int_mux000363" G2 , inpin "u7/u9/T_iA_int" G1 , ; net "u6/Addr_or0000" , outpin "u6/Addr_or0000" Y , inpin "u6/Addr<1>" SR , inpin "u6/Addr<3>" SR , ; net "u6/stateEn_and0000_inv" , outpin "state_D<0>LogicTrst82" Y , inpin "r1/state<2>" G2 , inpin "state_D<0>LogicTrst82" F4 , ; net "u6/u1/Q" , outpin "u6/u1/Q" YQ , inpin "u6/Addr<1>" CE , inpin "u6/Addr<3>" CE , inpin "u6/Addr_or0000" G2 , inpin "u6/u3/Qa" BY , inpin "u7/u8/Wr_int_mux000363" G4 , ; net "u6/u1/Q_int" , outpin "u6/u1/Q_int" YQ , inpin "u6/u1/Q" BY , ; net "u6/u3/Qa" , outpin "u6/u3/Qa" YQ , inpin "u6/u3/Qb" BY , ; net "u6/u3/Qb" , outpin "u6/u3/Qb" YQ , inpin "u6/Addr_or0000" G4 , inpin "u7/u8/Wr_int_mux000363" G1 , ; net "u6/u4/Q" , outpin "u6/u4/Q" YQ , inpin "state_D<0>LogicTrst82" G4 , inpin "u7/u8/Wr_int_mux000363" G3 , ; net "u6/u4/Q_int" , outpin "u6/u4/Q_int" YQ , inpin "u6/u4/Q" BY , ; net "u7/Go_int" , outpin "u7/Go_int" X , inpin "u7/u4/ff" CE , ; net "u7/N01" , outpin "u7/u1/count<0>" Y , inpin "u7/u1/count<0>" F4 , inpin "u7/u1/count<1>" G1 , ; net "u7/iRst_out_inv" , outpin "SPI_iRst" Y , inpin "u7/iRst_out_inv_shift10" SR , inpin "u7/iRst_out_inv_shift12" SR , inpin "u7/iRst_out_inv_shift2" SR , inpin "u7/iRst_out_inv_shift4" SR , inpin "u7/iRst_out_inv_shift6" SR , inpin "u7/iRst_out_inv_shift8" SR , inpin "u7/u1/count<0>" SR , inpin "u7/u1/count<1>" SR , inpin "u7/u1/count<3>" SR , inpin "u7/u1/count<4>" SR , inpin "u7/u4/ff" SR , inpin "u7/u5/A_addr<1>" SR , inpin "u7/u5/A_addr<2>" SR , inpin "u7/u6/reg<13>" SR , inpin "u7/u6/reg<14>" SR , inpin "u7/u7/line" SR , inpin "u7/u7/reg<11>" SR , inpin "u7/u7/reg<4>" SR , inpin "u7/u7/reg<7>" SR , inpin "u7/u7/reg<9>" SR , inpin "u7/u8/Addr_mem<1>" SR , inpin "u7/u8/Addr_mem<2>" SR , inpin "u7/u8/Go_next_clk" SR , inpin "u7/u8/Wr_int" SR , inpin "u7/u9/CycNum" SR , inpin "u7/u9/RstCyc" SR , ; net "u7/iRst_out_inv_shift1" , outpin "u7/iRst_out_inv_shift2" YQ , inpin "u7/iRst_out_inv_shift2" BX , ; net "u7/iRst_out_inv_shift10" , outpin "u7/iRst_out_inv_shift10" XQ , inpin "u7/iRst_out_inv_shift12" BY , ; net "u7/iRst_out_inv_shift11" , outpin "u7/iRst_out_inv_shift12" YQ , inpin "u7/iRst_out_inv_shift12" BX , ; net "u7/iRst_out_inv_shift12" , outpin "u7/iRst_out_inv_shift12" XQ , inpin "u7/u6/reg<13>" G2 , ; net "u7/iRst_out_inv_shift2" , outpin "u7/iRst_out_inv_shift2" XQ , inpin "u7/iRst_out_inv_shift4" BY , ; net "u7/iRst_out_inv_shift3" , outpin "u7/iRst_out_inv_shift4" YQ , inpin "u7/iRst_out_inv_shift4" BX , ; net "u7/iRst_out_inv_shift4" , outpin "u7/iRst_out_inv_shift4" XQ , inpin "u7/iRst_out_inv_shift6" BY , ; net "u7/iRst_out_inv_shift5" , outpin "u7/iRst_out_inv_shift6" YQ , inpin "u7/iRst_out_inv_shift6" BX , ; net "u7/iRst_out_inv_shift6" , outpin "u7/iRst_out_inv_shift6" XQ , inpin "u7/iRst_out_inv_shift8" BY , ; net "u7/iRst_out_inv_shift7" , outpin "u7/iRst_out_inv_shift8" YQ , inpin "u7/iRst_out_inv_shift8" BX , ; net "u7/iRst_out_inv_shift8" , outpin "u7/iRst_out_inv_shift8" XQ , inpin "u7/iRst_out_inv_shift10" BY , ; net "u7/iRst_out_inv_shift9" , outpin "u7/iRst_out_inv_shift10" YQ , inpin "u7/iRst_out_inv_shift10" BX , ; net "u7/u1/count<0>" , outpin "u7/u1/count<0>" XQ , inpin "u7/u1/count<0>" F1 , inpin "u7/u1/count<1>" F4 , inpin "u7/u1/count<1>" G4 , inpin "u7/u1/count<3>" F4 , inpin "u7/u1/count<3>" G4 , inpin "u7/u1/count<4>" F1 , inpin "u7/u1/count<4>" G1 , inpin "u7/u1/count_not0001" F4 , inpin "u7/u8/Done_int" F1 , inpin "u7/u8/Done_int" G4 , inpin "u7/u8/Go_next_clk" F2 , inpin "u7/u8/Go_next_clk" G1 , inpin "u7/u8/Wr_int_and0000" G4 , ; net "u7/u1/count<1>" , outpin "u7/u1/count<1>" YQ , inpin "u7/u1/count<0>" F2 , inpin "u7/u1/count<1>" G3 , inpin "u7/u1/count<3>" F3 , inpin "u7/u1/count<3>" G1 , inpin "u7/u1/count<4>" F2 , inpin "u7/u1/count<4>" G2 , inpin "u7/u1/count_not0001" G1 , ; net "u7/u1/count<2>" , outpin "u7/u1/count<3>" YQ , inpin "u7/u1/count<0>" G2 , inpin "u7/u1/count<3>" F2 , inpin "u7/u1/count<3>" G3 , inpin "u7/u1/count<4>" F3 , inpin "u7/u1/count<4>" G3 , inpin "u7/u1/count_not0001" G3 , ; net "u7/u1/count<3>" , outpin "u7/u1/count<3>" XQ , inpin "u7/u1/count<0>" G4 , inpin "u7/u1/count<3>" F1 , inpin "u7/u1/count<4>" F4 , inpin "u7/u1/count<4>" G4 , inpin "u7/u1/count_not0001" F1 , ; net "u7/u1/count<4>" , outpin "u7/u1/count<4>" XQ , inpin "u7/u1/count<0>" G3 , inpin "u7/u1/count<1>" F1 , inpin "u7/u1/count<4>" BX , inpin "u7/u1/count_not0001" F2 , inpin "u7/u2/Q_int" BY , inpin "u7/u3/u1/Q_int" BY , inpin "u7/u7/line" F3 , inpin "u7/u7/line" G3 , inpin "u7/u7/reg<11>" F1 , inpin "u7/u7/reg<11>" G1 , inpin "u7/u7/reg<4>" BX , inpin "u7/u7/reg<4>" G1 , inpin "u7/u7/reg<7>" F1 , inpin "u7/u7/reg<7>" G3 , inpin "u7/u7/reg<9>" F4 , inpin "u7/u7/reg<9>" G4 , inpin "u7/u8/Done_int" F2 , inpin "u7/u8/Done_int" G2 , inpin "u7/u8/Go_next_clk" F3 , inpin "u7/u8/Go_next_clk" G3 , inpin "u7/u8/Wr_int_and0000" G2 , ; net "u7/u1/count_not0001" , outpin "u7/u1/count_not0001" X , inpin "u7/u1/count<0>" CE , inpin "u7/u1/count<1>" CE , inpin "u7/u1/count<3>" CE , inpin "u7/u1/count<4>" CE , ; net "u7/u2/Q" , outpin "u7/u2/Q" YQ , inpin "u7/iRst_out_inv_shift10" CE , inpin "u7/iRst_out_inv_shift12" CE , inpin "u7/iRst_out_inv_shift2" CE , inpin "u7/iRst_out_inv_shift4" CE , inpin "u7/iRst_out_inv_shift6" CE , inpin "u7/iRst_out_inv_shift8" CE , inpin "u7/u6/reg<13>" CE , inpin "u7/u6/reg<14>" CE , inpin "u7/u6/reg_121" CE , inpin "u7/u6/reg_121" SR , ; net "u7/u2/Q_int" , outpin "u7/u2/Q_int" YQ , inpin "u7/u2/Q" BY , ; net "u7/u3/u1/Q" , outpin "u7/u3/u1/Q" YQ , inpin "SPI_A_iCS" O1 , ; net "u7/u3/u1/Q_int" , outpin "u7/u3/u1/Q_int" YQ , inpin "u7/u3/u1/Q" BY , ; net "u7/u4/ff" , outpin "u7/u4/ff" YQ , inpin "u7/u1/count<1>" F2 , ; net "u7/u5/A_addr<0>" , outpin "u7/u5/A_addr<1>" YQ , inpin "u7/u8/Wr_int" F2 , ; net "u7/u5/A_addr<1>" , outpin "u7/u5/A_addr<1>" XQ , inpin "u7/u8/Wr_int" G1 , ; net "u7/u5/A_addr<2>" , outpin "u7/u5/A_addr<2>" YQ , inpin "u7/u8/Wr_int" G2 , ; net "u7/u5/A_addr_not0001" , outpin "u7/u1/count<1>" X , inpin "u7/u5/A_addr<1>" CE , inpin "u7/u5/A_addr<2>" CE , ; net "u7/u6/reg<12>" , outpin "u7/u6/reg<13>" YQ , inpin "u7/u5/A_addr<1>" BY , inpin "u7/u6/reg<13>" BX , ; net "u7/u6/reg<13>" , outpin "u7/u6/reg<13>" XQ , inpin "u7/u5/A_addr<1>" BX , inpin "u7/u6/reg<14>" BY , ; net "u7/u6/reg<14>" , outpin "u7/u6/reg<14>" YQ , inpin "u7/u5/A_addr<2>" BY , ; net "u7/u6/reg_121" , outpin "u7/u6/reg_121" YQ , inpin "u7/u6/reg<13>" G3 , ; net "u7/u7/line" , outpin "u7/u7/line" YQ , inpin "u7/Go_int" G2 , ; net "u7/u7/reg<10>" , outpin "u7/u7/reg<11>" YQ , inpin "u7/u7/reg<11>" F4 , ; net "u7/u7/reg<11>" , outpin "u7/u7/reg<11>" XQ , inpin "u7/u7/line" G4 , ; net "u7/u7/reg<4>" , outpin "u7/u7/reg<4>" XQ , inpin "u7/u7/reg<4>" G2 , ; net "u7/u7/reg<5>" , outpin "u7/u7/reg<4>" YQ , inpin "u7/u7/reg<7>" G1 , ; net "u7/u7/reg<6>" , outpin "u7/u7/reg<7>" YQ , inpin "u7/u7/reg<7>" F4 , ; net "u7/u7/reg<7>" , outpin "u7/u7/reg<7>" XQ , inpin "u7/u7/reg<9>" G2 , ; net "u7/u7/reg<8>" , outpin "u7/u7/reg<9>" YQ , inpin "u7/u7/reg<9>" F2 , ; net "u7/u7/reg<9>" , outpin "u7/u7/reg<9>" XQ , inpin "u7/u7/reg<11>" G2 , ; net "u7/u8/Addr_mem<0>" , outpin "u7/u8/Addr_mem<1>" YQ , inpin "u7/u7/reg<7>" G2 , ; net "u7/u8/Addr_mem<1>" , outpin "u7/u8/Addr_mem<1>" XQ , inpin "u7/u7/reg<7>" F3 , ; net "u7/u8/Addr_mem<2>" , outpin "u7/u8/Addr_mem<2>" YQ , inpin "u7/u7/reg<9>" G1 , ; net "u7/u8/Addr_mem_and0000" , outpin "u7/u9/T_iA_int" X , inpin "u7/u8/Addr_mem<1>" CE , inpin "u7/u8/Addr_mem<2>" CE , ; net "u7/u8/Done_int" , outpin "u7/u8/Done_int" YQ , inpin "u7/u8/u2/Q_int" BY , ; net "u7/u8/Done_int_and0000" , outpin "u7/u8/Done_int_and0000" Y , inpin "u7/u8/Done_int" CE , ; net "u7/u8/Go_next_clk" , outpin "u7/u8/Go_next_clk" YQ , inpin "u7/u8/u1/Q_int" BY , ; net "u7/u8/Wr_int" , outpin "u7/u8/Wr_int" XQ , inpin "u7/u7/reg<11>" F3 , inpin "u7/u8/Done_int" G1 , inpin "u7/u8/Go_next_clk" G2 , inpin "u7/u8/Wr_int_and0000" G3 , ; net "u7/u8/Wr_int_and0000" , outpin "u7/u8/Wr_int_and0000" X , inpin "u7/u8/Wr_int" CE , ; net "u7/u8/Wr_int_mux000363" , outpin "u7/u8/Wr_int_mux000363" X , inpin "u7/u8/Wr_int" F4 , ; net "u7/u8/u1/Q" , outpin "u7/u8/u1/Q" YQ , inpin "u7/Go_int" F1 , inpin "u7/u1/count_not0001" G4 , ; net "u7/u8/u1/Q_int" , outpin "u7/u8/u1/Q_int" YQ , inpin "u7/u8/u1/Q" BY , ; net "u7/u8/u2/Q" , outpin "u7/u8/u2/Q" YQ , inpin "u6/Addr<1>" CLK , inpin "u6/Addr<3>" CLK , inpin "u6/u4/Q_int" BY , ; net "u7/u8/u2/Q_int" , outpin "u7/u8/u2/Q_int" YQ , inpin "u7/u8/u2/Q" BY , ; net "u7/u9/CycNum" , outpin "u7/u9/CycNum" YQ , inpin "u7/u8/Done_int" F3 , inpin "u7/u9/CycNum" BY , ; net "u7/u9/CycNum_not0001" , outpin "u7/u8/Go_next_clk" X , inpin "u7/u9/CycNum" CE , ; net "u7/u9/RstCyc" , outpin "u7/u9/RstCyc" YQ , inpin "u7/Go_int" F2 , inpin "u7/Go_int" G1 , inpin "u7/u1/count_not0001" G2 , inpin "u7/u8/Done_int" F4 , inpin "u7/u8/Done_int_and0000" G1 , inpin "u7/u8/Go_next_clk" CE , inpin "u7/u8/Go_next_clk" F1 , inpin "u7/u8/Wr_int_and0000" BX , inpin "u7/u9/T_iA_int" F4 , inpin "u7/u9/T_iA_int" G4 , ; net "u7/u9/RstCyc_not0001" , outpin "u7/u8/Done_int" X , inpin "u7/u9/RstCyc" CE , ; net "u7/u9/T_iA_int" , outpin "u7/u9/T_iA_int" YQ , inpin "u7/u3/u1/Q_int" SR , inpin "u7/u4/ff" BY , inpin "u7/u7/line" F1 , inpin "u7/u8/Wr_int_mux000363" F1 , ; net "u8/Addr<0>" , outpin "u8/Addr<0>" XQ , inpin "u8/Addr<0>" BX , inpin "u8/Addr<0>" G1 , inpin "u8/Addr<3>" F4 , inpin "u8/Addr<3>" G4 , inpin "u8/Addr<4>" F4 , inpin "u8/Addr<4>" G4 , inpin "u8/Mtridata_DAC_Addr<1>" G1 , ; net "u8/Addr<1>" , outpin "u8/Addr<0>" YQ , inpin "u8/Addr<0>" G2 , inpin "u8/Addr<3>" F3 , inpin "u8/Addr<3>" G3 , inpin "u8/Addr<4>" F3 , inpin "u8/Addr<4>" G3 , inpin "u8/Mtridata_DAC_Addr<1>" F4 , ; net "u8/Addr<2>" , outpin "u8/Addr<3>" YQ , inpin "u8/Addr<3>" F1 , inpin "u8/Addr<3>" G2 , inpin "u8/Addr<4>" F1 , inpin "u8/Addr<4>" G1 , inpin "u8/Mtridata_DAC_Addr<3>" G1 , ; net "u8/Addr<3>" , outpin "u8/Addr<3>" XQ , inpin "u8/Addr<3>" F2 , inpin "u8/Addr<4>" F2 , inpin "u8/Addr<4>" G2 , inpin "u8/Mtridata_DAC_Addr<3>" F2 , ; net "u8/Addr<4>" , outpin "u8/Addr<4>" XQ , inpin "u8/Addr<4>" BX , inpin "u8/Mtridata_DAC_Addr<4>" G3 , ; net "u8/Addr_and0000" , outpin "u8/Addr_and0000" Y , inpin "u8/Addr<0>" CE , inpin "u8/Addr<3>" CE , inpin "u8/Addr<4>" CE , inpin "u8/VoltData<7>" CE , ; net "u8/ByteCount<0>" , outpin "u8/ByteCount<0>" XQ , inpin "u8/Addr_and0000" G1 , inpin "u8/ByteCount<0>" F3 , inpin "u8/Mcompar_En_cmp_ne0000_cy<1>" F3 , inpin "u8/VoltData_10_and0000" F2 , inpin "u8/u3/u1/u1/Q_int" G2 , ; net "u8/ByteCount<10>" , outpin "u8/ByteCount<10>" XQ , inpin "u8/ByteCount<10>" F3 , inpin "u8/Mcompar_En_cmp_ne0000_cy<5>" G4 , ; net "u8/ByteCount<11>" , outpin "u8/ByteCount<10>" YQ , inpin "u8/ByteCount<10>" G2 , inpin "u8/Mcompar_En_cmp_ne0000_cy<5>" G2 , ; net "u8/ByteCount<12>" , outpin "u8/ByteCount<12>" XQ , inpin "u8/ByteCount<12>" F2 , inpin "u8/Mcompar_En_cmp_ne0000_cy<7>" F2 , ; net "u8/ByteCount<13>" , outpin "u8/ByteCount<12>" YQ , inpin "u8/ByteCount<12>" G3 , inpin "u8/Mcompar_En_cmp_ne0000_cy<7>" F4 , ; net "u8/ByteCount<14>" , outpin "u8/ByteCount<14>" XQ , inpin "u8/ByteCount<14>" F4 , inpin "u8/Mcompar_En_cmp_ne0000_cy<7>" G4 , ; net "u8/ByteCount<15>" , outpin "u8/ByteCount<14>" YQ , inpin "u8/ByteCount<14>" G1 , inpin "u8/Mcompar_En_cmp_ne0000_cy<7>" G1 , ; net "u8/ByteCount<1>" , outpin "u8/ByteCount<0>" YQ , inpin "u8/ByteCount<0>" G1 , inpin "u8/Mcompar_En_cmp_ne0000_cy<1>" F1 , ; net "u8/ByteCount<2>" , outpin "u8/ByteCount<2>" XQ , inpin "u8/ByteCount<2>" F2 , inpin "u8/Mcompar_En_cmp_ne0000_cy<1>" G2 , ; net "u8/ByteCount<3>" , outpin "u8/ByteCount<2>" YQ , inpin "u8/ByteCount<2>" G3 , inpin "u8/Mcompar_En_cmp_ne0000_cy<1>" G4 , ; net "u8/ByteCount<4>" , outpin "u8/ByteCount<4>" XQ , inpin "u8/ByteCount<4>" F2 , inpin "u8/Mcompar_En_cmp_ne0000_cy<3>" F4 , ; net "u8/ByteCount<5>" , outpin "u8/ByteCount<4>" YQ , inpin "u8/ByteCount<4>" G1 , inpin "u8/Mcompar_En_cmp_ne0000_cy<3>" F1 , ; net "u8/ByteCount<6>" , outpin "u8/ByteCount<6>" XQ , inpin "u8/ByteCount<6>" F4 , inpin "u8/Mcompar_En_cmp_ne0000_cy<3>" G4 , ; net "u8/ByteCount<7>" , outpin "u8/ByteCount<6>" YQ , inpin "u8/ByteCount<6>" G4 , inpin "u8/Mcompar_En_cmp_ne0000_cy<3>" G2 , ; net "u8/ByteCount<8>" , outpin "u8/ByteCount<8>" XQ , inpin "u8/ByteCount<8>" F4 , inpin "u8/Mcompar_En_cmp_ne0000_cy<5>" F3 , ; net "u8/ByteCount<9>" , outpin "u8/ByteCount<8>" YQ , inpin "u8/ByteCount<8>" G1 , inpin "u8/Mcompar_En_cmp_ne0000_cy<5>" F1 , ; net "u8/ByteCount_or0000" , outpin "u8/ByteCount_or0000" Y , inpin "u8/ByteCount<0>" SR , inpin "u8/ByteCount<10>" SR , inpin "u8/ByteCount<12>" SR , inpin "u8/ByteCount<14>" SR , inpin "u8/ByteCount<2>" SR , inpin "u8/ByteCount<4>" SR , inpin "u8/ByteCount<6>" SR , inpin "u8/ByteCount<8>" SR , ; net "u8/Data<0>" , outpin "u8/lenregL/Data<0>" Y , inpin "u8/VoltData<7>" BY , inpin "u8/VoltData<9>" BY , inpin "u8/lenregH/Data<0>" BY , ; net "u8/Done_PacketSkip" , outpin "u8/u2/Q_int" X , inpin "r1/state<0>" F1 , inpin "r1/state<2>" G3 , inpin "u8/u5/Working" CE , ; net "u8/En" , outpin "u8/u2/Q_int" Y , inpin "u8/Mtridata_DAC_Addr<1>" F3 , inpin "u8/Mtridata_DAC_Addr<1>" G3 , inpin "u8/Mtridata_DAC_Addr<3>" F3 , inpin "u8/Mtridata_DAC_Addr<3>" G3 , inpin "u8/Mtridata_DAC_Addr<4>" G2 , inpin "u8/Mtridata_DAC_D<10>" F1 , inpin "u8/Mtridata_DAC_D<10>" G3 , inpin "u8/Mtrien_DAC_Addr" F2 , inpin "u8/Mtrien_DAC_Addr" G2 , inpin "u8/u1/Qa" BY , inpin "u8/u2/Q_int" F3 , inpin "u8/u3/u1/u1/Q_int" F4 , ; net "u8/Go_PacketSkip" , outpin "u8/Mtrien_DAC_Addr" X , inpin "u8/u5/Working" BY , ; net "u8/MaskStage" , outpin "u8/MaskStage" XQ , inpin "u8/Addr_and0000" G2 , inpin "u8/VoltData_10_and0000" F3 , inpin "u8/intMaskByteNum<0>" CE , inpin "u8/intMaskByteNum<0>" F1 , inpin "u8/lenregL/Data<0>" F2 , inpin "u8/u3/u1/u1/Q_int" G1 , ; net "u8/MaskStage_and0000" , outpin "u8/lenregL/Data<0>" X , inpin "u8/MaskStage" BY , ; net "u8/MaskStage_and0001" , outpin "u8/intMaskByteNum<0>" X , inpin "u8/MaskStage" CE , ; net "u8/Mcompar_En_cmp_ne0000_cy<1>" , outpin "u8/Mcompar_En_cmp_ne0000_cy<1>" COUT , inpin "u8/Mcompar_En_cmp_ne0000_cy<3>" CIN , ; net "u8/Mcompar_En_cmp_ne0000_cy<3>" , outpin "u8/Mcompar_En_cmp_ne0000_cy<3>" COUT , inpin "u8/Mcompar_En_cmp_ne0000_cy<5>" CIN , ; net "u8/Mcompar_En_cmp_ne0000_cy<5>" , outpin "u8/Mcompar_En_cmp_ne0000_cy<5>" COUT , inpin "u8/Mcompar_En_cmp_ne0000_cy<7>" CIN , ; net "u8/Mcompar_En_cmp_ne0000_cy<7>" , outpin "u8/Mcompar_En_cmp_ne0000_cy<7>" COUT , inpin "u8/Addr_and0000" G3 , inpin "u8/VoltData_10_and0000" F4 , inpin "u8/u2/Q_int" G4 , ; net "u8/Mcount_ByteCount_cy<11>" , outpin "u8/ByteCount<10>" COUT , inpin "u8/ByteCount<12>" CIN , ; net "u8/Mcount_ByteCount_cy<13>" , outpin "u8/ByteCount<12>" COUT , inpin "u8/ByteCount<14>" CIN , ; net "u8/Mcount_ByteCount_cy<1>" , outpin "u8/ByteCount<0>" COUT , inpin "u8/ByteCount<2>" CIN , ; net "u8/Mcount_ByteCount_cy<3>" , outpin "u8/ByteCount<2>" COUT , inpin "u8/ByteCount<4>" CIN , ; net "u8/Mcount_ByteCount_cy<5>" , outpin "u8/ByteCount<4>" COUT , inpin "u8/ByteCount<6>" CIN , ; net "u8/Mcount_ByteCount_cy<7>" , outpin "u8/ByteCount<6>" COUT , inpin "u8/ByteCount<8>" CIN , ; net "u8/Mcount_ByteCount_cy<9>" , outpin "u8/ByteCount<8>" COUT , inpin "u8/ByteCount<10>" CIN , ; net "u8/Mtridata_DAC_Addr<0>" , outpin "u8/Mtridata_DAC_Addr<1>" YQ , inpin "u9/u2/SReg_14_and0000" F2 , inpin "u9/u2/SReg_14_and0000" G4 , ; net "u8/Mtridata_DAC_Addr<1>" , outpin "u8/Mtridata_DAC_Addr<1>" XQ , inpin "u9/u2/SReg_15_or0000" F4 , inpin "u9/u2/SReg_15_or0000" G4 , ; net "u8/Mtridata_DAC_Addr<2>" , outpin "u8/Mtridata_DAC_Addr<3>" YQ , inpin "u9/u2/SReg_16_and0000" F3 , inpin "u9/u2/SReg_16_and0000" G3 , ; net "u8/Mtridata_DAC_Addr<3>" , outpin "u8/Mtridata_DAC_Addr<3>" XQ , inpin "u9/u2/SReg_17_and0000" F3 , inpin "u9/u2/SReg_17_and0000" G3 , ; net "u8/Mtridata_DAC_Addr<4>" , outpin "u8/Mtridata_DAC_Addr<4>" YQ , inpin "u9/u2/SReg_18_and0000" F3 , inpin "u9/u2/SReg_18_and0000" G3 , ; net "u8/Mtridata_DAC_D<0>" , outpin "u8/Mtridata_DAC_D<10>" YQ , inpin "u9/u2/SReg_0_or0000" F3 , inpin "u9/u2/SReg_0_or0000" G3 , ; net "u8/Mtridata_DAC_D<10>" , outpin "u8/Mtridata_DAC_D<10>" XQ , inpin "u9/u2/SReg_10_or0000" F3 , inpin "u9/u2/SReg_10_or0000" G3 , ; net "u8/Mtrien_DAC_Addr" , outpin "u8/Mtrien_DAC_Addr" YQ , inpin "u9/u2/SReg_14_and0000" F4 , inpin "u9/u2/SReg_14_and0000" G3 , inpin "u9/u2/SReg_15_or0000" F2 , inpin "u9/u2/SReg_15_or0000" G2 , inpin "u9/u2/SReg_16_and0000" F1 , inpin "u9/u2/SReg_16_and0000" G1 , inpin "u9/u2/SReg_17_and0000" F1 , inpin "u9/u2/SReg_17_and0000" G1 , inpin "u9/u2/SReg_18_and0000" F1 , inpin "u9/u2/SReg_18_and0000" G1 , ; net "u8/Mtrien_DAC_Addr_mux0000" , outpin "u8/Mtrien_DAC_Addr" Y , inpin "u8/Mtrien_DAC_D" BY , ; net "u8/Mtrien_DAC_D" , outpin "u8/Mtrien_DAC_D" YQ , inpin "u9/u2/SReg_0_or0000" F4 , inpin "u9/u2/SReg_0_or0000" G4 , inpin "u9/u2/SReg_10_or0000" F4 , inpin "u9/u2/SReg_10_or0000" G4 , ; net "u8/VoltData<7>" , outpin "u8/VoltData<7>" YQ , inpin "u8/Mtridata_DAC_D<10>" G4 , ; net "u8/VoltData<9>" , outpin "u8/VoltData<9>" YQ , inpin "u8/Mtridata_DAC_D<10>" F3 , ; net "u8/VoltData_10_and0000" , outpin "u8/VoltData_10_and0000" X , inpin "u8/VoltData<9>" CE , ; net "u8/intMaskByteNum<0>" , outpin "u8/intMaskByteNum<0>" XQ , inpin "u8/intMaskByteNum<0>" BX , inpin "u8/intMaskByteNum<0>" F4 , inpin "u8/intMaskByteNum<0>" G4 , ; net "u8/intMaskByteNum<1>" , outpin "u8/intMaskByteNum<0>" YQ , inpin "u8/intMaskByteNum<0>" F3 , inpin "u8/intMaskByteNum<0>" G3 , ; net "u8/l1/En" , outpin "u8/l1/En" XQ , inpin "u8/l2/u1/Q_int" BY , inpin "u8/lenregH/Data<0>" CE , inpin "u8/lenregL/Data<0>" G3 , ; net "u8/l1/En_and0000" , outpin "u1/m6/b2/En_and0000" Y , inpin "u8/l1/En" BY , ; net "u8/l1/u1/Q" , outpin "u8/l1/u1/Q" YQ , inpin "u1/m6/b2/En_and0000" G2 , ; net "u8/l1/u1/Q_int" , outpin "u8/l1/u1/Q_int" YQ , inpin "u8/l1/u1/Q" BY , ; net "u8/l2/En" , outpin "u8/l2/En" XQ , inpin "u8/intMaskByteNum<0>" F2 , inpin "u8/lenregL/Data<0>" CE , inpin "u8/lenregL/Data<0>" F4 , inpin "u8/lenregL/Data<0>" G4 , inpin "u8/u3/u1/u1/Q_int" F1 , ; net "u8/l2/En_and0000" , outpin "u1/p7/u2/En_and0000" Y , inpin "u8/l2/En" BY , ; net "u8/l2/u1/Q" , outpin "u8/l2/u1/Q" YQ , inpin "u1/p7/u2/En_and0000" G1 , ; net "u8/l2/u1/Q_int" , outpin "u8/l2/u1/Q_int" YQ , inpin "u8/l2/u1/Q" BY , ; net "u8/lenregH/Data<0>" , outpin "u8/lenregH/Data<0>" YQ , inpin "u8/Mcompar_En_cmp_ne0000_cy<5>" F2 , inpin "u8/Mcompar_En_cmp_ne0000_cy<5>" G3 , inpin "u8/Mcompar_En_cmp_ne0000_cy<7>" F3 , inpin "u8/Mcompar_En_cmp_ne0000_cy<7>" G2 , ; net "u8/lenregL/Data<0>" , outpin "u8/lenregL/Data<0>" YQ , inpin "u8/Mcompar_En_cmp_ne0000_cy<1>" F2 , inpin "u8/Mcompar_En_cmp_ne0000_cy<1>" G1 , inpin "u8/Mcompar_En_cmp_ne0000_cy<3>" F2 , inpin "u8/Mcompar_En_cmp_ne0000_cy<3>" G1 , ; net "u8/u1/Qa" , outpin "u8/u1/Qa" YQ , inpin "u8/u1/Qb" BY , ; net "u8/u1/Qb" , outpin "u8/u1/Qb" YQ , inpin "u8/u2/Q_int" SR , ; net "u8/u2/Q" , outpin "u8/u2/Q" YQ , inpin "u8/ByteCount_or0000" G1 , inpin "u8/l1/u1/Q_int" BY , ; net "u8/u2/Q_int" , outpin "u8/u2/Q_int" YQ , inpin "u8/u2/Q" BY , ; net "u8/u3/u1/En" , outpin "u8/u3/u1/En_BUFG" O , inpin "u8/Addr<0>" CLK , inpin "u8/Addr<3>" CLK , inpin "u8/Addr<4>" CLK , inpin "u8/ByteCount<0>" CLK , inpin "u8/ByteCount<10>" CLK , inpin "u8/ByteCount<12>" CLK , inpin "u8/ByteCount<14>" CLK , inpin "u8/ByteCount<2>" CLK , inpin "u8/ByteCount<4>" CLK , inpin "u8/ByteCount<6>" CLK , inpin "u8/ByteCount<8>" CLK , inpin "u8/MaskStage" CLK , inpin "u8/VoltData<7>" CLK , inpin "u8/VoltData<9>" CLK , inpin "u8/intMaskByteNum<0>" CLK , ; net "u8/u3/u1/En1" , outpin "u8/u3/u1/En1" XQ , inpin "u8/lenregL/Data<0>" G2 , inpin "u8/u3/u1/En_BUFG" I0 , inpin "u8/u3/u1/u1/Q_int" G3 , ; net "u8/u3/u1/En_and0000" , outpin "u8/u3/u1/En_and0000" X , inpin "u8/u3/u1/En1" BY , ; net "u8/u3/u1/u1/Q" , outpin "u8/u3/u1/u1/Q" YQ , inpin "u8/u3/u1/En_and0000" F2 , ; net "u8/u3/u1/u1/Q_int" , outpin "u8/u3/u1/u1/Q_int" XQ , inpin "u8/u3/u1/u1/Q" BY , ; net "u8/u5/Working" , outpin "u8/u5/Working" XQ , inpin "u8/u2/Q_int" F4 , ; net "u9/shift" , outpin "u9/shift" X , inpin "u9/u2/LineOut_not0001_inv" G1 , inpin "u9/u2/SReg_0_or0000" F2 , inpin "u9/u2/SReg_0_or0000" G2 , inpin "u9/u2/SReg_10_or0000" F2 , inpin "u9/u2/SReg_10_or0000" G2 , inpin "u9/u2/SReg_14_and0000" F1 , inpin "u9/u2/SReg_14_and0000" G2 , inpin "u9/u2/SReg_15_or0000" F1 , inpin "u9/u2/SReg_15_or0000" G1 , inpin "u9/u2/SReg_16_and0000" F2 , inpin "u9/u2/SReg_16_and0000" G2 , inpin "u9/u2/SReg_17_and0000" F2 , inpin "u9/u2/SReg_17_and0000" G2 , inpin "u9/u2/SReg_18_and0000" F4 , inpin "u9/u2/SReg_18_and0000" G2 , inpin "u9/u4/Qa" SR , inpin "u9/u5/Q_int" SR , ; net "u9/u1/N3" , outpin "u9/u1/count<2>" Y , inpin "u9/u1/count<2>" F4 , inpin "u9/u1/count<4>" F1 , ; net "u9/u1/count<0>" , outpin "u9/u1/count<0>" XQ , inpin "u9/shift" G3 , inpin "u9/u1/count<0>" BX , inpin "u9/u1/count<0>" G2 , inpin "u9/u1/count<2>" G2 , inpin "u9/u1/count<4>" G3 , ; net "u9/u1/count<1>" , outpin "u9/u1/count<0>" YQ , inpin "u9/shift" G4 , inpin "u9/u1/count<0>" G4 , inpin "u9/u1/count<2>" G1 , inpin "u9/u1/count<4>" G4 , ; net "u9/u1/count<2>" , outpin "u9/u1/count<2>" XQ , inpin "u9/shift" G2 , inpin "u9/u1/count<2>" F3 , inpin "u9/u1/count<4>" F2 , inpin "u9/u1/count<4>" G2 , ; net "u9/u1/count<3>" , outpin "u9/u1/count<4>" YQ , inpin "u9/shift" G1 , inpin "u9/u1/count<2>" F2 , inpin "u9/u1/count<4>" F3 , inpin "u9/u1/count<4>" G1 , ; net "u9/u1/count<4>" , outpin "u9/u1/count<4>" XQ , inpin "u9/shift" BX , inpin "u9/u1/count<2>" F1 , inpin "u9/u1/count<4>" F4 , ; net "u9/u2/LineOut" , outpin "u9/u2/LineOut" YQ , inpin "DAC_serData" O1 , ; net "u9/u2/LineOut_not0001_inv" , outpin "u9/u2/LineOut_not0001_inv" Y , inpin "u9/u2/LineOut" SR , ; net "u9/u2/SReg<0>" , outpin "u9/u2/SReg<1>" YQ , inpin "u9/u2/SReg<1>" BX , ; net "u9/u2/SReg<10>" , outpin "u9/u2/SReg<11>" YQ , inpin "u9/u2/SReg<11>" BX , ; net "u9/u2/SReg<11>" , outpin "u9/u2/SReg<11>" XQ , inpin "u9/u2/SReg<13>" G1 , ; net "u9/u2/SReg<12>" , outpin "u9/u2/SReg<13>" YQ , inpin "u9/u2/SReg<13>" BX , ; net "u9/u2/SReg<13>" , outpin "u9/u2/SReg<13>" XQ , inpin "u9/u2/SReg<14>" BX , ; net "u9/u2/SReg<14>" , outpin "u9/u2/SReg<14>" XQ , inpin "u9/u2/SReg<15>" BX , ; net "u9/u2/SReg<15>" , outpin "u9/u2/SReg<15>" XQ , inpin "u9/u2/SReg<16>" BX , ; net "u9/u2/SReg<16>" , outpin "u9/u2/SReg<16>" XQ , inpin "u9/u2/SReg<17>" BX , ; net "u9/u2/SReg<17>" , outpin "u9/u2/SReg<17>" XQ , inpin "u9/u2/SReg<18>" BX , ; net "u9/u2/SReg<18>" , outpin "u9/u2/SReg<18>" XQ , inpin "u9/u2/LineOut" BY , ; net "u9/u2/SReg<1>" , outpin "u9/u2/SReg<1>" XQ , inpin "u9/u2/SReg<3>" G2 , ; net "u9/u2/SReg<2>" , outpin "u9/u2/SReg<3>" YQ , inpin "u9/u2/SReg<3>" BX , ; net "u9/u2/SReg<3>" , outpin "u9/u2/SReg<3>" XQ , inpin "u9/u2/SReg<5>" G2 , ; net "u9/u2/SReg<4>" , outpin "u9/u2/SReg<5>" YQ , inpin "u9/u2/SReg<5>" BX , ; net "u9/u2/SReg<5>" , outpin "u9/u2/SReg<5>" XQ , inpin "u9/u2/SReg<7>" G3 , ; net "u9/u2/SReg<6>" , outpin "u9/u2/SReg<7>" YQ , inpin "u9/u2/SReg<7>" BX , ; net "u9/u2/SReg<7>" , outpin "u9/u2/SReg<7>" XQ , inpin "u9/u2/SReg<9>" G2 , ; net "u9/u2/SReg<8>" , outpin "u9/u2/SReg<9>" YQ , inpin "u9/u2/SReg<9>" BX , ; net "u9/u2/SReg<9>" , outpin "u9/u2/SReg<9>" XQ , inpin "u9/u2/SReg<11>" G2 , ; net "u9/u2/SReg_0_and0000" , outpin "u9/u2/SReg_0_or0000" Y , inpin "u9/u2/SReg<1>" BY , inpin "u9/u2/SReg<3>" BY , inpin "u9/u2/SReg<5>" BY , inpin "u9/u2/SReg<7>" BY , ; net "u9/u2/SReg_0_or0000" , outpin "u9/u2/SReg_0_or0000" X , inpin "u9/u2/SReg<1>" SR , inpin "u9/u2/SReg<3>" SR , inpin "u9/u2/SReg<5>" SR , inpin "u9/u2/SReg<7>" SR , ; net "u9/u2/SReg_10_and0000" , outpin "u9/u2/SReg_10_or0000" Y , inpin "u9/u2/SReg<11>" BY , inpin "u9/u2/SReg<13>" BY , inpin "u9/u2/SReg<9>" BY , ; net "u9/u2/SReg_10_or0000" , outpin "u9/u2/SReg_10_or0000" X , inpin "u9/u2/SReg<11>" SR , inpin "u9/u2/SReg<13>" SR , inpin "u9/u2/SReg<9>" SR , ; net "u9/u2/SReg_14_and0000" , outpin "u9/u2/SReg_14_and0000" X , inpin "u9/u2/SReg<14>" BY , ; net "u9/u2/SReg_14_or0000" , outpin "u9/u2/SReg_14_and0000" Y , inpin "u9/u2/SReg<14>" SR , ; net "u9/u2/SReg_15_and0000" , outpin "u9/u2/SReg_15_or0000" Y , inpin "u9/u2/SReg<15>" BY , ; net "u9/u2/SReg_15_or0000" , outpin "u9/u2/SReg_15_or0000" X , inpin "u9/u2/SReg<15>" SR , ; net "u9/u2/SReg_16_and0000" , outpin "u9/u2/SReg_16_and0000" X , inpin "u9/u2/SReg<16>" BY , ; net "u9/u2/SReg_16_or0000" , outpin "u9/u2/SReg_16_and0000" Y , inpin "u9/u2/SReg<16>" SR , ; net "u9/u2/SReg_17_and0000" , outpin "u9/u2/SReg_17_and0000" X , inpin "u9/u2/SReg<17>" BY , ; net "u9/u2/SReg_17_or0000" , outpin "u9/u2/SReg_17_and0000" Y , inpin "u9/u2/SReg<17>" SR , ; net "u9/u2/SReg_18_and0000" , outpin "u9/u2/SReg_18_and0000" X , inpin "u9/u2/SReg<18>" BY , ; net "u9/u2/SReg_18_or0000" , outpin "u9/u2/SReg_18_and0000" Y , inpin "u9/u2/SReg<18>" SR , ; net "u9/u4/Qa" , outpin "u9/u4/Qa" YQ , inpin "u9/u4/Qb" BY , ; net "u9/u4/Qb" , outpin "u9/u4/Qb" YQ , inpin "u9/u5/Q_int" BY , ; net "u9/u5/Q" , outpin "u9/u5/Q" YQ , inpin "u8/Mtrien_DAC_Addr" F3 , inpin "u8/u2/Q_int" F2 , inpin "u8/u3/u1/u1/Q_int" F2 , ; net "u9/u5/Q_int" , outpin "u9/u5/Q_int" YQ , inpin "u9/u5/Q" BY , ; # ======================================================= # SUMMARY # Number of Module Defs: 0 # Number of Module Insts: 0 # Number of Primitive Insts: 362 # Number of Nets: 551 # =======================================================