-------------------------------------------------------------------------------- Release 11.3 Trace (nt) Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved. E:\Xilinx\11.1\ISE\bin\nt\unwrapped\trce.exe -ise E:/igors work/GlueX/Tagger/Electronics/FPGA/TotalTest/TotalTest.ise -intstyle ise -v 3 -s 4 -xml FPGA_ctrl.twx FPGA_ctrl.ncd -o FPGA_ctrl.twr FPGA_ctrl.pcf -ucf FPGA_ctrl.ucf Design file: FPGA_ctrl.ncd Physical constraint file: FPGA_ctrl.pcf Device,package,speed: xc3s50a,vq100,-4 (PRODUCTION 1.41 2009-08-24) Report level: verbose report Environment Variable Effect -------------------- ------ NONE No environment variables were set -------------------------------------------------------------------------------- INFO:Timing:2698 - No timing constraints found, doing default enumeration. INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths option. All paths that are not constrained will be reported in the unconstrained paths section(s) of the report. INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on a 50 Ohm transmission line loading model. For the details of this model, and for more information on accounting for different loading conditions, please see the device datasheet. Data Sheet report: ----------------- All values displayed in nanoseconds (ns) Setup/Hold to clock fClk ------------+------------+------------+------------------+--------+ |Max Setup to|Max Hold to | | Clock | Source | clk (edge) | clk (edge) |Internal Clock(s) | Phase | ------------+------------+------------+------------------+--------+ AD<0> | 1.930(R)| 0.359(R)|fClk_out_OBUF | 0.000| AD<1> | 1.923(R)| 0.367(R)|fClk_out_OBUF | 0.000| AD<2> | 1.923(R)| 0.367(R)|fClk_out_OBUF | 0.000| AD<3> | 1.914(R)| 0.378(R)|fClk_out_OBUF | 0.000| AD<4> | 1.914(R)| 0.378(R)|fClk_out_OBUF | 0.000| AD<5> | 1.911(R)| 0.381(R)|fClk_out_OBUF | 0.000| AD<6> | 1.901(R)| 0.393(R)|fClk_out_OBUF | 0.000| AD<7> | 1.906(R)| 0.387(R)|fClk_out_OBUF | 0.000| Eth_iINT | 1.713(F)| 1.086(F)|DAC_Clk_OBUF | 0.000| LocStamp<0> | 8.557(F)| -2.097(F)|DAC_Clk_OBUF | 0.000| LocStamp<1> | 8.242(F)| -2.456(F)|DAC_Clk_OBUF | 0.000| LocStamp<2> | 8.055(F)| -2.600(F)|DAC_Clk_OBUF | 0.000| LocStamp<3> | 8.226(F)| -2.377(F)|DAC_Clk_OBUF | 0.000| LocStamp<4> | 8.509(F)| 0.189(F)|DAC_Clk_OBUF | 0.000| SPI_SDO | 3.119(R)| 0.438(R)|DAC_Clk_OBUF | 0.000| | 1.304(F)| 1.112(F)|DAC_Clk_OBUF | 0.000| ------------+------------+------------+------------------+--------+ Clock Rst to Pad ------------+------------+------------------+--------+ | clk (edge) | | Clock | Destination | to PAD |Internal Clock(s) | Phase | ------------+------------+------------------+--------+ iRD | 14.541(R)|Rst_int | 0.000| iWR | 14.837(R)|Rst_int | 0.000| ------------+------------+------------------+--------+ Clock fClk to Pad -------------+------------+------------------+--------+ | clk (edge) | | Clock | Destination | to PAD |Internal Clock(s) | Phase | -------------+------------+------------------+--------+ AD<0> | 16.101(R)|fClk_out_OBUF | 0.000| | 14.311(F)|fClk_out_OBUF | 0.000| AD<1> | 15.730(R)|fClk_out_OBUF | 0.000| | 13.940(F)|fClk_out_OBUF | 0.000| AD<2> | 16.068(R)|fClk_out_OBUF | 0.000| | 14.821(F)|fClk_out_OBUF | 0.000| AD<3> | 16.266(R)|fClk_out_OBUF | 0.000| | 14.476(F)|fClk_out_OBUF | 0.000| AD<4> | 16.270(R)|fClk_out_OBUF | 0.000| | 14.480(F)|fClk_out_OBUF | 0.000| AD<5> | 16.824(R)|fClk_out_OBUF | 0.000| | 15.034(F)|fClk_out_OBUF | 0.000| AD<6> | 17.095(R)|fClk_out_OBUF | 0.000| | 15.305(F)|fClk_out_OBUF | 0.000| AD<7> | 15.319(R)|fClk_out_OBUF | 0.000| | 14.416(F)|fClk_out_OBUF | 0.000| ALE | 11.339(F)|fClk_out_OBUF | 0.000| DAC_iRst | 12.984(R)|DAC_Clk_OBUF | 0.000| | 14.830(R)|fClk_out_OBUF | 0.000| DAC_serData | 7.648(R)|DAC_Clk_OBUF | 0.000| DAC_serISync | 7.705(R)|DAC_Clk_OBUF | 0.000| Eth_iRst | 12.291(R)|DAC_Clk_OBUF | 0.000| SPI_A_iCS | 14.090(R)|DAC_Clk_OBUF | 0.000| | 11.815(F)|DAC_Clk_OBUF | 0.000| SPI_SDI | 14.325(R)|DAC_Clk_OBUF | 0.000| | 12.599(F)|DAC_Clk_OBUF | 0.000| | 13.719(R)|fClk_out_OBUF | 0.000| SPI_T_CE | 9.776(F)|DAC_Clk_OBUF | 0.000| dbInfoStart | 11.578(R)|DAC_Clk_OBUF | 0.000| dbInfoStream1| 12.005(R)|DAC_Clk_OBUF | 0.000| | 15.329(F)|DAC_Clk_OBUF | 0.000| dbInfoStream2| 7.877(R)|DAC_Clk_OBUF | 0.000| iRD | 11.689(F)|fClk_out_OBUF | 0.000| iWR | 11.873(F)|fClk_out_OBUF | 0.000| state_Qout<0>| 9.616(R)|DAC_Clk_OBUF | 0.000| state_Qout<1>| 11.910(R)|DAC_Clk_OBUF | 0.000| state_Qout<2>| 10.919(R)|DAC_Clk_OBUF | 0.000| -------------+------------+------------------+--------+ Clock to Setup on destination clock Rst ---------------+---------+---------+---------+---------+ | Src:Rise| Src:Fall| Src:Rise| Src:Fall| Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall| ---------------+---------+---------+---------+---------+ fClk | 0.555| 2.905| | | ---------------+---------+---------+---------+---------+ Clock to Setup on destination clock fClk ---------------+---------+---------+---------+---------+ | Src:Rise| Src:Fall| Src:Rise| Src:Fall| Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall| ---------------+---------+---------+---------+---------+ Rst | 8.479| 8.479| 10.762| 10.762| fClk | 13.848| 13.401| 14.272| 16.316| ---------------+---------+---------+---------+---------+ Pad to Pad ---------------+---------------+---------+ Source Pad |Destination Pad| Delay | ---------------+---------------+---------+ Rst |AD<0> | 13.312| Rst |AD<1> | 12.941| Rst |AD<2> | 13.279| Rst |AD<3> | 13.477| Rst |AD<4> | 13.481| Rst |AD<5> | 14.035| Rst |AD<6> | 14.306| Rst |AD<7> | 12.530| Rst |DAC_iRst | 12.040| Rst |SPI_SDI | 10.939| fClk |DAC_Clk | 7.522| fClk |SPI_SCLK | 7.521| fClk |fClk_out | 6.779| ---------------+---------------+---------+ Analysis completed Fri Nov 01 12:06:23 2013 -------------------------------------------------------------------------------- Trace Settings: ------------------------- Trace Settings Peak Memory Usage: 106 MB