Release 11.3 par L.57 (nt) Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved. FIBER-STATION:: Fri Nov 01 12:06:07 2013 par -ise TotalTest.ise -w -intstyle ise -ol std -t 1 -smartguide FPGA_ctrl_guide.ncd FPGA_ctrl_map.ncd FPGA_ctrl.ncd FPGA_ctrl.pcf Constraints file: FPGA_ctrl.pcf. "FPGA_ctrl" is an NCD, version 3.2, device xc3s50a, package vq100, speed -4 Loading database for application par from file: "FPGA_ctrl_guide.ncd" "FPGA_ctrl" is an NCD, version 3.2, device xc3s50a, package vq100, speed -4 INFO:Par:465 - The PAR option, "-t" (Starting Placer Cost Table), will be disabled in the next software release when used in combination with MAP -timing(Perform Timing-Driven Packing and Placement) or when run with V5 or newer architectures. To explore cost tables, please use the MAP option, "-t" (Starting Placer Cost Table), instead. Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000 Celsius) Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.260 Volts) INFO:Par:282 - No user timing constraints were detected or you have set the option to ignore timing constraints ("par -x"). Place and Route will run in "Performance Evaluation Mode" to automatically improve the performance of all internal clocks in this design. Because there are not defined timing requirements, a timing score will not be reported in the PAR report in this mode. The PAR timing summary will list the performance achieved for each clock. Note: For the fastest runtime, set the effort level to "std". For best performance, set the effort level to "high". Device speed data version: "PRODUCTION 1.41 2009-08-24". INFO:Par:402 - SmartGuide was run during Map. Since all guiding (mapping, packing, placement and routing) is completed in MAP, PAR does not require the use of the guide switches. The -smartguide switch only generates a post place and route guide report in the SmartGuide Report File(.GRF). Runtime can be reduced, if this detailed report is not generated. PAR will automatically generate the SmartGuide summary report based on the guide file used during MAP. This summary information is always in the PAR report file and the GRF. Design Summary Report: Number of External IOBs 38 out of 68 55% Number of External Input IOBs 9 Number of External Input IBUFs 9 Number of LOCed External Input IBUFs 9 out of 9 100% Number of External Output IOBs 20 Number of External Output IOBs 20 Number of LOCed External Output IOBs 20 out of 20 100% Number of External Bidir IOBs 9 Number of External Bidir IOBs 9 Number of LOCed External Bidir IOBs 9 out of 9 100% Number of BUFGMUXs 2 out of 24 8% Number of DCMs 1 out of 2 50% Number of Slices 689 out of 704 97% Number of SLICEMs 64 out of 352 18% Number of STARTUPs 1 out of 1 100% Overall effort level (-ol): Standard Router effort level (-rl): Standard Starting initial Timing Analysis. REAL time: 3 secs Finished initial Timing Analysis. REAL time: 3 secs Starting Router Phase 1 : 748 unrouted; REAL time: 4 secs Phase 2 : 671 unrouted; REAL time: 4 secs Phase 3 : 157 unrouted; REAL time: 5 secs Phase 4 : 209 unrouted; (Par is working to improve performance) REAL time: 5 secs Phase 5 : 0 unrouted; (Par is working to improve performance) REAL time: 5 secs Updating file: FPGA_ctrl.ncd with current fully routed design. Phase 6 : 0 unrouted; (Par is working to improve performance) REAL time: 6 secs Phase 7 : 0 unrouted; (Par is working to improve performance) REAL time: 6 secs Phase 8 : 0 unrouted; (Par is working to improve performance) REAL time: 8 secs Phase 9 : 0 unrouted; (Par is working to improve performance) REAL time: 8 secs Phase 10 : 0 unrouted; (Par is working to improve performance) REAL time: 8 secs Phase 11 : 0 unrouted; (Par is working to improve performance) REAL time: 8 secs WARNING:Route:455 - CLK Net:uResS/Done_Byte may have excessive skew because 2 CLK pins and 0 NON_CLK pins failed to route using a CLK template. WARNING:Route:455 - CLK Net:uXmit/uSpack/Done_Word may have excessive skew because 2 CLK pins and 0 NON_CLK pins failed to route using a CLK template. WARNING:Route:455 - CLK Net:db0/u0/serClk may have excessive skew because 0 CLK pins and 1 NON_CLK pins failed to route using a CLK template. WARNING:Route:455 - CLK Net:db0/u2/Q may have excessive skew because 1 CLK pins and 11 NON_CLK pins failed to route using a CLK template. WARNING:Route:455 - CLK Net:uXmit/uDpack/Done_Word may have excessive skew because 1 CLK pins and 1 NON_CLK pins failed to route using a CLK template. WARNING:Route:455 - CLK Net:uXmit/uTxMAC/u1/Q may have excessive skew because 0 CLK pins and 3 NON_CLK pins failed to route using a CLK template. WARNING:Route:455 - CLK Net:ser_Go_uINT may have excessive skew because 1 CLK pins and 11 NON_CLK pins failed to route using a CLK template. WARNING:Route:455 - CLK Net:Rst_int may have excessive skew because 0 CLK pins and 77 NON_CLK pins failed to route using a CLK template. WARNING:Route:455 - CLK Net:uXmit/uDpack/u1/Q may have excessive skew because 0 CLK pins and 11 NON_CLK pins failed to route using a CLK template. WARNING:Route:455 - CLK Net:uXmit/uDpack/w/C_0_0_not0000 may have excessive skew because 0 CLK pins and 7 NON_CLK pins failed to route using a CLK template. WARNING:Route:455 - CLK Net:uQuer/u3/u1/Q may have excessive skew because 3 CLK pins and 18 NON_CLK pins failed to route using a CLK template. WARNING:Route:455 - CLK Net:uINT/u4/u2/Q may have excessive skew because 1 CLK pins and 12 NON_CLK pins failed to route using a CLK template. Total REAL time to Router completion: 8 secs Total CPU time to Router completion: 8 secs SmartGuide Results ------------------ This section describes the guide results after invoking the Router. This report accurately reflects the differences between the input design and the guide design. Number of Components in the input design | 731 Number of guided Components | 731 out of 731 100.0% Number of re-implemented Components | 0 out of 731 0.0% Number of new/changed Components | 0 out of 731 0.0% Number of Nets in the input design | 1689 Number of guided Nets | 1619 out of 1689 95.9% Number of partially guided Nets | 50 out of 1689 3.0% Number of re-routed Nets | 20 out of 1689 1.2% Number of new/changed Nets | 0 out of 1689 0.0% Partition Implementation Status ------------------------------- No Partitions were found in this design. ------------------------------- Generating "PAR" statistics. ************************** Generating Clock Report ************************** +---------------------+--------------+------+------+------------+-------------+ | Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)| +---------------------+--------------+------+------+------------+-------------+ | DAC_Clk_OBUF | BUFGMUX_X2Y11| No | 588 | 0.566 | 1.037 | +---------------------+--------------+------+------+------------+-------------+ | fClk_out_OBUF | BUFGMUX_X1Y1| No | 31 | 0.066 | 0.541 | +---------------------+--------------+------+------+------------+-------------+ | Rst_int | Local| | 278 | 0.000 | 3.857 | +---------------------+--------------+------+------+------------+-------------+ | uINT/u4/u2/Q | Local| | 16 | 1.221 | 2.748 | +---------------------+--------------+------+------+------------+-------------+ | uXmit/uTxMAC/u1/Q | Local| | 6 | 0.094 | 1.831 | +---------------------+--------------+------+------+------------+-------------+ | db0/u0/serClk | Local| | 4 | 0.058 | 1.913 | +---------------------+--------------+------+------+------------+-------------+ | uQuer/u3/u1/Q | Local| | 21 | 0.005 | 1.534 | +---------------------+--------------+------+------+------------+-------------+ |uXmit/uDpack/w/C_0_0 | | | | | | | _not0000 | Local| | 11 | 0.043 | 1.721 | +---------------------+--------------+------+------+------------+-------------+ | uXmit/uDpack/u1/Q | Local| | 15 | 0.247 | 2.204 | +---------------------+--------------+------+------+------------+-------------+ | ser_Go_uINT | Local| | 12 | 0.000 | 0.743 | +---------------------+--------------+------+------+------------+-------------+ | uResS/Done_Byte | Local| | 2 | 0.361 | 2.261 | +---------------------+--------------+------+------+------------+-------------+ |uXmit/uSpack/Done_Wo | | | | | | | rd | Local| | 6 | 1.097 | 1.767 | +---------------------+--------------+------+------+------------+-------------+ |uXmit/uDpack/Done_Wo | | | | | | | rd | Local| | 2 | 0.000 | 1.436 | +---------------------+--------------+------+------+------------+-------------+ | db0/u2/Q | Local| | 12 | 0.000 | 2.367 | +---------------------+--------------+------+------+------------+-------------+ * Net Skew is the difference between the minimum and maximum routing only delays for the net. Note this is different from Clock Skew which is reported in TRCE timing report. Clock Skew is the difference between the minimum and maximum path delays which includes logic delays. Timing Score: 0 (Setup: 0, Hold: 0) Asterisk (*) preceding a constraint indicates it was not met. This may be due to a setup or hold violation. ---------------------------------------------------------------------------------------------------------- Constraint | Check | Worst Case | Best Case | Timing | Timing | | Slack | Achievable | Errors | Score ---------------------------------------------------------------------------------------------------------- Autotimespec constraint for clock net DAC | SETUP | N/A| 27.522ns| N/A| 0 _Clk_OBUF | HOLD | 0.933ns| | 0| 0 ---------------------------------------------------------------------------------------------------------- Autotimespec constraint for clock net uXm | SETUP | N/A| 2.506ns| N/A| 0 it/uTxMAC/u1/Q | HOLD | 1.242ns| | 0| 0 ---------------------------------------------------------------------------------------------------------- Autotimespec constraint for clock net db0 | SETUP | N/A| 4.648ns| N/A| 0 /u0/serClk | HOLD | 1.026ns| | 0| 0 ---------------------------------------------------------------------------------------------------------- Autotimespec constraint for clock net fCl | SETUP | N/A| 23.524ns| N/A| 0 k_out_OBUF | HOLD | 1.067ns| | 0| 0 ---------------------------------------------------------------------------------------------------------- Autotimespec constraint for clock net uQu | SETUP | N/A| 2.206ns| N/A| 0 er/u3/u1/Q | HOLD | 1.293ns| | 0| 0 ---------------------------------------------------------------------------------------------------------- Autotimespec constraint for clock net uXm | SETUP | N/A| 3.223ns| N/A| 0 it/uDpack/w/C_0_0_not0000 | HOLD | 1.292ns| | 0| 0 ---------------------------------------------------------------------------------------------------------- Autotimespec constraint for clock net uXm | SETUP | N/A| 4.210ns| N/A| 0 it/uDpack/u1/Q | HOLD | 0.901ns| | 0| 0 ---------------------------------------------------------------------------------------------------------- Autotimespec constraint for clock net uRe | SETUP | N/A| 2.460ns| N/A| 0 sS/Done_Byte | HOLD | 1.199ns| | 0| 0 ---------------------------------------------------------------------------------------------------------- Autotimespec constraint for clock net uXm | SETUP | N/A| 5.688ns| N/A| 0 it/uSpack/Done_Word | HOLD | 0.849ns| | 0| 0 ---------------------------------------------------------------------------------------------------------- All constraints were met. INFO:Timing:2761 - N/A entries in the Constraints list may indicate that the constraint does not cover any paths or that it has no requested value. Generating Pad Report. All signals are completely routed. Total REAL time to PAR completion: 10 secs Total CPU time to PAR completion: 9 secs Peak Memory Usage: 157 MB Placer: Placement generated during map. Routing: Completed - No errors found. Number of error messages: 0 Number of warning messages: 12 Number of info messages: 4 Writing design to file FPGA_ctrl.ncd PAR done!