Release 11.3 - par L.57 (nt)
Copyright (c) 1995-2009 Xilinx, Inc.  All rights reserved.

Fri Nov 01 12:06:17 2013

  SmartGuide Results
  ------------------
  This section describes the guide results after invoking the Router. This
  report accurately reflects the differences between the input design
  and the guide design.

  Number of Components in the input design    |    731
    Number of guided Components               |    731 out of    731 100.0%
    Number of re-implemented Components       |      0 out of    731   0.0%
    Number of new/changed Components          |      0 out of    731   0.0%
  Number of Nets in the input design          |   1689
    Number of guided Nets                     |   1619 out of   1689  95.9%
    Number of partially guided Nets           |     50 out of   1689   3.0%
    Number of re-routed Nets                  |     20 out of   1689   1.2%
    Number of new/changed Nets                |      0 out of   1689   0.0%


The following Components were re-implemented.
---------------------------------------------


The following Components are new/changed.
-----------------------------------------


The following Nets were re-routed.
----------------------------------
 uResH/Result<1>1.
 r6/u1/Q0<4>.
 r6/u1/Q1<4>.
 r6/u1/Q0<5>.
 r6/u1/Q1<5>.
 r6/u1/Q0<7>.
 r6/u1/Q1<7>.
 r6/u1/Q1<11>.
 state_D<0>.
 r6/u1/Q0<13>.
 r6/u1/Q1<13>.
 DAC_D<6>.
 uProg/MaskByte_0_0.
 uProg/MaskByte_0_7.
 uProg/MaskByte_0_6.
 u10/Reg<16>.
 u10/Reg<4>.
 uXmit/uDpack/LastWord.
 N401.
 uXmit/uSpack/Data<6>_SW2_1.


The following Nets are new/changed.
-----------------------------------


The following Nets were partially guided.
-----------------------------------------
 uResH/p5/count_not000114.
 u1/u5/Q.
 uResH/m6/MACbytenum<1>.
 uXmit/uTxMAC/ByteCount<1>.
 uXmit/uTxMAC/ByteCount<3>.
 uXmit/uTxMAC/ByteCount<2>.
 db0/u0/SerCnt<2>.
 db0/u0/SerCnt<1>.
 db0/u0/SerCnt<0>.
 DAC_D<10>.
 ser_Go.
 db0/u0/u1/Qb.
 uResH/Done_LEDdis.
 uResH/Done_Phy.
 uProg/Cnt<1>.
 uXmit/uDpack/w/C<1>.
 uResS/ReadCount<2>.
 DAC_D<8>.
 db0/Ai<3>.
 db0/Ai<1>.
 uXmit/uSpack/w/C<1>.
 uXmit/uSpack/ChanCount<0>.
 u1/TxRx_Q<0>.
 uResS/ReadCount<1>.
 uXmit/uSpack/Data_and0000.
 u1/TxRx_Q<1>.
 uResS/ReadCount<3>.
 uQuer/ChanCnt<1>.
 uResH/m1b/Q.
 state_En.
 N35.
 DAC_D<0>.
 ser_D<3>.
 uXmit/RAwrD<0>LogicTrst116.
 db0/Ao<0>.
 uQuer/ChanCnt<0>.
 DAC_D<9>.
 uRd/newstate<1>.
 u1/TxRx_Q<2>.
 db0/Ao<1>.
 db0/Ao<3>.
 db0/Ao<2>.
 r6/u1/En_r1.
 db0/r1/En<1>.
 DAC_Addr<0>.
 DAC_Addr<1>.
 DAC_Addr<2>.
 DAC_Addr<3>.
 DAC_D<2>.
 DAC_D<4>.