----------------------------------------------------------------------------------
-- Company: University of Connecticut
-- Engineer: Igor Senderovich
-- 
-- Create Date:    04:14:41 10/01/2007 
-- Design Name: 
-- Module Name:    Eth_emulator_ctrl - Behavioral 
-- Description:	   Emulator for the Ethernet Controller Chip designed to test 
--		   communication across the the Multiplexed Intel bus and 
--		   Ethernet controller register operations.
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;

entity Eth_emulator_ctrl is
    port ( fClk : in  STD_LOGIC; -- "fast" 20MHz clock
	   Rst : in STD_LOGIC;

	   -- puppet signals to the emulator from simulator
           Go_GetPacket : in  STD_LOGIC_VECTOR (2 downto 0);
	   iINT_sug : in  STD_LOGIC;
	   iINT_type : in  STD_LOGIC_VECTOR (3 downto 0);
	   iINT : out  STD_LOGIC;

	   -- Eth_emulator_ctrl lines ------------------------
	   ALE : in STD_LOGIC;
	   AD  : inout STD_LOGIC_VECTOR (7 downto 0);
	   iRD : in STD_LOGIC;
	   iWR : in STD_LOGIC
	);
end Eth_emulator_ctrl;

architecture Behavioral of Eth_emulator_ctrl is

	component pulser is
	    port ( Clk : in  STD_LOGIC;
		   D   : in  STD_LOGIC;
           	   Q   : out  STD_LOGIC
		 );
	end component;

	component c_delay is
	    port ( Clk : in  STD_LOGIC;
		   D   : in  STD_LOGIC;
           	   Q   : out  STD_LOGIC
		 );
	end component;
--
--	component EdgeCounter4bit is
--	    port ( Clk : in  STD_LOGIC;
--		   Go : in  STD_LOGIC;
--		   En : out STD_LOGIC;
--		   Q : out  STD_LOGIC_VECTOR (3 downto 0)
--		 );
--	end component;
	
	component Regs is
	    Port ( Clk : in  STD_LOGIC;
        	   Rst : in  STD_LOGIC;
          	   Go_GetPacket : in  STD_LOGIC_VECTOR (2 downto 0);
		   iINT_sug : in  STD_LOGIC;
		   iINT_type : in  STD_LOGIC_VECTOR (3 downto 0);
		   iINT : out STD_LOGIC;
           	   Wr : in  STD_LOGIC;
           	   Rd : in  STD_LOGIC;
           	   A : in  STD_LOGIC_VECTOR (7 downto 0);
           	   D : in  STD_LOGIC_VECTOR (7 downto 0);
           	   Q : out  STD_LOGIC_VECTOR (7 downto 0);
		   Done_Send : out STD_LOGIC
		 );
	end component;
	
	signal Regs_D : STD_LOGIC_VECTOR (7 downto 0);
	signal Regs_Q : STD_LOGIC_VECTOR (7 downto 0);
	signal Regs_A : STD_LOGIC_VECTOR (7 downto 0);
	signal Regs_Wr : STD_LOGIC;
	signal Regs_Rd : STD_LOGIC;
	signal Rd : STD_LOGIC;
	signal iRD_delay : STD_LOGIC;
	signal ifClk : STD_LOGIC;
	
begin

	u1: Regs
	port map (fClk,Rst,Go_GetPacket,iINT_sug,iINT_type,iINT,
		  Regs_Wr,Regs_Rd,Regs_A,Regs_D,Regs_Q);

	u2: pulser port map(fClk, iWR, Regs_Wr);
	
	Rd <= not iRd;
	u3: pulser port map(fClk, Rd, Regs_Rd);
	Regs_D <= AD;
	
	--u4: c_delay port map(fClk, iRD, iRD_delay);
	ifClk <= not fClk;
	u4: c_delay port map(ifClk, iRD, iRD_delay);

	tb : process (ALE,iRD_delay,iINT_sug)
	begin
		if (Rst='0') then
			if falling_edge(ALE) then
				Regs_A  <= AD;
			else
				Regs_A  <= Regs_A;
			end if;
			
			if (iRD_delay='0') then
				AD <= Regs_Q;
			else
				AD <= "ZZZZZZZZ";
			end if;
		end if;

--		while (1) loop
--			wait until ALE='1';
--			wait for 10 ns;
--			wait for 40 ns;
--			Regs_A  <= AD;
--	
--			if (iRD='0' and iWR='1') then
--				Regs_Wr <= '1';
--			elsif (iRD='1' and iWR='0') then
--				Regs_Wr <= '0';				
--			end if;
--	
--			wait for 160 ns;
--			wait until iRW='1';
--	
--			if (iRD='1' and iWR='0') then
--				AD <= Regs_Q;
--			elsif (iRD='0' and iWR='1') then
--				Regs_D <= AD;				
--			end if;
--	
--			wait for 40 ns;
--		
--			Regs_Wr <= 'Z';
--			Regs_D  <= "ZZZZZZZZ";
--			AD      <= "ZZZZZZZZ";
--
--		end loop;

	end process;
	
end Behavioral;