-------------------------------------------------------------------------------- -- Company: University of Connecticut -- Engineer: Igor Senderovich -- -- Create Date: 01:46:07 02/15/2008 -- Design Name: Eth_emulator_ctrl -- Module Name: C:/work/GlueX/SiPMs/Electronics/FPGA/TotalTest/Eth_emulator_MuxIntelTest.vhd -- Project Name: TotalTest -- Target Device: -- Tool versions: -- Description: Container for all FPGA and emulators for Ethernet Controller, -- DAC, ADC, Temperature sensor -- -------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.STD_LOGIC_ARITH.all; use IEEE.STD_LOGIC_UNSIGNED.all; entity Eth_emulator_MuxIntelTest_vhd is end Eth_emulator_MuxIntelTest_vhd; architecture behavior of Eth_emulator_MuxIntelTest_vhd is -- Component Declaration for the Unit Under Test (UUT) component Eth_emulator_ctrl port ( fClk : in STD_LOGIC; -- "fast" 20MHz clock Rst : in STD_LOGIC; -- puppet signals to the emulator from simulator Go_GetPacket : in STD_LOGIC_VECTOR (2 downto 0); iINT_sug : in STD_LOGIC; iINT_type : in STD_LOGIC_VECTOR (3 downto 0); iINT : out STD_LOGIC; -- Eth_emulator_ctrl lines ------------------------ ALE : in STD_LOGIC; AD : inout STD_LOGIC_VECTOR (7 downto 0); iRD : in STD_LOGIC; iWR : in STD_LOGIC ); end component; component FPGA_ctrl is port ( fClk : in STD_LOGIC; Rst : in STD_LOGIC; Eth_iRst : inout STD_LOGIC; Eth_iINT : in STD_LOGIC; LocStamp : in STD_LOGIC_VECTOR (5 downto 0); state_Qout : out STD_LOGIC_VECTOR (2 downto 0); -- SPI bus (with ADC and Temp sensors) lines SPI_SCLK : out STD_LOGIC; SPI_T_CE : out STD_LOGIC; SPI_A_iCS : out STD_LOGIC; SPI_SDI : out STD_LOGIC; SPI_SDO : in STD_LOGIC; -- DAC lines ----------------------------- DAC_Clk : out STD_LOGIC; DAC_iRst : out STD_LOGIC; DAC_serISync : out STD_LOGIC; DAC_serData : out STD_LOGIC; -- MuxIntel lines ------------------------ ALE : out STD_LOGIC; AD : inout STD_LOGIC_VECTOR (7 downto 0); iRD : out STD_LOGIC; iWR : out STD_LOGIC; iCS : out STD_LOGIC; dbShort : in STD_LOGIC; --debug pin to short out waiting periods fClk_out : out STD_LOGIC; dbInfoStart : out STD_LOGIC; dbInfoStream : out STD_LOGIC ); end component; component Temp_emul is -- emulator for the Temp. sensor port ( RST : in STD_LOGIC; -- reset SCLK : in STD_LOGIC; -- clock SDO : out STD_LOGIC; -- serial data out CE : in STD_LOGIC; -- chip enable Error : out STD_LOGIC; -- error flag Din : in STD_LOGIC_VECTOR (9 downto 0)); -- parallel data in end component; component ADC_emulator is -- emulator for the ADC Port ( SCLK : in STD_LOGIC; -- clock iRst : in STD_LOGIC; -- reset iCS : in STD_LOGIC; -- chip select D_in : in STD_LOGIC; -- 12 bit serial instruction ch0 : in STD_LOGIC_VECTOR (11 downto 0); -- fake voltage data input ch1 : in STD_LOGIC_VECTOR (11 downto 0); -- for debugging purposes ch2 : in STD_LOGIC_VECTOR (11 downto 0); ch3 : in STD_LOGIC_VECTOR (11 downto 0); ch4 : in STD_LOGIC_VECTOR (11 downto 0); ch5 : in STD_LOGIC_VECTOR (11 downto 0); ch6 : in STD_LOGIC_VECTOR (11 downto 0); ch7 : in STD_LOGIC_VECTOR (11 downto 0); D_out : out STD_LOGIC; -- serial data output Error : out STD_LOGIC ); end component; component DAC_emulator -- declare a DAC emulator wrapper port ( SCLK : in STD_LOGIC; -- SCLK invRESET : in STD_LOGIC; -- /RESET invSYNC : in STD_LOGIC; -- /SYNC D_in : in STD_LOGIC; -- D_in -- 32 14-bit output channels ch00 : out STD_LOGIC_VECTOR (13 downto 0); ch01 : out STD_LOGIC_VECTOR (13 downto 0); ch02 : out STD_LOGIC_VECTOR (13 downto 0); ch03 : out STD_LOGIC_VECTOR (13 downto 0); ch04 : out STD_LOGIC_VECTOR (13 downto 0); ch05 : out STD_LOGIC_VECTOR (13 downto 0); ch06 : out STD_LOGIC_VECTOR (13 downto 0); ch07 : out STD_LOGIC_VECTOR (13 downto 0); ch08 : out STD_LOGIC_VECTOR (13 downto 0); ch09 : out STD_LOGIC_VECTOR (13 downto 0); ch10 : out STD_LOGIC_VECTOR (13 downto 0); ch11 : out STD_LOGIC_VECTOR (13 downto 0); ch12 : out STD_LOGIC_VECTOR (13 downto 0); ch13 : out STD_LOGIC_VECTOR (13 downto 0); ch14 : out STD_LOGIC_VECTOR (13 downto 0); ch15 : out STD_LOGIC_VECTOR (13 downto 0); ch16 : out STD_LOGIC_VECTOR (13 downto 0); ch17 : out STD_LOGIC_VECTOR (13 downto 0); ch18 : out STD_LOGIC_VECTOR (13 downto 0); ch19 : out STD_LOGIC_VECTOR (13 downto 0); ch20 : out STD_LOGIC_VECTOR (13 downto 0); ch21 : out STD_LOGIC_VECTOR (13 downto 0); ch22 : out STD_LOGIC_VECTOR (13 downto 0); ch23 : out STD_LOGIC_VECTOR (13 downto 0); ch24 : out STD_LOGIC_VECTOR (13 downto 0); ch25 : out STD_LOGIC_VECTOR (13 downto 0); ch26 : out STD_LOGIC_VECTOR (13 downto 0); ch27 : out STD_LOGIC_VECTOR (13 downto 0); ch28 : out STD_LOGIC_VECTOR (13 downto 0); ch29 : out STD_LOGIC_VECTOR (13 downto 0); ch30 : out STD_LOGIC_VECTOR (13 downto 0); ch31 : out STD_LOGIC_VECTOR (13 downto 0) ); end component; --Inputs SIGNAL fClk : std_logic := '0'; SIGNAL Rst : std_logic := '1'; -- SIGNAL Go : std_logic := '0'; -- SIGNAL RiW : std_logic := '0'; -- SIGNAL A : std_logic_vector(7 downto 0) := (others=>'0'); -- SIGNAL D : std_logic_vector(7 downto 0) := (others=>'0'); -- signal Regs_Q : STD_LOGIC_VECTOR (7 downto 0); -- -- --BiDirs -- SIGNAL AD : std_logic_vector(7 downto 0); -- -- --Outputs -- SIGNAL sClk : std_logic; signal fClk_out : STD_LOGIC; signal dbInfoStart : STD_LOGIC; signal dbInfoStream : STD_LOGIC; signal state_Qout : STD_LOGIC_VECTOR (2 downto 0); SIGNAL ALE : std_logic; SIGNAL iRD : std_logic; SIGNAL iWR : std_logic; SIGNAL AD : std_logic_vector(7 downto 0); SIGNAL iCS : STD_LOGIC; signal iINT_sug : STD_LOGIC := '1'; signal iINT : STD_LOGIC; signal iINT_type : STD_LOGIC_VECTOR (3 downto 0); SIGNAL Eth_iRst : std_logic := '1'; SIGNAL LocStamp : std_logic_vector(5 downto 0) := "011100"; SIGNAL Go_GetPacket : std_logic_vector (2 downto 0) := "000"; -- SPI lines -- signal SPI_SDO : STD_LOGIC; signal SPI_SCLK : STD_LOGIC; signal SPI_iRst_out : STD_LOGIC; signal SPI_T_CE : STD_LOGIC; signal SPI_A_iCS : STD_LOGIC; signal SPI_SDI : STD_LOGIC; signal SPI_A_err : STD_LOGIC; signal SPI_T_err : STD_LOGIC; --emulator signals signal A_ch0 : STD_LOGIC_VECTOR (11 downto 0):="100000000001"; signal A_ch1 : STD_LOGIC_VECTOR (11 downto 0):="100000000011"; signal A_ch2 : STD_LOGIC_VECTOR (11 downto 0):="100000000101"; signal A_ch3 : STD_LOGIC_VECTOR (11 downto 0):="100000000111"; signal A_ch4 : STD_LOGIC_VECTOR (11 downto 0):="100000001001"; signal A_ch5 : STD_LOGIC_VECTOR (11 downto 0):="100000001011"; signal A_ch6 : STD_LOGIC_VECTOR (11 downto 0):="100000001101"; signal A_ch7 : STD_LOGIC_VECTOR (11 downto 0):="100000001111"; signal T_Din : STD_LOGIC_VECTOR (9 downto 0) :="1011001101"; -- DAC signals signal DAC_Clk : STD_LOGIC; signal DAC_iRst : STD_LOGIC; -- /RESET signal DAC_serISync : STD_LOGIC; -- /SYNC signal DAC_serData : STD_LOGIC; -- D_in signal DAC_ch00 : STD_LOGIC_VECTOR (13 downto 0) := "00" & X"001"; signal DAC_ch01 : STD_LOGIC_VECTOR (13 downto 0) := "00" & X"002"; signal DAC_ch02 : STD_LOGIC_VECTOR (13 downto 0) := "00" & X"003"; signal DAC_ch03 : STD_LOGIC_VECTOR (13 downto 0) := "00" & X"004"; signal DAC_ch04 : STD_LOGIC_VECTOR (13 downto 0) := "00" & X"005"; signal DAC_ch05 : STD_LOGIC_VECTOR (13 downto 0) := "00" & X"006"; signal DAC_ch06 : STD_LOGIC_VECTOR (13 downto 0) := "00" & X"007"; signal DAC_ch07 : STD_LOGIC_VECTOR (13 downto 0) := "00" & X"008"; signal DAC_ch08 : STD_LOGIC_VECTOR (13 downto 0) := "00" & X"009"; signal DAC_ch09 : STD_LOGIC_VECTOR (13 downto 0) := "00" & X"00A"; signal DAC_ch10 : STD_LOGIC_VECTOR (13 downto 0) := "00" & X"00C"; signal DAC_ch11 : STD_LOGIC_VECTOR (13 downto 0) := "00" & X"00B"; signal DAC_ch12 : STD_LOGIC_VECTOR (13 downto 0) := "00" & X"00D"; signal DAC_ch13 : STD_LOGIC_VECTOR (13 downto 0) := "00" & X"00E"; signal DAC_ch14 : STD_LOGIC_VECTOR (13 downto 0) := "00" & X"00F"; signal DAC_ch15 : STD_LOGIC_VECTOR (13 downto 0) := "00" & X"010"; signal DAC_ch16 : STD_LOGIC_VECTOR (13 downto 0) := "00" & X"011"; signal DAC_ch17 : STD_LOGIC_VECTOR (13 downto 0) := "00" & X"012"; signal DAC_ch18 : STD_LOGIC_VECTOR (13 downto 0) := "00" & X"013"; signal DAC_ch19 : STD_LOGIC_VECTOR (13 downto 0) := "00" & X"014"; signal DAC_ch20 : STD_LOGIC_VECTOR (13 downto 0) := "00" & X"015"; signal DAC_ch21 : STD_LOGIC_VECTOR (13 downto 0) := "00" & X"016"; signal DAC_ch22 : STD_LOGIC_VECTOR (13 downto 0) := "00" & X"017"; signal DAC_ch23 : STD_LOGIC_VECTOR (13 downto 0) := "00" & X"018"; signal DAC_ch24 : STD_LOGIC_VECTOR (13 downto 0) := "00" & X"019"; signal DAC_ch25 : STD_LOGIC_VECTOR (13 downto 0) := "00" & X"01A"; signal DAC_ch26 : STD_LOGIC_VECTOR (13 downto 0) := "00" & X"01B"; signal DAC_ch27 : STD_LOGIC_VECTOR (13 downto 0) := "00" & X"01C"; signal DAC_ch28 : STD_LOGIC_VECTOR (13 downto 0) := "00" & X"01D"; signal DAC_ch29 : STD_LOGIC_VECTOR (13 downto 0) := "00" & X"01E"; signal DAC_ch30 : STD_LOGIC_VECTOR (13 downto 0) := "00" & X"01F"; signal DAC_ch31 : STD_LOGIC_VECTOR (13 downto 0) := "00" & X"020"; begin -- Instantiate the Unit Under Test (UUT) uut1: Eth_emulator_ctrl port map(fClk,Rst,Go_GetPacket,iINT_sug,iINT_type,iINT,ALE,AD,iRD,iWR); uut2: FPGA_ctrl port map(fClk,Rst,Eth_iRst,iINT,LocStamp,state_Qout, SPI_SCLK, SPI_T_CE, SPI_A_iCS, SPI_SDI, SPI_SDO, DAC_Clk, DAC_iRst, DAC_serISync, DAC_serData, ALE, AD, iRD, iWR, iCS, '1', -- dbShort pin (to void Reset wait time for Eth. chip) fClk_out,dbInfoStart,dbInfoStream ); uut3: Temp_emul port map (SPI_iRst_out, SPI_SCLK, SPI_SDO, SPI_T_CE, SPI_T_err, T_Din); uut4: ADC_emulator port map (SPI_SCLK, SPI_iRst_out, SPI_A_iCS, SPI_SDI, A_ch0, A_ch1, A_ch2, A_ch3, A_ch4, A_ch5, A_ch6, A_ch7, SPI_SDO, SPI_A_err); uut5: DAC_emulator port map (SPI_SCLK, DAC_iRst, DAC_serISync, DAC_serData, DAC_ch00, DAC_ch01, DAC_ch02, DAC_ch03, DAC_ch04, DAC_ch05, DAC_ch06, DAC_ch07, DAC_ch08, DAC_ch09, DAC_ch10, DAC_ch11, DAC_ch12, DAC_ch13, DAC_ch14, DAC_ch15, DAC_ch16, DAC_ch17, DAC_ch18, DAC_ch19, DAC_ch20, DAC_ch21, DAC_ch22, DAC_ch23, DAC_ch24, DAC_ch25, DAC_ch26, DAC_ch27, DAC_ch28, DAC_ch29, DAC_ch30, DAC_ch31); Startup : process begin Rst <= '1'; -- turn on reset wait for 50 ns; Rst <= '0'; -- turn off reset wait for 343 ns; -- after some arbitrary amount of time... -- "Oscillator stabilization" interrupt iINT_sug <= '0'; -- interrupt! iINT_type <= "0100"; wait for 50 ns; iINT_sug <= '1'; wait for 4500 ns; -- "Self-Initialization complete" interrupt iINT_sug <= '0'; -- interrupt! iINT_type <= "0001"; wait for 50 ns; iINT_sug <= '1'; -- Inject "soft reset" (0xD2) packet wait for 85000 ns; -- after hard reset processes are complete Go_GetPacket <= "001"; wait for 50ns; Go_GetPacket <= "000"; wait for 1000 ns; iINT_sug <= '0'; -- Rx buffer non-empty interrupt (you got mail!) iINT_type <= "1000"; wait for 50 ns; iINT_sug <= '1'; -- Inject a Query (0x51) packet wait for 80000 ns; Go_GetPacket <= "010"; wait for 50ns; Go_GetPacket <= "000"; iINT_sug <= '0'; -- Rx buffer non-empty interrupt (you got mail!) iINT_type <= "1000"; wait for 50 ns; iINT_sug <= '1'; -- Inject a Program (0x50) packet wait for 150000 ns; Go_GetPacket <= "011"; wait for 50ns; Go_GetPacket <= "000"; iINT_sug <= '0'; -- Rx buffer non-empty interrupt (you got mail!) iINT_type <= "1000"; wait for 50 ns; iINT_sug <= '1'; -- iINT_sug <= '0'; -- interrupt! -- iINT_type <= "0100"; -- wait for 50 ns; -- iINT_sug <= '1'; -- -- wait for 4500 ns; -- -- iINT_sug <= '0'; -- interrupt! -- iINT_type <= "0001"; -- wait for 50 ns; -- iINT_sug <= '1'; -- wait for 10000 ns; -- Go_GetPacket <= '1'; -- wait for 50ns; -- Go_GetPacket <= '0'; wait; end process; MakeCLK : process begin wait for 25ns; fClk <= '1'; wait for 25ns; fClk <= '0'; end process; end;