----------------------------------------------------------------------------------
-- Company: University of Connecticut
-- Engineer: Brendan Krueger
-- 
-- Create Date:    14:36:14 06/19/2007 
-- Design Name:    Shift Register for DAC Emulator
-- Module Name:    DAC_shifter - DAC_shift_arch  
-- Project Name:   Readout Electronics Digital Board
-- Target Devices: no devices; for testing of other designs
-- Tool versions: Xilinx ISE WebPACK 9.1.03i
-- Description: Serial-in, parallel-out shift register
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity DAC_shifter is
    port ( SCLK	: in STD_LOGIC;		-- clock
           invRESET : in STD_LOGIC;	-- asynchronous, active-low reset
           Enable : in STD_LOGIC;	-- shift enable
           D_in	: in STD_LOGIC;		-- serial in
           Addr	: out STD_LOGIC_VECTOR (4 downto 0); -- address portion of output (5MSB)
           Code	: out STD_LOGIC_VECTOR (13 downto 0)); -- code portion of output (14LSB)
end DAC_shifter;

architecture DAC_shift_arch of DAC_shifter is

	signal SReg : STD_LOGIC_VECTOR (18 downto 0);	-- internal resistor value
	signal delayed : STD_LOGIC; -- delay serial input due to delay caused by 19-cycle hold block

begin

	delayer : process (SCLK, D_in, delayed)		-- delay serial input
	begin
		if (rising_edge(SCLK)) then
			delayed <= D_in;
		else
			delayed <= delayed;
		end if;
	end process delayer;

	shift_reg : process (SCLK, invRESET, Enable, D_in)
	begin
		if (invRESET = '0') then
			-- asynchronous, active-low reset
			SReg <= "0000000000000000000";
		else
			if (Enable = '1') then
				if (falling_edge(SCLK)) then
					-- shift up when shift is enabled
					for i in 0 to 17 loop
						SReg(i+1) <= SReg(i);
					end loop;
					SReg(0) <= delayed;
				else
					SReg <= SReg;
				end if;
			else
				SReg <= SReg;
			end if;
		end if;
	end process shift_reg;
	
	Addr <= SReg(18 downto 14);		-- split parallel output
	Code <= SReg(13 downto 0);		-- split parallel output

end DAC_shift_arch;