----------------------------------------------------------------------------------
-- Company: University of Connecticut
-- Engineer: Brendan Krueger
-- 
-- Create Date:    14:27:46 06/19/2007 
-- Design Name:    Terminal Register for DAC Emulator
-- Module Name:    DAC_register - DAC_reg_arch 
-- Project Name:   Readout Electronics Digital Board
-- Target Devices: no devices; for testing of other designs
-- Tool versions: Xilinx ISE WebPACK 9.1.03i
-- Description: 14-bit register
--
-- Dependencies: 
--
-- Revision: Igor Senderovich (D accepted on *falling* clock edge, as per spec sheet)
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity DAC_register is
    Port ( CLK : in  STD_LOGIC;			-- clock
           invRST : in  STD_LOGIC;		-- asynchronous, active-low reset
	   Enable : in STD_LOGIC;		-- read enable
           D : in  STD_LOGIC_VECTOR (13 downto 0);	-- input
           Q : out  STD_LOGIC_VECTOR (13 downto 0)	-- output
	 );
end DAC_register;

architecture DAC_reg_arch of DAC_register is

	signal storage : STD_LOGIC_VECTOR (13 downto 0);	-- internal storage value

begin

	reg : process (CLK, invRST, Enable, D, storage)
	begin
		if (invRST = '0') then
			-- asynchronous, active-low reset
			storage <= "00000000000000";
		else
			if (falling_edge(CLK)) then
				if (Enable = '1') then
					-- if read enabled, load new value
					storage <= D;
				else
					storage <= storage;
				end if;
			else
				storage <= storage;
			end if;
		end if;
	end process reg;
	
	Q <= storage;		-- register always writes out

end DAC_reg_arch;