----------------------------------------------------------------------------------
-- Company: University of Connecticut
-- Engineer: Brendan Krueger
-- 
-- Create Date:    15:50:08 06/19/2007 
-- Design Name:    Follow Pulse Component for DAC Emulator
-- Module Name:    DAC_follow - DAC_follow_arch 
-- Project Name:   Readout Electronics Digital Board
-- Target Devices: no devices; for testing of other designs
-- Tool versions: Xilinx ISE WebPACK 9.1.03i
-- Description: Watches an input signal and pulses after the input falls
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity DAC_follow is
    port ( CLK : in STD_LOGIC;		-- clock
           invReset : in STD_LOGIC;	-- asynchronous, active-low reset
	   D : in STD_LOGIC;		-- input signal to watch
           Q : out STD_LOGIC		-- output line to pulse
	 );
end DAC_follow;

architecture DAC_follow_arch of DAC_follow is

	signal prev : STD_LOGIC;	-- previous value of input
	signal curr : STD_LOGIC;	-- current value of input

begin

	follower : process (CLK, invReset, D, prev, curr)
	begin
		if (invReset = '0') then
			-- asynchronous, active-low reset
			prev <= '0';
			curr <= '0';
		else
			if (rising_edge(CLK)) then
				-- cycle signals to track last two values
				prev <= curr;
				curr <= D;
			else
				prev <= prev;
				curr <= curr;
			end if;
		end if;
	end process follower;
	
	faller : process (prev, curr)
	begin
		if (prev = '1') then
			if (curr = '0') then
				-- pulse on a falling edge
				Q <= '1';
			else
				Q <= '0';
			end if;
		else
			Q <= '0';
		end if;
	end process faller;

end DAC_follow_arch;