---------------------------------------------------------------------------------- -- Company: University of Connecticut -- Engineer: Brendan Krueger -- -- Create Date: 14:10:45 06/19/2007 -- Design Name: Emulator for AD5535 DAC -- Module Name: DAC_emulator - DAC_emul_arch -- Project Name: Readout Electronics Digital Board -- Target Devices: no devices; for testing of other designs -- Tool versions: Xilinx ISE WebPACK 9.1.03i -- Description: Emulates the actions of the Analog Devices' AD5535 DAC and -- displays channels. Mainly intended for testing purposes. -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.STD_LOGIC_ARITH.all; use IEEE.STD_LOGIC_UNSIGNED.all; ---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity DAC_emulator is port ( SCLK : in STD_LOGIC; -- SCLK invRESET : in STD_LOGIC; -- /RESET invSYNC : in STD_LOGIC; -- /SYNC D_in : in STD_LOGIC; -- D_in -- 32 14-bit output channels ch00 : out STD_LOGIC_VECTOR (13 downto 0); ch01 : out STD_LOGIC_VECTOR (13 downto 0); ch02 : out STD_LOGIC_VECTOR (13 downto 0); ch03 : out STD_LOGIC_VECTOR (13 downto 0); ch04 : out STD_LOGIC_VECTOR (13 downto 0); ch05 : out STD_LOGIC_VECTOR (13 downto 0); ch06 : out STD_LOGIC_VECTOR (13 downto 0); ch07 : out STD_LOGIC_VECTOR (13 downto 0); ch08 : out STD_LOGIC_VECTOR (13 downto 0); ch09 : out STD_LOGIC_VECTOR (13 downto 0); ch10 : out STD_LOGIC_VECTOR (13 downto 0); ch11 : out STD_LOGIC_VECTOR (13 downto 0); ch12 : out STD_LOGIC_VECTOR (13 downto 0); ch13 : out STD_LOGIC_VECTOR (13 downto 0); ch14 : out STD_LOGIC_VECTOR (13 downto 0); ch15 : out STD_LOGIC_VECTOR (13 downto 0); ch16 : out STD_LOGIC_VECTOR (13 downto 0); ch17 : out STD_LOGIC_VECTOR (13 downto 0); ch18 : out STD_LOGIC_VECTOR (13 downto 0); ch19 : out STD_LOGIC_VECTOR (13 downto 0); ch20 : out STD_LOGIC_VECTOR (13 downto 0); ch21 : out STD_LOGIC_VECTOR (13 downto 0); ch22 : out STD_LOGIC_VECTOR (13 downto 0); ch23 : out STD_LOGIC_VECTOR (13 downto 0); ch24 : out STD_LOGIC_VECTOR (13 downto 0); ch25 : out STD_LOGIC_VECTOR (13 downto 0); ch26 : out STD_LOGIC_VECTOR (13 downto 0); ch27 : out STD_LOGIC_VECTOR (13 downto 0); ch28 : out STD_LOGIC_VECTOR (13 downto 0); ch29 : out STD_LOGIC_VECTOR (13 downto 0); ch30 : out STD_LOGIC_VECTOR (13 downto 0); ch31 : out STD_LOGIC_VECTOR (13 downto 0) ); end DAC_emulator; architecture DAC_emul_arch of DAC_emulator is -- declare component wrappers component DAC_demux port ( S : in STD_LOGIC_VECTOR (4 downto 0); D : in STD_LOGIC; Q : out STD_LOGIC_VECTOR (31 downto 0) ); end component; component DAC_follow port ( CLK : in STD_LOGIC; invReset : in STD_LOGIC; D : in STD_LOGIC; Q : out STD_LOGIC ); end component; component DAC_hold19 port ( CLK : in STD_LOGIC; invReset : in STD_LOGIC; invBegin : in STD_LOGIC; Go : out STD_LOGIC ); end component; component DAC_shifter port ( SCLK : in STD_LOGIC; invRESET : in STD_LOGIC; Enable : in STD_LOGIC; D_in : in STD_LOGIC; Addr : out STD_LOGIC_VECTOR (4 downto 0); Code : out STD_LOGIC_VECTOR (13 downto 0) ); end component; component DAC_register port ( CLK : in STD_LOGIC; invRST : in STD_LOGIC; Enable : in STD_LOGIC; D : in STD_LOGIC_VECTOR (13 downto 0); Q : out STD_LOGIC_VECTOR (13 downto 0) ); end component; -- declare internal signals to connect components signal Enable : STD_LOGIC; signal Reg_Enable : STD_LOGIC; signal Reg32_Enable : STD_LOGIC_VECTOR (31 downto 0); signal Addr : STD_LOGIC_VECTOR (4 downto 0); signal Code : STD_LOGIC_VECTOR (13 downto 0); begin -- port maps to create component instances u1: DAC_demux port map (Addr, Reg_Enable, Reg32_Enable); u2: DAC_follow port map (SCLK, invReset, Enable, Reg_Enable); u3: DAC_hold19 port map (SCLK, invReset, invSync, Enable); u4: DAC_shifter port map (SCLK, invReset, Enable, D_in, Addr, Code); u500: DAC_register port map (SCLK, invReset, Reg32_Enable(0), Code, ch00); u501: DAC_register port map (SCLK, invReset, Reg32_Enable(1), Code, ch01); u502: DAC_register port map (SCLK, invReset, Reg32_Enable(2), Code, ch02); u503: DAC_register port map (SCLK, invReset, Reg32_Enable(3), Code, ch03); u504: DAC_register port map (SCLK, invReset, Reg32_Enable(4), Code, ch04); u505: DAC_register port map (SCLK, invReset, Reg32_Enable(5), Code, ch05); u506: DAC_register port map (SCLK, invReset, Reg32_Enable(6), Code, ch06); u507: DAC_register port map (SCLK, invReset, Reg32_Enable(7), Code, ch07); u508: DAC_register port map (SCLK, invReset, Reg32_Enable(8), Code, ch08); u509: DAC_register port map (SCLK, invReset, Reg32_Enable(9), Code, ch09); u510: DAC_register port map (SCLK, invReset, Reg32_Enable(10), Code, ch10); u511: DAC_register port map (SCLK, invReset, Reg32_Enable(11), Code, ch11); u512: DAC_register port map (SCLK, invReset, Reg32_Enable(12), Code, ch12); u513: DAC_register port map (SCLK, invReset, Reg32_Enable(13), Code, ch13); u514: DAC_register port map (SCLK, invReset, Reg32_Enable(14), Code, ch14); u515: DAC_register port map (SCLK, invReset, Reg32_Enable(15), Code, ch15); u516: DAC_register port map (SCLK, invReset, Reg32_Enable(16), Code, ch16); u517: DAC_register port map (SCLK, invReset, Reg32_Enable(17), Code, ch17); u518: DAC_register port map (SCLK, invReset, Reg32_Enable(18), Code, ch18); u519: DAC_register port map (SCLK, invReset, Reg32_Enable(19), Code, ch19); u520: DAC_register port map (SCLK, invReset, Reg32_Enable(20), Code, ch20); u521: DAC_register port map (SCLK, invReset, Reg32_Enable(21), Code, ch21); u522: DAC_register port map (SCLK, invReset, Reg32_Enable(22), Code, ch22); u523: DAC_register port map (SCLK, invReset, Reg32_Enable(23), Code, ch23); u524: DAC_register port map (SCLK, invReset, Reg32_Enable(24), Code, ch24); u525: DAC_register port map (SCLK, invReset, Reg32_Enable(25), Code, ch25); u526: DAC_register port map (SCLK, invReset, Reg32_Enable(26), Code, ch26); u527: DAC_register port map (SCLK, invReset, Reg32_Enable(27), Code, ch27); u528: DAC_register port map (SCLK, invReset, Reg32_Enable(28), Code, ch28); u529: DAC_register port map (SCLK, invReset, Reg32_Enable(29), Code, ch29); u530: DAC_register port map (SCLK, invReset, Reg32_Enable(30), Code, ch30); u531: DAC_register port map (SCLK, invReset, Reg32_Enable(31), Code, ch31); end DAC_emul_arch;