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-- Company: University of Connecticut
-- Engineer: Brendan Krueger
-- 
-- Create Date:    16:06:21 06/19/2007 
-- Design Name:    5-to-32 Demux for DAC Emulator
-- Module Name:    DAC_demux - DAC_demux_arch  
-- Project Name:   Readout Electronics Digital Board
-- Target Devices: no devices; for testing of other designs
-- Tool versions: Xilinx ISE WebPACK 9.1.03i
-- Description: A 5-to-32 demultiplexer
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity DAC_demux is
    Port ( S : in  STD_LOGIC_VECTOR (4 downto 0);	-- 5-bit select
           D : in  STD_LOGIC;				-- data to demux
           Q : out  STD_LOGIC_VECTOR (31 downto 0)	-- 32 output lines
	 );
end DAC_demux;

architecture DAC_demux_arch of DAC_demux is

begin

	-- combinational logic to implement demux
	Q(0)	<= D and not (S(4)) and not(S(3)) and not(S(2)) and not(S(1)) and not(S(0));
	Q(1)	<= D and not (S(4)) and not(S(3)) and not(S(2)) and not(S(1)) and S(0);
	Q(2)	<= D and not (S(4)) and not(S(3)) and not(S(2)) and S(1) and not(S(0));
	Q(3)	<= D and not (S(4)) and not(S(3)) and not(S(2)) and S(1) and S(0);
	Q(4)	<= D and not (S(4)) and not(S(3)) and S(2) and not(S(1)) and not(S(0));
	Q(5)	<= D and not (S(4)) and not(S(3)) and S(2) and not(S(1)) and S(0);
	Q(6)	<= D and not (S(4)) and not(S(3)) and S(2) and S(1) and not(S(0));
	Q(7)	<= D and not (S(4)) and not(S(3)) and S(2) and S(1) and S(0);
	Q(8)	<= D and not (S(4)) and S(3) and not(S(2)) and not(S(1)) and not(S(0));
	Q(9)	<= D and not (S(4)) and S(3) and not(S(2)) and not(S(1)) and S(0);
	Q(10)	<= D and not (S(4)) and S(3) and not(S(2)) and S(1) and not(S(0));
	Q(11)	<= D and not (S(4)) and S(3) and not(S(2)) and S(1) and S(0);
	Q(12)	<= D and not (S(4)) and S(3) and S(2) and not(S(1)) and not(S(0));
	Q(13)	<= D and not (S(4)) and S(3) and S(2) and not(S(1)) and S(0);
	Q(14)	<= D and not (S(4)) and S(3) and S(2) and S(1) and not(S(0));
	Q(15)	<= D and not (S(4)) and S(3) and S(2) and S(1) and S(0);
	Q(16)	<= D and S(4) and not(S(3)) and not(S(2)) and not(S(1)) and not(S(0));
	Q(17)	<= D and S(4) and not(S(3)) and not(S(2)) and not(S(1)) and S(0);
	Q(18)	<= D and S(4) and not(S(3)) and not(S(2)) and S(1) and not(S(0));
	Q(19)	<= D and S(4) and not(S(3)) and not(S(2)) and S(1) and S(0);
	Q(20)	<= D and S(4) and not(S(3)) and S(2) and not(S(1)) and not(S(0));
	Q(21)	<= D and S(4) and not(S(3)) and S(2) and not(S(1)) and S(0);
	Q(22)	<= D and S(4) and not(S(3)) and S(2) and S(1) and not(S(0));
	Q(23)	<= D and S(4) and not(S(3)) and S(2) and S(1) and S(0);
	Q(24)	<= D and S(4) and S(3) and not(S(2)) and not(S(1)) and not(S(0));
	Q(25)	<= D and S(4) and S(3) and not(S(2)) and not(S(1)) and S(0);
	Q(26)	<= D and S(4) and S(3) and not(S(2)) and S(1) and not(S(0));
	Q(27)	<= D and S(4) and S(3) and not(S(2)) and S(1) and S(0);
	Q(28)	<= D and S(4) and S(3) and S(2) and not(S(1)) and not(S(0));
	Q(29)	<= D and S(4) and S(3) and S(2) and not(S(1)) and S(0);
	Q(30)	<= D and S(4) and S(3) and S(2) and S(1) and not(S(0));
	Q(31)	<= D and S(4) and S(3) and S(2) and S(1) and S(0);

end DAC_demux_arch;