----------------------------------------------------------------------------------
-- Company: University of Connecticut
-- Engineer: Brendan Krueger
-- 
-- Create Date:    11:43:24 07/13/2007 
-- Design Name:    ADC Emulator
-- Module Name:    ADC_emulator - emul_arch 
-- Project Name:   ADC Module
-- Target Devices: none; for testing and simulation only
-- Tool versions: Xilinx ISE WebPACK 9.1.03i
-- Description: Emulator for ADC chip
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity ADC_emulator is
    Port ( SCLK : in  STD_LOGIC;
           iRst : in  STD_LOGIC;
           iCS : in  STD_LOGIC;
           D_in : in  STD_LOGIC;
           ch0 : in  STD_LOGIC_VECTOR (11 downto 0);
           ch1 : in  STD_LOGIC_VECTOR (11 downto 0);
           ch2 : in  STD_LOGIC_VECTOR (11 downto 0);
           ch3 : in  STD_LOGIC_VECTOR (11 downto 0);
           ch4 : in  STD_LOGIC_VECTOR (11 downto 0);
           ch5 : in  STD_LOGIC_VECTOR (11 downto 0);
           ch6 : in  STD_LOGIC_VECTOR (11 downto 0);
           ch7 : in  STD_LOGIC_VECTOR (11 downto 0);
           D_out : out  STD_LOGIC;
           Error : out  STD_LOGIC
	 );
end ADC_emulator;

architecture emul_arch of ADC_emulator is

	component e_creg is
	    port ( Clk : in  STD_LOGIC;
		   iRst : in  STD_LOGIC;
		   En : in  STD_LOGIC;
		   D : in  STD_LOGIC_VECTOR (10 downto 0);
		   Q : out  STD_LOGIC_VECTOR (10 downto 0)
		 );
	end component;
	
	component e_demux is
	    port ( D : in  STD_LOGIC;
		   S : in  STD_LOGIC_VECTOR (2 downto 0);
		   Q : out  STD_LOGIC_VECTOR (7 downto 0)
		 );
	end component;
	
	component e_error is
	    port ( D : in  STD_LOGIC_VECTOR (7 downto 0);
		   Err : out  STD_LOGIC
		 );
	end component;
	
	component e_shift_in16 is
	    port ( Clk : in  STD_LOGIC;
		   iRst : in  STD_LOGIC;
		   En : in  STD_LOGIC;
		   D : in  STD_LOGIC;
		   Q_W : out  STD_LOGIC;
		   Q_D : out  STD_LOGIC_VECTOR (10 downto 0)
		 );
	end component;
	
	component e_shift_out15 is
	    port ( Clk : in  STD_LOGIC;
		   iRst : in  STD_LOGIC;
		   Sh_Ld : in  STD_LOGIC;
		   D : in  STD_LOGIC_VECTOR (11 downto 0);
		   A : in  STD_LOGIC_VECTOR (14 downto 12);
		   Q : out  STD_LOGIC
		 );
	end component;
	
	component e_tri is
	    port ( iEn : in  STD_LOGIC;
		   D : in  STD_LOGIC;
		   Q : out  STD_LOGIC
		 );
	end component;
	
	signal CS : STD_LOGIC;
	signal Wr : STD_LOGIC;
	signal CRegEn : STD_LOGIC;
	signal IntData : STD_LOGIC_VECTOR (10 downto 0);
	signal CData : STD_LOGIC_VECTOR (10 downto 0);
	signal DData : STD_LOGIC_VECTOR (2 downto 0);
	signal EData : STD_LOGIC_VECTOR (7 downto 0);
	signal ChEn : STD_LOGIC_VECTOR (7 downto 0);
	signal ChOut : STD_LOGIC_VECTOR (7 downto 0);
	signal ChOr : STD_LOGIC;

begin

	CS <= not iCS;
	CRegEn <= Wr and iCS;
	DData <= CData (8 downto 6);
	EData (7 downto 6) <= CData (10 downto 9);
	EData (5 downto 0) <= CData (5 downto 0);
	ChOr <= ChOut(7) or ChOut(6) or ChOut(5) or ChOut(4) or ChOut(3) or ChOut(2) or ChOut(1) or ChOut(0);
	
	u1: e_creg port map (SCLK, iRst, CRegEn, IntData, CData);
	u2: e_demux port map (CS, DData, ChEn);
	u3: e_error port map (EData, Error);
	u4: e_shift_in16 port map (SCLK, iRst, CS, D_in, Wr, IntData);
	--u5: e_tri port map (iCS, ChOr, D_out);
	D_out <= ChOr when iCS='0' else 'Z';
	u60: e_shift_out15 port map (SCLK, iRst, ChEn(0), ch0, "000", ChOut(0));
	u61: e_shift_out15 port map (SCLK, iRst, ChEn(1), ch1, "001", ChOut(1));
	u62: e_shift_out15 port map (SCLK, iRst, ChEn(2), ch2, "010", ChOut(2));
	u63: e_shift_out15 port map (SCLK, iRst, ChEn(3), ch3, "011", ChOut(3));
	u64: e_shift_out15 port map (SCLK, iRst, ChEn(4), ch4, "100", ChOut(4));
	u65: e_shift_out15 port map (SCLK, iRst, ChEn(5), ch5, "101", ChOut(5));
	u66: e_shift_out15 port map (SCLK, iRst, ChEn(6), ch6, "110", ChOut(6));
	u67: e_shift_out15 port map (SCLK, iRst, ChEn(7), ch7, "111", ChOut(7));

end emul_arch;