----------------------------------------------------------------------------------
-- Company: University of Connecticut
-- Engineer: Brendan Krueger
-- 
-- Create Date:    11:27:12 07/13/2007 
-- Design Name: Shift-Out Register for ADC Emulator
-- Module Name:    e_shift_out15 - e_shift_out15_arch 
-- Project Name: ADC Module
-- Target Devices: none; for testing and simulation only
-- Tool versions: Xilinx ISE WebPACK 9.1.03i
-- Description: 15-bit shift-out register with asynchronous, active-low reset
--		and shift/load toggle; loads address (3 bits) and data (12 bits) then
--		shifts out along serial data line
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity e_shift_out15 is
    Port ( Clk : in  STD_LOGIC;
           iRst : in  STD_LOGIC;
           Sh_Ld : in  STD_LOGIC;
           D : in  STD_LOGIC_VECTOR (11 downto 0);
           A : in  STD_LOGIC_VECTOR (14 downto 12);
           Q : out  STD_LOGIC
	 );
end e_shift_out15;

architecture e_shift_out15_arch of e_shift_out15 is

	signal reg : STD_LOGIC_VECTOR (14 downto 0);
	signal line : STD_LOGIC;

begin

	shift : process (Clk, iRst, Sh_Ld)
	begin
		if (iRst = '0') then
			reg <= "000000000000000";
			line <= '0';
		else
			if (rising_edge(Clk)) then
				if (Sh_Ld = '1') then
					line <= reg(14);
					for i in 0 to 13 loop
						reg(i+1) <= reg(i);
					end loop;
					reg(0) <= '0';
				else
					reg (14 downto 12) <= A;
					reg (11 downto 0) <= D;
					line <= '0';
				end if;
			else
				reg <= reg;
				line <= line;
			end if;
		end if;
	end process shift;
	
	Q <= line;

end e_shift_out15_arch;