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-- Company: University of Connecticut
-- Engineer: Brendan Krueger
-- 
-- Create Date:    10:34:07 07/13/2007 
-- Design Name: Shift-In Register for ADC Emulator
-- Module Name:    e_shift_in16 - e_shift_in16_arch 
-- Project Name: ADC Module
-- Target Devices: none; for testing and simulation only
-- Tool versions: Xilinx ISE WebPACK 9.1.03i
-- Description: 16-bit shift-in register with asynchronous reset and shift
--		enable; custom outputs to select write bit and data bits; shifts in all
--		16 cycles of transfer, but only uses 12 MSB (4 bits of padding ignored)
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity e_shift_in16 is
    Port ( Clk : in  STD_LOGIC;
           iRst : in  STD_LOGIC;
           En : in  STD_LOGIC;
           D : in  STD_LOGIC;
           Q_W : out  STD_LOGIC;
           Q_D : out  STD_LOGIC_VECTOR (10 downto 0)
	 );
end e_shift_in16;

architecture e_shift_in16_arch of e_shift_in16 is

	signal reg : STD_LOGIC_VECTOR (15 downto 0);

begin

	shift : process (Clk, iRst, En)
	begin
		if (iRst = '0') then
			reg <= "0000000000000000";
		else
			if (rising_edge(Clk)) then
				if (En = '1') then
					for i in 0 to 14 loop
						reg(i+1) <= reg(i);
					end loop;
					reg(0) <= D;
				else
					reg <= reg;
				end if;
			else
				reg <= reg;
			end if;
		end if;
	end process shift;
	
	Q_W <= reg(15);
	Q_D <= reg(14 downto 4);

end e_shift_in16_arch;