----------------------------------------------------------------------------------
-- Company: University of Connecticut
-- Engineer: Brendan Krueger
-- 
-- Create Date:    11:21:04 07/13/2007 
-- Design Name:	   Error Flag for ADC Emulator
-- Module Name:    e_error - e_error_arch 
-- Project Name:   ADC Module
-- Target Devices: none; for testing and simulation only
-- Tool versions: Xilinx ISE WebPACK 9.1.03i
-- Description: Raises an error flag if the bits of the control register form
--		an invalid sequence: d00ddd11000 is valid (d = don't care; 0 or 1)
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity e_error is
    port ( D : in  STD_LOGIC_VECTOR (7 downto 0);
           Err : out  STD_LOGIC
	 );
end e_error;

architecture e_error_arch of e_error is
begin

	Err <= not (not D(7) and not D(6) and D(5) and D(4) and
                    not D(3) and not D(2) and not D(1) and not D(0));

end e_error_arch;