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-- Company: University of Connecticut
-- Engineer: Brendan Krueger
-- 
-- Create Date:    11:07:47 07/13/2007 
-- Design Name:    3-to-8 Demultiplexer for ADC Emulator
-- Module Name:    e_demux - e_demux_arch 
-- Project Name:   ADC Module
-- Target Devices: none; for testing and simulation only
-- Tool versions: Xilinx ISE WebPACK 9.1.03i
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity e_demux is
    port ( D : in  STD_LOGIC;
           S : in  STD_LOGIC_VECTOR (2 downto 0);
           Q : out  STD_LOGIC_VECTOR (7 downto 0)
	 );
end e_demux;

architecture e_demux_arch of e_demux is

begin

	Q(0) <= D and not S(2) and not S(1) and not S(0);
	Q(1) <= D and not S(2) and not S(1) and S(0);
	Q(2) <= D and not S(2) and S(1) and not S(0);
	Q(3) <= D and not S(2) and S(1) and S(0);
	Q(4) <= D and S(2) and not S(1) and not S(0);
	Q(5) <= D and S(2) and not S(1) and S(0);
	Q(6) <= D and S(2) and S(1) and not S(0);
	Q(7) <= D and S(2) and S(1) and S(0);

end e_demux_arch;