----------------------------------------------------------------------------------
-- Company: University of Connecticut
-- Engineer: Brendan Krueger
-- 
-- Create Date:    11:02:48 07/13/2007 
-- Design Name:    Control Register for ADC Emulator
-- Module Name:    e_creg - e_creg_arch 
-- Project Name:   ADC Module
-- Target Devices: none; for testing and simulation only
-- Tool versions: Xilinx ISE WebPACK 9.1.03i
-- Description: 11-bit register with asychronous, active-low reset and load enable
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity e_creg is
    Port ( Clk : in  STD_LOGIC;
           iRst : in  STD_LOGIC;
           En : in  STD_LOGIC;
           D : in  STD_LOGIC_VECTOR (10 downto 0);
           Q : out  STD_LOGIC_VECTOR (10 downto 0)
	 );
end e_creg;

architecture e_creg_arch of e_creg is

	signal reg : STD_LOGIC_VECTOR (10 downto 0);

begin

	creg : process (Clk, iRst, En)
	begin
		if (iRst = '0') then
			reg <= "00000000000";
		else
			if (rising_edge(Clk)) then
				if (En = '1') then
					reg <= D;
				else
					reg <= reg;
				end if;
			else
				reg <= reg;
			end if;
		end if;
	end process creg;
	
	Q <= reg;

end e_creg_arch;