----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date:    12:28:17 08/07/2009 
-- Design Name: 
-- Module Name:    TS2bit - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity TS2bit is
    Port ( D : in  STD_LOGIC;
           Q : out  STD_LOGIC
	 );
end TS2bit;

architecture Behavioral of TS2bit is

begin

	TS2bit_proc : process (D)
	begin
		if D='1' then
			Q <= '1';
		else
		        Q <= '0';
		end if;
	end process;

end Behavioral;