----------------------------------------------------------------------------------
-- Company: University of Connecticut
-- Engineer: Igor Senderovich
-- 
-- Create Date:  10/30/2007 
-- Design Name:  Generic 8-bit register
-- Module Name:  Reg8bit - Behavioral 
-- Description:  8bit register that records on falling edge of Clk (when Enabled)
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
--use IEEE.STD_LOGIC_ARITH.ALL;
--use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity Reg8bit is
    Port ( Clk : in  STD_LOGIC;
           Rst : in  STD_LOGIC;
           En : in  STD_LOGIC;
           D : in  STD_LOGIC_VECTOR (7 downto 0);
           Q : out  STD_LOGIC_VECTOR (7 downto 0)
	 );
end Reg8bit;

architecture Behavioral of Reg8bit is

	signal Data : STD_LOGIC_VECTOR (7 downto 0);

begin

	Reg8bit : process (Clk, Rst, En)
	begin
		if (Rst = '1') then
			Data <= "00000000";
		else
			if falling_edge(Clk) then
				if (En = '1') then
					Data <= D;
				else
					Data <= Data;
				end if;
			else
				Data <= Data;
			end if;
		end if;
	end process Reg8bit;

	Q <= Data;

end Behavioral;